JPH0513708A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0513708A JPH0513708A JP3165552A JP16555291A JPH0513708A JP H0513708 A JPH0513708 A JP H0513708A JP 3165552 A JP3165552 A JP 3165552A JP 16555291 A JP16555291 A JP 16555291A JP H0513708 A JPH0513708 A JP H0513708A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- capacitor
- semiconductor substrate
- oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 28
- 239000001301 oxygen Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000000126 substance Substances 0.000 abstract description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000011521 glass Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 9
- 230000015654 memory Effects 0.000 description 9
- 239000010410 layer Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- NKZSPGSOXYXWQA-UHFFFAOYSA-N dioxido(oxo)titanium;lead(2+) Chemical compound [Pb+2].[O-][Ti]([O-])=O NKZSPGSOXYXWQA-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
(57)【要約】
【目的】 強誘電体を用いたキャパシタが、能動素子が
形成された同一半導体基板上に集積された半導体メモリ
において、酸素を含む雰囲気中での熱処理による、素子
特性の劣化を防ぐ。
【構成】 図１において、強誘電体を用いたキャパシタ
の下部電極１０９と、半導体基板１０２との間の層に、
応力を緩和するための膜としてほう素りんガラスの層１
０６を設ける。その膜と前記キャパシタとの間の層に、
前記ほう素りんガラスに開けられた接続孔１０７の側壁
を覆うように、酸素非透過性の膜として窒化珪素の層１
０８を設ける。
(57) [Summary] [Objective] In a semiconductor memory in which a capacitor using a ferroelectric material is integrated on the same semiconductor substrate on which an active element is formed, deterioration of element characteristics due to heat treatment in an atmosphere containing oxygen. prevent. [Structure] In FIG. 1, in a layer between a lower electrode 109 of a capacitor using a ferroelectric substance and a semiconductor substrate 102,
Boron-phosphorus glass layer 1 as a film for relieving stress
06 is provided. On the layer between the film and the capacitor,
A silicon nitride layer 1 as an oxygen impermeable film so as to cover the side wall of the connection hole 107 formed in the boron phosphorus glass.
08 is provided.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、強誘電体を用いた、半
導体装置の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device using a ferroelectric material.
【０００２】[0002]
【発明の概要】本発明は、強誘電体を用いた半導体記憶
装置において、半導体基板と強誘電体キャパシタとの間
に、絶縁性の酸素非透過膜を形成することによって、以
後の酸化雰囲気中での熱処理工程における酸素の拡散を
阻止し、さらに配線電極と半導体基板との接続孔部側壁
の内、前記絶縁性の酸素非透過膜より下部を前記絶縁性
の酸素非透過膜で被覆することによって、前記接続後部
側壁からの酸素の拡散をも阻止し、前記絶縁性の酸素非
透過膜より下層に位置する素子の、酸素による特性劣化
を防ぐことができる。SUMMARY OF THE INVENTION According to the present invention, in a semiconductor memory device using a ferroelectric substance, an insulating oxygen non-permeable film is formed between a semiconductor substrate and a ferroelectric capacitor, so that it can be used in an oxidizing atmosphere thereafter. Of oxygen diffusion in the heat treatment step in step (4), and further covering the insulating oxygen non-permeable film below the insulating oxygen non-permeable film in the side wall of the connection hole between the wiring electrode and the semiconductor substrate. Thus, it is possible to prevent oxygen from diffusing from the side wall of the rear portion of the connection, and to prevent deterioration of characteristics of the element located below the insulating oxygen impermeable film due to oxygen.
【０００３】[0003]
【従来の技術】従来の半導体不揮発性メモリとしては、
絶縁ゲート中のトラップまたは浮遊ゲートにシリコン基
板からの電荷を注入することによりシリコン基板の表面
ポテンシャルが変調される現象を用いた、ＭＩＳ型トラ
ンジスタが一般的に使用されており、ＥＰＲＯＭ（紫外
線消去型不揮発性メモリ）やＥＥＰＲＯＭ（電気的書換
え可能型不揮発性メモリ）などとして実用化されてい
る。2. Description of the Related Art As a conventional semiconductor nonvolatile memory,
A MIS transistor, which uses a phenomenon in which a surface potential of a silicon substrate is modulated by injecting charges from the silicon substrate into a trap or a floating gate in an insulated gate, is generally used, and an EPROM (UV erasing type) is used. Non-volatile memory), EEPROM (electrically rewritable non-volatile memory) and the like have been put to practical use.
【０００４】[0004]
【発明が解決しようとする課題】しかしこれらの不揮発
性メモリは、情報の書換え電圧が、通常２０Ｖ前後と高
いことや、書換え時間が非常に長い（例えばＥＥＰＲＯ
Ｍの場合数十ｍｓｅｃ）等の欠点を有する。また、情報
の書換え回数が、約１０2回程度であり、非常に少な
く、繰り返し使用する場合には問題が多い。However, in these nonvolatile memories, the rewriting voltage of information is usually as high as about 20V, and the rewriting time is very long (for example, EEPRO).
In the case of M, it has a defect such as several tens of msec). In addition, the number of times of rewriting information is about 10 2 times, which is very small, and there are many problems when repeatedly used.
【０００５】電気的に分極が反転可能である強誘電体を
用いた、不揮発性メモリについては、書き込み時間と、
読みだし時間が原理的にほぼ同じであり、また電源を切
っても分極は保持されるため、理想的な不揮発性メモリ
となる可能性を有する。この様な強誘電体を用いた不揮
発性メモリについては、例えば米国特許４１４９３０２
のように、シリコン基板上に強誘電体からなるキャパシ
タを集積した構造や、米国特許３８３２７００のように
ＭＩＳ型トランジスタのゲート部分に強誘電体膜を配置
した不揮発性メモリなどの提案がなされている。また、
最近では図２のようなＭＯＳ型半導体装置に積層した構
造の不揮発性メモリがＩＥＤＭ’８７ｐｐ．８５０−８
５１に提案されている。For a non-volatile memory using a ferroelectric material whose polarization is electrically reversible, write time and
In principle, the read times are almost the same, and the polarization is retained even when the power is turned off, so there is a possibility that it will be an ideal non-volatile memory. A nonvolatile memory using such a ferroelectric substance is disclosed in, for example, US Pat. No. 4,149,302.
As described above, a structure in which a capacitor made of a ferroelectric material is integrated on a silicon substrate, and a non-volatile memory in which a ferroelectric film is arranged in the gate portion of a MIS transistor as in US Pat. No. 3,832,700 have been proposed. . Also,
Recently, a nonvolatile memory having a structure stacked on a MOS type semiconductor device as shown in FIG. 850-8
51 have been proposed.
【０００６】図２において、２０１はＰ型Ｓｉ基板であ
り、２０２は素子分離用のＬＯＣＯＳ酸化膜、２０３は
ソースとなるＮ型拡散層であり、２０４はドレインとな
るＮ型拡散層である。２０５ゲート電極であり、２０６
は層間絶縁膜である。２０７が強誘電体膜であり、電極
２０８と２０９により挟まれ、キャパシタを構成してい
る。２１０は第２層間絶縁膜であり、２１１が配線電極
となるＡｌである。In FIG. 2, 201 is a P-type Si substrate, 202 is a LOCOS oxide film for element isolation, 203 is an N-type diffusion layer serving as a source, and 204 is an N-type diffusion layer serving as a drain. 205 is a gate electrode, and 206
Is an interlayer insulating film. A ferroelectric film 207 is sandwiched between electrodes 208 and 209 to form a capacitor. 210 is a second interlayer insulating film, and 211 is Al that serves as a wiring electrode.
【０００７】この様にＭＯＳ型半導体装置の上部に強誘
電体膜を積層した構造では、酸化雰囲気中での熱処理の
際に、半導体素子中に酸素が拡散し、素子特性を劣化さ
せるという課題を有する。As described above, in the structure in which the ferroelectric film is laminated on the upper part of the MOS type semiconductor device, oxygen is diffused into the semiconductor element during the heat treatment in the oxidizing atmosphere, which deteriorates the element characteristics. Have.
【０００８】そこで本発明はこのような課題を解決する
もので、その目的とするところは、半導体素子中への酸
素の拡散を阻止し、それによる素子特性の劣化を防止す
ることによって、優れた半導体装置を提供することにあ
る。Therefore, the present invention solves such a problem, and an object of the present invention is to prevent oxygen from diffusing into a semiconductor element and prevent deterioration of element characteristics due to the oxygen diffusion. It is to provide a semiconductor device.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置は、
強誘電体を用いたキャパシタが、能動素子が形成された
同一半導体基板上に集積された半導体装置において、前
記半導体基板と前記キャパシタとの間の層に、絶縁性の
酸素非透過膜を有し、前記絶縁性の酸素非透過膜と、前
記半導体基板との間の層に、応力緩和膜を有し、前記絶
縁性の酸素非透過膜が、前記絶縁性の酸素非透過膜より
上部にある配線電極と、前記半導体基板とを接続するべ
き、接続孔部側壁において、前記絶縁性の酸素非透過膜
より下部を被覆し、前記絶縁性の酸素非透過膜が、窒化
珪素を主成分とし、前記応力緩和膜が、二酸化珪素を主
成分とすることを特徴とする。The semiconductor device of the present invention comprises:
In a semiconductor device in which a capacitor using a ferroelectric material is integrated on the same semiconductor substrate on which an active element is formed, an insulating oxygen-impermeable film is provided in a layer between the semiconductor substrate and the capacitor. A stress relaxation film is provided in a layer between the insulating oxygen-impermeable film and the semiconductor substrate, and the insulating oxygen-impermeable film is located above the insulating oxygen-impermeable film. In order to connect the wiring electrode and the semiconductor substrate, in the side wall of the connection hole portion, the lower part of the insulating oxygen non-permeable film is covered, and the insulating oxygen non-permeable film contains silicon nitride as a main component, The stress relaxation film is characterized by containing silicon dioxide as a main component.
【００１０】[0010]
【実施例】図１（ａ）は、本発明の半導体装置の一実施
例における主要断面図であり、図１（ｂ）は前記実施例
における主要平面図である。以下、図１にしたがい、本
発明の半導体装置を説明する。ここでは説明の都合上Ｓ
ｉ基板を用い、Ｎチャンネルトランジスタを用いた例に
つき説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a main sectional view of an embodiment of a semiconductor device of the present invention, and FIG. 1B is a main plan view of the embodiment. The semiconductor device of the present invention will be described below with reference to FIG. Here, for convenience of explanation, S
An example using an i substrate and an N channel transistor will be described.
【００１１】１０１はＰ型Ｓｉ基板であり、例えば２０
Ω・ｃｍの比抵抗のウェハを用いる。１０２は素子分離
用の絶縁膜であり、例えば、従来技術であるＬＯＣＯＳ
法により酸化膜を６０００Å形成する。１０３はソース
となるＮ型拡散層であり、例えばリンを８０ｋｅＶ５×
１０15ｃｍー2イオン注入することによって形成する。１
０４はドレインとなるＮ型拡散層であり、１０３と同時
に形成する。１０５はゲート電極であり、例えばリンで
ドープされたポリシリコンを用いる。１０６は請求項２
の主旨による応力緩和膜であり、例えば化学的気相成長
法によりリン及び、ホウ素を含む二酸化珪素を４０００
Å形成する。その後、１０３、１０４などの高濃度拡散
層、及び、１０５などのゲート電極と、それより上層に
位置する配線電極とが接続されるべき部位の応力緩和膜
１０６に、フォト・リソグラフィ技術を用いて、接続孔
１０７を形成する。Reference numeral 101 is a P-type Si substrate, for example, 20
A wafer having a specific resistance of Ω · cm is used. 102 is an insulating film for element isolation, for example, LOCOS which is a conventional technique.
An oxide film of 6000Å is formed by the method. Reference numeral 103 is an N-type diffusion layer which serves as a source, and is made of, for example, phosphorus of 80 keV5 ×
It is formed by implanting 10 15 cm −2 ions. 1
Reference numeral 04 denotes an N-type diffusion layer which will be a drain and is formed simultaneously with 103. Reference numeral 105 denotes a gate electrode, which uses, for example, polysilicon doped with phosphorus. 106 is claim 2
Is a stress relaxation film according to the gist of, for example, by chemical vapor deposition, silicon dioxide containing phosphorus and boron is added to 4000
Å Form. After that, a photolithography technique is used for the stress relaxation film 106 at the site where the high-concentration diffusion layers such as 103 and 104, and the gate electrodes such as 105, and the wiring electrodes located thereabove are to be connected. , The connection hole 107 is formed.
【００１２】１０８は請求項１の主旨による絶縁性の酸
素非透過膜であり、窒化珪素をスパッタ法により、１０
００Å形成する。Reference numeral 108 denotes an insulating oxygen-impermeable film according to the subject matter of claim 1, which is formed by sputtering silicon nitride by sputtering.
00Å Form.
【００１３】１０９は強誘電体膜を挟む一方の電極であ
り、例えばＰｔをスパッタ法により、１０００Å形成す
る。１１０は強誘電体膜であり、例えばチタン酸鉛をゾ
ル・ゲル法により、２０００Å形成した後、５００℃の
酸素雰囲気中で焼結する。１１１は強誘電体膜を挟む、
もう一方の電極であり、１０９と同様にして形成する。
１１２は層間絶縁膜であり、例えば化学的気相成長法に
より二酸化珪素を４０００Å形成した後、従来からの技
術である、フォト・リソグラフィによって、接続孔１１
３を形成する。この時、図１（ｂ）に示すように、接続
孔１１３を接続孔１０７より小さくすることによって、
酸素非透過膜１０８より下層に位置する応力緩和膜１０
６の接続孔側壁が、酸素非透過膜１０８で被覆されるこ
とになり、請求項３の主旨による構造を得ることができ
る。Numeral 109 is one of the electrodes sandwiching the ferroelectric film, and for example, Pt is formed to a thickness of 1000 by sputtering. Reference numeral 110 denotes a ferroelectric film, for example, lead titanate is formed to 2000 Å by a sol-gel method and then sintered in an oxygen atmosphere at 500 ° C. 111 sandwiches the ferroelectric film,
The other electrode, which is formed in the same manner as 109.
Reference numeral 112 denotes an interlayer insulating film, which is formed by forming chemical vapor deposition method such as 4000 Å of silicon dioxide and then forming the connection hole 11 by photolithography which is a conventional technique.
3 is formed. At this time, by making the connection hole 113 smaller than the connection hole 107, as shown in FIG.
The stress relaxation film 10 located below the oxygen impermeable film 108.
The side wall of the connection hole 6 is covered with the oxygen impermeable film 108, and the structure according to the gist of claim 3 can be obtained.
【００１４】１１４は配線電極であり、例えば、アルミ
ニウムをスパッタ法により、５０００Å形成し、所定の
パターンを形成する。Reference numeral 114 is a wiring electrode, for example, aluminum is formed by sputtering to a thickness of 5000 Å to form a predetermined pattern.
【００１５】以上をもって、本実施例の構造を得る。The structure of this embodiment is obtained as described above.
【００１６】このような構造にすることによって、酸素
非透過膜１０８形成以後の酸素雰囲気中での熱処理によ
る、酸素の基板への拡散は阻止され、また、接続孔側壁
からの酸素の拡散をも阻止することができる。With such a structure, diffusion of oxygen into the substrate due to heat treatment in the oxygen atmosphere after formation of the oxygen impermeable film 108 is prevented, and diffusion of oxygen from the side wall of the contact hole is also prevented. Can be stopped.
【００１７】さて、図１（ａ）において、酸素非透過膜
１０８がない場合、チタン酸鉛の焼結時に、７００℃の
酸素中での熱処理を行うと、Ｎチャンネル型のＭＯＳト
ランジスタのドレイン漏れ電流は、ドレイン電圧５Ｖ時
において、約１０-7Ａであったが、本実施例の構造とし
た場合、同様な熱処理を加えても、ドレイン漏れ電流は
約１０-11Ａであった。Now, in FIG. 1A, in the case where the oxygen impermeable film 108 is not provided, if a heat treatment in oxygen at 700 ° C. is performed during the sintering of lead titanate, the drain leakage of the N-channel type MOS transistor is caused. The current was about 10 −7 A when the drain voltage was 5 V, but in the case of the structure of this example, the drain leakage current was about 10 −11 A even when the similar heat treatment was applied.
【００１８】[0018]
【発明の効果】本発明によれば、能動素子が形成された
半導体基板上に導電性の酸素非透過膜を形成したことに
より、それ以後の工程における酸化雰囲気中での熱処理
の際の、半導体基板中への酸素の拡散が阻止され、それ
による素子特性の劣化を防止できるという効果を有す
る。According to the present invention, a conductive oxygen-impermeable film is formed on a semiconductor substrate on which an active element is formed, so that the semiconductor during heat treatment in an oxidizing atmosphere in the subsequent steps is formed. Oxygen is prevented from diffusing into the substrate, and the device characteristics can be prevented from deteriorating.
【図１】本発明の実施例による、半導体装置の主要断面
図、及び主要平面図。FIG. 1 is a main sectional view and a main plan view of a semiconductor device according to an embodiment of the present invention.
【図２】従来の技術による、半導体記憶装置の主要断面
図。FIG. 2 is a main cross-sectional view of a semiconductor memory device according to a conventional technique.
１０１ シリコン基板 １０２ 素子分離膜 １０３ ソース領域 １０４ ドレイン領域 １０５ ゲート電極 １０６ 応力緩和膜 １０７ 接続孔 １０８ 絶縁性の酸素非透過膜 １０９ 下部電極 １１０ 強誘電体膜 １１１ 上部電極 １１２ 層間絶縁膜 １１３ 接続孔 １１４ 配線電極 ２０１ シリコン基板 ２０２ 素子分離膜 ２０３ ソース領域 ２０４ ドレイン領域 ２０５ ゲート電極 ２０６ 第１層間絶縁膜 ２０７ 強誘電体膜 ２０８ 下部電極 ２０９ 上部電極 ２１０ 第２層間絶縁膜 ２１１ 配線電極 101 Silicon substrate 102 element isolation film 103 source area 104 drain region 105 gate electrode 106 stress relaxation film 107 connection hole 108 Insulating oxygen impermeable membrane 109 Lower electrode 110 Ferroelectric film 111 upper electrode 112 Interlayer insulation film 113 connection hole 114 wiring electrode 201 Silicon substrate 202 element isolation film 203 Source area 204 drain region 205 gate electrode 206 First interlayer insulating film 207 Ferroelectric film 208 Lower electrode 209 upper electrode 210 second interlayer insulating film 211 wiring electrode
Claims (5)
子が形成された同一半導体基板上に集積された半導体装
置において、前記半導体基板と前記キャパシタとの間の
層に、少なくとも絶縁性の酸素非透過膜の層を含むこと
を特徴とする半導体装置。1. In a semiconductor device in which a capacitor using a ferroelectric material is integrated on the same semiconductor substrate on which an active element is formed, at least insulating oxygen is provided in a layer between the semiconductor substrate and the capacitor. A semiconductor device comprising a layer of a non-transmissive film.
子が形成された同一半導体基板上に集積された半導体装
置において、前記絶縁性の酸素非透過膜と、前記半導体
基板との間の層に、応力緩和膜を有することを特徴とす
る、請求項１記載の半導体装置。2. A semiconductor device in which a capacitor using a ferroelectric is integrated on the same semiconductor substrate on which an active element is formed, and a layer between the insulating oxygen-impermeable film and the semiconductor substrate. The semiconductor device according to claim 1, further comprising a stress relaxation film.
子が形成された同一半導体基板上に集積された半導体装
置において、前記絶縁性の酸素非透過膜が、前記絶縁性
の酸素非透過膜より上部にある配線電極と、前記半導体
基板とを接続するべき、接続孔部側壁において、前記絶
縁性の酸素非透過膜より下部を被覆することを特徴とす
る、請求項１及び２記載の半導体装置。3. A semiconductor device in which a capacitor using a ferroelectric material is integrated on the same semiconductor substrate on which an active element is formed, wherein the insulating oxygen non-permeable film is the insulating oxygen non-permeable film. 3. The semiconductor according to claim 1, wherein the side wall of the connection hole, which should connect the wiring electrode on the upper side to the semiconductor substrate, covers the lower side of the insulating oxygen-impermeable film. apparatus.
子が形成された同一半導体基板上に集積された半導体装
置において、前記絶縁性の酸素非透過膜が、窒化珪素を
主成分とすることを特徴とする、請求項１、２及び３記
載の半導体装置。4. A semiconductor device in which a capacitor using a ferroelectric material is integrated on the same semiconductor substrate on which an active element is formed, and the insulating oxygen-impermeable film contains silicon nitride as a main component. The semiconductor device according to claim 1, 2 or 3, characterized in that.
子が形成された同一半導体基板上に集積された半導体装
置において、前記応力緩和膜が、二酸化珪素を主成分と
することを特徴とする、請求項２記載の半導体装置。5. A semiconductor device in which a capacitor using a ferroelectric material is integrated on the same semiconductor substrate on which active elements are formed, and the stress relaxation film contains silicon dioxide as a main component. The semiconductor device according to claim 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3165552A JPH0513708A (en) | 1991-07-05 | 1991-07-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3165552A JPH0513708A (en) | 1991-07-05 | 1991-07-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0513708A true JPH0513708A (en) | 1993-01-22 |
Family
ID=15814541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3165552A Pending JPH0513708A (en) | 1991-07-05 | 1991-07-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0513708A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5953619A (en) * | 1997-08-06 | 1999-09-14 | Fujitsu Limited | Semiconductor device with perovskite capacitor and its manufacture method |
-
1991
- 1991-07-05 JP JP3165552A patent/JPH0513708A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5953619A (en) * | 1997-08-06 | 1999-09-14 | Fujitsu Limited | Semiconductor device with perovskite capacitor and its manufacture method |
| US6307228B1 (en) | 1997-08-06 | 2001-10-23 | Fujitsu Limited | Semiconductor device with perovskite capacitor and its manufacture method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04158570A (en) | Structure of semiconductor device and manufacture thereof | |
| JP3092140B2 (en) | Method for manufacturing semiconductor device | |
| US5369296A (en) | Semiconductor device having a ferroelectric film in a through-hole | |
| JPH0864706A (en) | Method of manufacturing nonvolatile semiconductor memory device | |
| EP0495114A1 (en) | Semiconductor device | |
| JPH0590606A (en) | Semiconductor device | |
| JPH0513708A (en) | Semiconductor device | |
| JP3120477B2 (en) | Semiconductor device | |
| JP3111416B2 (en) | Semiconductor device | |
| JP3079542B2 (en) | Method for manufacturing semiconductor device | |
| JPH03142973A (en) | Semiconductor storage device | |
| JPH0319372A (en) | Semiconductor device | |
| JP3387850B2 (en) | Method for manufacturing semiconductor device | |
| WO1992002047A1 (en) | Semiconductor device and its manufacturing method | |
| JP3270020B2 (en) | Semiconductor device | |
| WO1992007383A1 (en) | Semiconductor device | |
| JP3345781B2 (en) | Method for manufacturing semiconductor device | |
| JP3008495B2 (en) | Semiconductor device | |
| JPH11330275A (en) | Semiconductor device and manufacturing method thereof | |
| JPH08148589A (en) | Semiconductor device and manufacturing method thereof | |
| JPH04196485A (en) | semiconductor equipment | |
| JPH02307275A (en) | Semiconductor device | |
| JPH04137662A (en) | Semiconductor device | |
| JP2000082793A (en) | Method for manufacturing semiconductor device | |
| JPH0493065A (en) | Structure of semiconductor device |