JPH05137320A - Voltage generation circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Switches Q1 and Q2 are turned on, Q3 and Q4 are turned off to charge capacitor C1 with DC input voltage VIN, and then switches Q1 and Q2 are turned off and Q3 and Q4 are turned on. In the voltage doubler generation circuit that repeats the operation of charging the capacitor C2 with the series voltage of the input voltage VIN and the voltage of the capacitor C1, conventionally, the switches Q1 to Q are irrelevant regardless of the state of the load RL.
Since the above-mentioned opening / closing operation of No. 4 is performed at a constant cycle, it is possible to improve the fact that the circuit loss occurs even in the unloaded state of the load RL. The comparator CP2 detects that the voltage of the capacitor C2 falls below a predetermined level e4, and turns off the switches Q3 and Q4 and turns on Q1 and Q2 via the control circuit 3. Next, in the comparator CP1, the voltage of the capacitor C1 reaches a predetermined level e2.
Is detected, and switches Q3 and Q4 are turned on,
By turning off Q1 and Q2, the switching frequency of the switches Q1 to Q4 is changed according to the state of the load RL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage generating circuit for boosting or reducing an input DC voltage via a capacitance and a switch. In the following figures, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a conventional voltage generating circuit of this type. This circuit consists of FET switches Q1-
It is composed of Q4 and capacitances C1 and C2. VIN is the DC input voltage to this circuit, VOUT
Is the output voltage from this circuit and RL is the load. In this example, the output voltage VOU obtained by boosting the input voltage VIN by about 2 times
In the case where T is obtained, φ1 is a charge signal as a drive signal for the switches Q1 and Q2, and φ2 is a switch Q3 and Q.
4 is a boosting signal as a drive signal for 4. Also 1,
Reference numerals 2 are terminals (connection points) on the high voltage side and the low voltage side of the capacitance C1, respectively.

The operation of FIG. 3 will be described. First, the switches Q1 and Q2 are closed (however, the switches Q3 and Q2 are closed).
4 is off), the capacitance C1 is also the DC input voltage VIN
Charge at. Next, when the switches Q1 and Q2 are opened and the switch Q3 is closed, the low voltage side terminal 2 of the capacitance C1.
Is connected to the input voltage VIN and this capacitance C1
The high-voltage side terminal 1 of is boosted to about twice the input voltage VIN. At this time, when the switch Q4 is closed at the same timing as the switch Q3, the voltage charges the capacitance C2. By repeating the above operation, the output voltage VOUT as the voltage across the capacitance C2 is finally VIN.
Is charged to a voltage twice as high as the above voltage and supplied to the load RL.

FIG. 4 shows operation waveforms of each part of FIG. Figure 4
As shown in FIG. 3, the circuit of FIG. 3 operates at the two-phase timing of the charging signal φ1 and the boosting signal φ. And charging signal φ1
Indicates the timing for charging the capacitance C1, and the boosting signal φ2 provides the timing for boosting and transferring the charge to the capacitance C2. In addition, 1, 2 and V in FIG.
The waveforms of OUT are the waveforms of the high voltage side and low voltage side terminals of the capacitance C1 and the high voltage side terminal of the capacitance C2, respectively.

[0005]

By the way, in FIG. 3, the timing pulses .phi.1 and .phi.2 are arbitrarily generated in advance by the oscillator, and no consideration is given to the fluctuation of the load RL. That is, the clocks of φ1 and φ2 operate at a predetermined frequency regardless of whether there is no load or a high load, in other words, the charge / discharge switches Q1 to Q4 of the capacitances C1 and C2 are always operating.

However, considering the power saving of the circuit system or the battery drive, it is desirable to cut off the power supply to the circuit blocks which are not used temporarily. This is because the load disappears when viewed from the power supply. Therefore, according to the present invention, the switch Q is changed according to the change of the load RL.
An object of the present invention is to provide a voltage generating circuit that can change the operation timings of 1 to Q4 and can always suppress the circuit loss to a necessary minimum.

[0007]

In order to solve the above-mentioned problems, a direct current power supply is provided for a first capacitance (C1 etc.) and first and second terminals (1, 2, etc.) as both ends of this capacitance. One end was connected to the first electrode and the second switch (Q1, Q2, etc.) respectively connected to the first and second electrodes as both electrodes of the input voltage VIN, etc., and the second electrode of the DC power supply. A second capacitance (such as C2),
A third switch (such as Q3) that connects the second terminal of the first capacitance to the first electrode of the DC power supply.
And a first terminal of the first capacitance to the second terminal
The fourth switch (Q
4)) and a first state in which the first and second switches are turned on and the third and fourth switches are turned off, and the first and second switches are turned off and the third and fourth switches are turned on. In the voltage generating circuit which alternately repeats the ON second state of the switch and generates a voltage in the second capacitance that is approximately twice the voltage of the DC power supply, in the first state, the first Switching control means (control circuit 3 or the like) for determining that the voltage of the capacitance of 1 has exceeded a first predetermined level (e2 or the like) and switching to the second state.
And in the second state, it is determined that the voltage of the first or second capacitance has dropped below a second predetermined level (e4 or the like) corresponding to each capacitance, and the state is switched to the first state. And a second switching control means (control circuit 3 and the like),

The first, second, third and fourth switches are each composed of an FET, and

The first switching control means includes a comparator (CP1 or the like) for comparing the voltage of the first capacitance with a first predetermined level, and the second switching control means is the first or, A comparator (CP2 or the like) for comparing the voltage of the second capacitance with a second predetermined level is provided.

[0010]

Function: A means for monitoring the potentials of the terminals of the capacitances C1 and C2 is provided, and the switches Q1 to Q4 are provided according to the load fluctuation.
By varying the operating frequency of the switch (that is, by stopping the operation of the switches Q1 to Q4 if there is no load (actually, it is an extremely low frequency due to leakage, etc.), the power saving of the switch operation is achieved. Is.

[0011]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration as an embodiment of the present invention and corresponds to FIG. 1, in contrast to FIG. 3, comparators CP1 and CP2 that monitor the potentials of the high voltage side terminals of the capacitances C1 and C2, respectively, and a control circuit 3 that controls the output timing of the charging signal φ1 and the boosting signal φ2 by the comparison output thereof. Has been added.

To describe the operation of FIG. 1, the control circuit 3 monitors the discharge state of the capacitance C2 by the comparator CP2, and when the output voltage VOUT becomes lower than the set level of e4, the boost signal φ2 is turned off and the charge signal φ1 is turned on. To do. Signal φ
By turning on 1, the capacitance C1 starts to be charged with the input voltage VIN. Here, in this embodiment, the charge state of the capacitance C1 is further monitored by the comparator CP1. In a switch such as an FET, the capacitance charging time varies depending on its ON resistance. When the control circuit 3 detects that the potential of the high-voltage side terminal 1 of the capacitance C1 becomes larger than the set potential e2 in the ON region of the signal φ1 via the comparator CP1, it determines that the charging is completed, and the charging is completed. The signal φ1 is turned off and the boosting signal φ2 is turned on.

FIG. 2 shows the operation waveforms of the respective parts of FIG. 1, and this FIG. 2 also corresponds to FIG. In the embodiment of FIG. 1, charge detection of the capacitance C1 is detected at its terminal 1,
Although the discharge detection of the capacitance is performed at the output voltage point VOUT, the charge of the capacitance C1 can also be detected at the terminal 2 thereof. That is, as shown in FIG. 2, when the charging signal φ1 is in the ON region and the terminal 2 becomes equal to or lower than the potential e3, it may be determined that the charging is completed. Similarly, with respect to capacitance discharge detection, in the region where the switch Q4 is on (that is, the signal φ2 is on), the connection point 1
You may monitor the electric potential fall of with a comparator. In FIG. 2, this comparison level is indicated by the potential e1.

[0014]

In the conventional voltage generating circuit, the switches Q1 to Q4 are always operated at a constant frequency. Therefore, the oscillating circuit for the switching signals φ1 and φ2 of the switches and the switches Q1 to Q4.
According to the present invention, the switch open / close signals φ1 and φ2 are output by monitoring the charge / discharge of the capacitance.
The frequency changes due to fluctuations in the load RL, and if there is no load and no discharge, the operation stops with the signal φ2 being on. Therefore, the control circuit 3 is composed of CMOS or the like, and the comparator CP1,
By configuring CP2 as an FET and utilizing the threshold voltage and the like, the power consumption under no load can be approached to zero without limit.

[Brief description of drawings]

FIG. 1 is a circuit diagram as an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of each part in FIG.

FIG. 3 is a conventional circuit diagram corresponding to FIG.

FIG. 4 is an operation waveform diagram of each part of FIG.

[Explanation of symbols]

 Q1 switch Q2 switch Q3 switch Q4 switch C1 capacitance C2 capacitance φ1 charge signal φ2 boost signal CP1 comparator CP2 comparator 1 capacitance C1 high voltage side terminal (connection point) 2 capacitance C1 low voltage side terminal (connection point) 3 control Circuit VIN Input DC voltage VOUT Output voltage e1 Comparison setting voltage e2 Comparison setting voltage e3 Comparison setting voltage e4 Comparison setting voltage

Claims (3)

[Claims] 1. A first capacitance, and first and second switches for connecting first and second terminals as both ends of this capacitance to first and second electrodes as both poles of a DC power supply, respectively. A second capacitance having one end connected to a second electrode of the DC power supply; a third switch connecting a second terminal of the first capacitance to the first electrode of the DC power supply; A fourth switch for connecting a first terminal of the first capacitance to the other end of the second capacitance, and turning on the first and second switches and turning off the third and fourth switches. The first state and the second state in which the first and second switches are turned off and the third and fourth switches are turned on are alternately repeated, and the second capacitance has approximately the voltage of the DC power supply. Generate twice the voltage In the pressure generating circuit, in the first state, first switching control means for determining that the voltage of the first capacitance exceeds a first predetermined level and switching to the second state; In the second state, the voltage of the first or second capacitance corresponds to each of the second capacitances.
And a second switching control means for switching to the first state when it is determined that the voltage has dropped below a predetermined level. 2. The voltage generating circuit according to claim 1,
The first, second, third and fourth switches are respectively FE
A voltage generation circuit comprising T. 3. The voltage generating circuit according to claim 1 or 2, wherein the first switching control means includes a comparator for comparing the voltage of the first capacitance with a first predetermined level. 2. The voltage generating circuit, wherein the second switching control means includes a comparator for comparing the voltage of the first or second capacitance with a second predetermined level.