JPH05143206A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH05143206A JPH05143206A JP3305174A JP30517491A JPH05143206A JP H05143206 A JPH05143206 A JP H05143206A JP 3305174 A JP3305174 A JP 3305174A JP 30517491 A JP30517491 A JP 30517491A JP H05143206 A JPH05143206 A JP H05143206A
- Authority
- JP
- Japan
- Prior art keywords
- storage battery
- integrated circuit
- power supply
- battery
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000007599 discharging Methods 0.000 claims abstract description 3
- 230000003252 repetitive effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 3
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
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- Power Sources (AREA)
- Static Random-Access Memory (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特にバックアップ電源一体型の半導体集積回路装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device integrated with a backup power source.
【0002】[0002]
【従来の技術】従来の半導体集積回路装置は、内部のI
Cチップ接続用の端子(以下パッド端子と略する)と、
外部のソケットやプリント基板等の接続用端子(以下ピ
ン端子と略する)を有しており、前記パッド端子とピン
端子とは、一対となってICソケット内でリードによっ
て電気的に接続されている。2. Description of the Related Art A conventional semiconductor integrated circuit device has an internal I
A terminal for connecting a C chip (hereinafter abbreviated as a pad terminal),
It has a connection terminal (hereinafter abbreviated as a pin terminal) for an external socket or a printed circuit board, and the pad terminal and the pin terminal are paired and electrically connected by a lead in the IC socket. There is.
【0003】図4は従来例として半導体集積回路装置の
VCC−GND(以下電源と略する)のピン端子1a,
1b−パッド端子2a,2b間の等価回路図である。As a conventional example, FIG. 4 shows a pin terminal 1a of a VCC-GND (hereinafter abbreviated as power supply) of a semiconductor integrated circuit device.
It is an equivalent circuit diagram between 1b-pad terminals 2a and 2b.
【0004】図4において、VCCピン端子1a,GN
Dピン端子1b,VCCパッド端子2a,GNDパッド
端子2bがあり、これら端子間1a−2a,1b−2b
はそれぞれ電源リード3a,3bによって電気的に接続
されている事を示している。また、電源リード3a,3
b間に、コンデンサ素子7を接続し、電源系から進入し
て来る振幅の小さい高周波ノイズを半導体集積回路装置
内で減衰させる事ができるようになっている。In FIG. 4, VCC pin terminals 1a, GN
There are a D pin terminal 1b, a VCC pad terminal 2a, and a GND pad terminal 2b, and between these terminals 1a-2a, 1b-2b.
Indicates that they are electrically connected by power supply leads 3a and 3b, respectively. Also, the power leads 3a, 3
A capacitor element 7 is connected between the points b and a high-frequency noise having a small amplitude and coming from the power supply system can be attenuated in the semiconductor integrated circuit device.
【0005】[0005]
【発明が解決しようとする課題】前述の半導体集積回路
装置において、電源系から進入して来る振幅の小さい高
周波ノイズに対しては、コンデンサ素子7の効果によっ
て内部IC6に与える影響を軽減される事ができるが、
振幅の大きな電源電圧変動例えば電源電圧の瞬断に対し
て、内部IC6の動作が停止してしまう欠点があった。In the semiconductor integrated circuit device described above, the effect of the capacitor element 7 on the high frequency noise having a small amplitude coming from the power supply system can be reduced. But you can
There is a drawback in that the operation of the internal IC 6 is stopped due to a large fluctuation of the power supply voltage such as a momentary interruption of the power supply voltage.
【0006】本発明の目的は、以上の欠点を解決し振幅
の大きな電源電圧変動に対して内部ICの動作状態を一
定時間以上補償することのできるようにした半導体集積
回路装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-mentioned drawbacks and can compensate the operating state of the internal IC for a certain time or longer against a large fluctuation in the power supply voltage. is there.
【0007】[0007]
【課題を解決するための手段】本発明の半導体集積回路
装置の構成は、蓄電池と、前記蓄電池が放電することを
防止するダイオード素子とを有し、前記蓄電池の+電極
がパッケージの高電位側電源リードへ接続され、−電極
が前記パッケージの低電位側電源リードへ接続され前記
ダイオード素子は前記リード間に外部より与えられる電
圧によって順バイアスされるように接続されていること
を特徴とする。The structure of a semiconductor integrated circuit device of the present invention has a storage battery and a diode element for preventing the storage battery from discharging, and the + electrode of the storage battery is on the high potential side of the package. The negative electrode is connected to a power supply lead, the negative electrode is connected to a power supply lead on the low potential side of the package, and the diode element is connected so as to be forward-biased by a voltage externally applied between the leads.
【0008】[0008]
【実施例】図1は本発明の第1の実施例としての半導体
集積回路装置の電源のピン端子−パッド端子間の等価回
路図である。FIG. 1 is an equivalent circuit diagram between a pin terminal and a pad terminal of a power source of a semiconductor integrated circuit device as a first embodiment of the present invention.
【0009】図1において、本実施例は、VCCピン端
子1aと、GNDピン端子1bと、VCCパッド端子2
aと、GNDパッド端子2bとを有し、端子間1a−2
aは、ダイオード素子5を介し、電源リード3a,3
a′によって電気的に接続され、端子間1b−2bは電
源リード3bによって電気的に接続されている事を示し
ている。Referring to FIG. 1, in this embodiment, a VCC pin terminal 1a, a GND pin terminal 1b, and a VCC pad terminal 2 are provided.
a and a GND pad terminal 2b, and between the terminals 1a-2
a is a power supply lead 3a, 3
It is shown that they are electrically connected by a'and the terminals 1b-2b are electrically connected by the power supply lead 3b.
【0010】また、電源リード3a,3b間に、蓄電池
(繰り返し充電することにより、反復使用が可能な蓄電
池)4が接続されている事を示している。Further, it is shown that a storage battery (storage battery which can be repeatedly used by repeatedly charging) 4 is connected between the power supply leads 3a and 3b.
【0011】このような接続を行うことにより、振幅の
大きな電源電圧変動例えば電源電圧の瞬断の場合、不足
分の電位は蓄電池4によって補充され、内部ICに及ぶ
影響を、一定時間補償する事ができる。By making such a connection, in the case of a large fluctuation of the power supply voltage, for example, a momentary interruption of the power supply voltage, the insufficient potential is replenished by the storage battery 4, and the influence on the internal IC is compensated for a certain period of time. You can
【0012】図2は図1の実施例としての半導体集積回
路装置の電源のピン端子−パッド端子間の内部実装状態
を示した斜視図である。FIG. 2 is a perspective view showing an internal mounting state between the pin terminal and the pad terminal of the power source of the semiconductor integrated circuit device as the embodiment of FIG.
【0013】図2において、図5と同じ部分には、同じ
数字を付してあり、内部IC6は、デュアルライン型の
リードを有するパッケージに実装されている。In FIG. 2, the same parts as those in FIG. 5 are denoted by the same numerals, and the internal IC 6 is mounted in a package having a dual line type lead.
【0014】図3は本発明の第2の実施例の等価回路図
である。FIG. 3 is an equivalent circuit diagram of the second embodiment of the present invention.
【0015】図3において、本実施例は、VCCピン端
子1aと、GNDピン端子1bと、VCCパッド端子2
aと、VCC1パッド端子2a′と、GNDパッド端子
2bとを備え、端子間1a−2aは、ダイオード素子5
を介して、電源リード3a,3a′によって電気的に接
続されており、端子間1a−2a′は、ダイオード素子
5′を介して、電源リード3a″,3a′によって電気
的に接続されており、端子間1b−2bは電源リード3
bによって電気的に接続されている事を示している。Referring to FIG. 3, in this embodiment, a VCC pin terminal 1a, a GND pin terminal 1b, and a VCC pad terminal 2 are provided.
a, a VCC1 pad terminal 2a ', and a GND pad terminal 2b, and the terminals 1a-2a are diode elements 5
Are electrically connected by means of power supply leads 3a, 3a ', and the terminals 1a-2a' are electrically connected by means of power supply leads 3a ", 3a 'via a diode element 5'. , Power lead 3 between terminals 1b-2b
It is shown that they are electrically connected by b.
【0016】また、電源リード3a−3b間及び3a″
−3b間に、蓄電池4,4′が接続されている事を示し
ている。Further, between the power leads 3a-3b and 3a "
It shows that the storage batteries 4 and 4'are connected between -3b.
【0017】VCCパッド端子2aには、内部IC6の
MAINのVCCに接続し、VCC1パッド端子2a′
には、内部IC6の非常時に内部状態等を記録するため
の比較的低消費電力な領域(以降バックアップ領域と略
する)のVCCに接続する。The VCC pad terminal 2a is connected to the VCC of MAIN of the internal IC 6, and the VCC1 pad terminal 2a '.
Is connected to the VCC of a relatively low power consumption area (hereinafter abbreviated as backup area) for recording the internal state and the like of the internal IC 6 in an emergency.
【0018】蓄電池4の充電容量は、内部IC6がバッ
クアップ領域にバックアップ動作を完了するまでを充分
補償できる容量にし、蓄電池4′の充電容量は電源電位
変動が回復し、正常に動作できるまでを充分補償できる
容量にする。The charging capacity of the storage battery 4 is set to a capacity capable of sufficiently compensating until the internal IC 6 completes the backup operation in the backup area, and the charging capacity of the storage battery 4'is sufficient to recover the fluctuation of the power supply potential and operate normally. Use a capacity that can be compensated.
【0019】このような設定を行うことにより、比較的
消費電力の大きい内部IC6の場合においても、少ない
充電容量の蓄電池で補償する事ができ、より一層の信頼
性の向上を図る事ができる。By making such a setting, even in the case of the internal IC 6 which consumes a relatively large amount of power, it is possible to compensate with a storage battery having a small charge capacity, and it is possible to further improve reliability.
【0020】[0020]
【発明の効果】以上の説明で明らかな如く、本発明の半
導体集積回路装置によれば、蓄電池及びダイオード素子
を内蔵する事により、電源電圧変動に対して内部ICの
動作状態を、例えば第1の実施例では数秒〜数分間、第
2の実施例では、数分間〜数日間の長期にわたり、補償
することができるという効果を有する。As is apparent from the above description, according to the semiconductor integrated circuit device of the present invention, by incorporating the storage battery and the diode element, the operating state of the internal IC can be adjusted against the fluctuation of the power supply voltage, for example, the first This embodiment has an effect that compensation can be performed over a long period of several seconds to several minutes, and in the second embodiment over a long period of several minutes to several days.
【図1】本発明の第1の実施例の電源のピン端子−パッ
ド端子間の等価回路図である。FIG. 1 is an equivalent circuit diagram between a pin terminal and a pad terminal of a power supply according to a first embodiment of the present invention.
【図2】図1に示した半導体集積回路装置の斜視図であ
る。FIG. 2 is a perspective view of the semiconductor integrated circuit device shown in FIG.
【図3】本発明の第2の実施例の電源ピン端子−パッド
端子間の等価回路図である。FIG. 3 is an equivalent circuit diagram between a power supply pin terminal and a pad terminal according to a second embodiment of the present invention.
【図4】従来例の電源のピン端子−パッド端子間の等価
回路図である。FIG. 4 is an equivalent circuit diagram between a pin terminal and a pad terminal of a conventional power supply.
1a VCCピン端子 1b GNDピン端子 2a VCCパッド端子 2a′ VCC1パッド端子 2b GNDパッド端子 3a,3a′,3a″,3b 電源リード 4,4′ 蓄電池 5 ダイオード素子 6 内部IC 7 コンデンサ素子 1a VCC pin terminal 1b GND pin terminal 2a VCC pad terminal 2a 'VCC1 pad terminal 2b GND pad terminal 3a, 3a', 3a ", 3b Power supply lead 4, 4 'Storage battery 5 Diode element 6 Internal IC 7 Capacitor element
Claims (2)
防止するダイオード素子とを有し、前記蓄電池の+電極
がパッケージの高電位側電源リードへ接続され、−電極
が前記パッケージの低電位側電源リードへ接続され前記
ダイオード素子は前記リード間に外部より与えられる電
圧によって順バイアスされるように接続されていること
を特徴とする半導体集積回路装置。1. A storage battery and a diode element for preventing the storage battery from discharging, wherein a + electrode of the storage battery is connected to a high potential side power supply lead of a package, and a − electrode of the storage battery is a low potential side of the package. A semiconductor integrated circuit device characterized in that it is connected to a power supply lead and the diode element is connected so as to be forward-biased by a voltage externally applied between the leads.
回路が、二組用意されている請求項1記載の半導体集積
回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein two sets of circuits each including a diode element and a storage battery are prepared.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3305174A JPH05143206A (en) | 1991-11-21 | 1991-11-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3305174A JPH05143206A (en) | 1991-11-21 | 1991-11-21 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05143206A true JPH05143206A (en) | 1993-06-11 |
Family
ID=17941953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3305174A Withdrawn JPH05143206A (en) | 1991-11-21 | 1991-11-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05143206A (en) |
-
1991
- 1991-11-21 JP JP3305174A patent/JPH05143206A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |