JPH0514341A - Isdn interface circuit - Google Patents

Abstract

PURPOSE:To shorten the transmission time to a reply signal line setting decoding circuit with respect to a control signal commanded from an exchange by providing a frame generating circuit and a timing command circuit to the interface circuit. CONSTITUTION:A frame generating circuit 11 receives a frame pulse 101 used for satellite communication from a TDM control circuit and outputs a counter output signal 109 whose timing is within a frame period being a desired time reference synchronously with a frame pulse such as within 5msec period. The signal 109 is inputted to a timing command circuit 12, which generates in-frame area signals 110-112 give to each of terminal interface circuits 13-15. The signals 110-112 need number of terminal interface circuits and to which area in a frame a signal of each terminal interface circuit is to be sent is decided by the circuit 102 to input an identification signal 102. That is, the circuit 12 decodes the signal 102 to designate an optional area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ISDN interface circuit, and more particularly to an ISDN interface circuit for realizing real-time signal exchange between an ISDN terminal and a TDMA satellite communication device.

[0002]

2. Description of the Related Art A conventional terrestrial interface circuit of a TDMA satellite communication device has a structure as shown in FIG. Input signals 201, 20 of some kind of terrestrial data
3. The data output signals 202 and 204 are interfaced with the terrestrial interface circuits 21 and 22 of the TDMA device. A certain type of terrestrial data is, for example, a relay 1.5 MBPS transmission line in which subscriber data is multiplexed or an 8 MBPS interface with a terrestrial M20 multiplexer.
For example, a transmission line. Input ground system data 201, 20
3, the terrestrial system interface circuit 21 and the terrestrial system interface circuit 22 perform appropriate processing such as data phase matching and frame synchronization, and the terrestrial system control signal 205,
206 is sent to the storage circuit 23. In the memory circuit 23, the control signals 205 and 206 are written in an appropriate memory at an address, and the CPU in the line setting decoding circuit 24 reads the data via the CPU bus 207 at an appropriate timing. In the line setting decoding circuit 24, the TDM of the reference station
The line setting instruction information 208 sent from the A control unit (not shown) via the satellite line is taken into the CPU, the control signals 205 and 206 are decoded from the ground system, and the line setting information 209 of the own station is created. To the TDMA control unit.

In the conventional circuit as described above, if the terrestrial interface circuit has 3 to 4 ports, the amount of data written to the memory circuit 23 is not so large, but 5 ports or more, 1
With 0 ports, the amount of data will increase dramatically, the capacity of memory will increase, and the scale of hardware will also increase.
This one port means one terrestrial interface circuit. Moreover, in the conventional TDMA satellite communication system,
Since no subscriber (terminal, etc.) in the ISDN network was accommodated, real-time transfer of the control signal between the line setting decoding circuit 24 and the TDMA control unit 3 terrestrial interface circuit was not required.

[0004]

The above-mentioned conventional circuit configuration has a drawback that the memory capacity and the hardware scale increase as the number of terminal interface ports mounted on the device increases. is there. Further, since the structure is such that the data is once written in the memory and the data is read out by the instruction of the external CPU, there is a drawback that the response real time property to the control signal necessary for the subscriber's mail system is lacking.

[0005]

An ISDN interface circuit of the present invention is an N (N is an integer) terminal interface circuit having an interface between an ISDN terminal and a control unit of a TDMA satellite communication device, and a reference station of a TDMA satellite communication system. From the line setting decoding circuit that inputs the line setting instruction information sent from the satellite communication from the station and sends the line setting information to the TDMA satellite communication device control unit of the own station, and to the own terminal that is input from this line setting decoding circuit. A frame generation circuit that time-multiplexes response signals of N terminal interface circuits corresponding to corresponding terminal control signals to generate a time reference signal to be sent to the line setting decoding circuit, and a frame generated by this frame generation circuit Output from N terminal interface circuits and a timing instruction circuit that indicates which position in the And a demultiplexer for outputting respectively to the terminal interface circuit that data by separating the data input from the TDMA controller sends out the multiplexed to TDMA control unit.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Figure 1
, The terminal signals 103, 1 arriving at the TDMA device
Reference numerals 05 and 107 denote terminal interface circuits 13, 14, and 1.
Input to 5. Appropriate processing of these terminal signal data (level conversion, cable delay equalization, frame synchronization, etc.)
And transmitted as transmission data 115, 117, 119 to the demultiplexing circuit 17. The demultiplexing circuit 17 multiplexes the data of the terminal interface circuits 13 to 15 and
Output as multiplexed data 123 to the DMA control unit. On the other hand, the multiplexed data 124 input from the TDMA control unit
Is the demultiplexing circuit 17 for the terminal interface circuit 13,
Received data 116,1 separated into 14 and 15 data
Terminal interface circuits 13, 1 as 18, 120
4 and 15 are sent. The above description is a description of the flow of data (B and D channels) between the ISDN terminal and the like and the TDMA control unit.
It is necessary to establish the layer 1 link defined by DN. Layer 1 means a physical interface, and is limited to an electrical interface with a terminal here. By the way, there are two methods for establishing Layer 1. One is when the terminal makes a call, and the other is when the terminal is activated on the network side. Here, it is assumed that the terminal is activated from the network side (exchange).

[0007] From the ISDN switch, a terminal control signal is transmitted by a transmission line to a reference station that creates a time reference in the TDMA system. At the reference station, this control signal is time-multiplexed on the satellite line together with other data to perform TD.
It is sent to the slave station in the MA system. Each slave station separates the line setting instruction information 121 from the received signal and sends it to the line setting decoding circuit 16. The control signal 11 for each terminal
4 is included in the line setting instruction information 121. Further, the control signal 114 to the terminal means the start instruction, start stop, and test loopback instruction information of each terminal sent from the ISDN exchange.

The line setting decoding circuit 16 separates the line setting information 122 for its own station from the line setting instruction information 121, transfers the line setting information 122 to the TDMA control section, and at the same time handles the line setting instruction information 121 for terminals handled by the own station. And the control signal 114 of each terminal is determined from each terminal interface circuit 13,
Send to 14 and 15. Terminal interface circuit 13,
14 and 15, the control signal 114 is received, the control is executed, and the response signal 1 to the control signal 114 is received.
13 is sent back to the line setting decoding circuit 16. Further, the line setting decoding circuit 16 sends the response signal 113 to the satellite line, and the reference station (not shown) of the satellite line that receives the response signal 113
A response signal will be returned to the exchange. By the way, it is essential that the line setting decoding circuit 16 normally uses a CPU to decode the line setting instruction information 121. However, when interfacing the line setting decoding circuit 16 and the terminal interface circuits 13, 14, and 15 with a CPU bus, it is necessary to determine a communication procedure between both circuits, but a simple hardware bus is used because of processing time constraints. It is preferable to use it. Here, the processing time constraint means a constraint that the response signal to the control signal from the exchange is returned in real time in the terminal interface circuits 13, 14 and 15, and after the control signal is transmitted by the exchange, The time until the response signal is returned is specified. But,
CP increases as the number of terminal interface circuits increases
Since the processing time of U becomes a problem, various control signals and response signals that require real-time processing time are transmitted to the line setting decoding circuit 16 and the terminal interface circuits 13 and 14,
In order to easily transfer data to and from 15, a configuration is adopted in which a certain time reference is defined and control signals and response signals are multiplexed within that time. A frame generation circuit 11 and a timing generation circuit 12 are used as this configuration. The frame generation circuit 11 inputs a frame pulse 101 (for example, 20 msec cycle) used in satellite communication from the TDMA control circuit, and generates timing within a frame cycle within a desired time reference synchronized with this frame pulse. The desired frame period in this case is a 5 msec period as shown in FIG. 2, and the timing within the frame period means the counter output signal 109 within the 5 msec period. The counter output signal 109 is input to the timing instruction circuit 12, and in the timing instruction circuit 12, each terminal interface circuit 13,
In-frame area signals 110 and 11 to be provided to 14 and 15
Create 1,112. This intra-frame area signal 11
0, 111, 112 are terminal interface circuits 13,
The response signal 113 detected at 14 and 15 is set to the above-mentioned 5 ms.
This is position designation information for multiplexing within the ec cycle. That is, as an example, it is the intra-frame area signal 110 that allocates the response signal 113 of the terminal interface circuit 13 to the area 1 as shown in FIG. Signals assigned to area N are intra-frame area signals 111 and 112.

These area signals are required for the number of terminal interface circuits. The timing instruction circuit 12 inputs the identification signal 102 to which area (position) in the frame the signal of each terminal interface circuit should be sent. It will be decided by doing. That is, the timing instruction circuit 12 decodes the value of the identification signal 102 to specify an arbitrary area.

As described above, the terminal interface circuit 1
By using the hardware 8-bit bus 113 shown in FIG. 2 between 3, 14, 15 and the line setting decoding circuit 16, it is possible to multiplex the control signal 3 response signal and interface without using the CPU bus. Become.

[0011]

As described above, according to the present invention, by providing the frame generation circuit and the timing instruction circuit,
Since the response signals sent from the N terminal interface circuits can be multiplexed in a frame and data can be transferred in real time, rather than interfacing the N terminal interface circuits and the line setting decoding circuit with the CPU bus. Also has the effect of shortening the startup time of layer 1. That is, there is an effect that the time for sending to the response signal line setting decoding circuit for the control signal instructed by the exchange is shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a frame configuration diagram illustrating the present embodiment.

FIG. 3 is a block diagram of a conventional ISDN interface circuit.

[Explanation of symbols]

11 frame generation circuit 12 timing instruction circuit 13, 14, 15 terminal interface circuit 16 line setting decoding circuit 17 demultiplexing circuit 101 timing pulse 102 identification signal 103, 105, 107 input terminal interface signal 104, 106, 108 output terminal interface signal 109 Counter output signals 110, 111, 112 Area instruction signal 113 Response signal 114 Control signals 115, 117, 119 Transmission data 116, 118, 120 Received data 121 Channel setting instruction information 122 Channel setting information 123 of own station Multiplex transmission data 124 Multiplex reception data

Claims (2)

[Claims] 1. N (N is an integer) terminal interface circuits having an interface between an ISDN terminal and a control unit of a TDMA satellite communication apparatus, and a line setting transmitted by satellite communication from a reference station of a TDMA satellite communication system. Line setting decoding circuit for inputting instruction information and transmitting line setting information to the TDMA satellite communication device control unit of the own station, and N corresponding to terminal control signals corresponding to the own terminal input from this line setting decoding circuit A frame generation circuit that time-multiplexes the response signal of the terminal interface circuit of 1 to generate a time reference signal to be sent to the line setting decoding circuit, and an instruction at which position in the frame created by this frame generation circuit Timing output circuit and the data output from the N terminal interface circuits are multiplexed and sent to the TDMA control unit. And a demultiplexing circuit that demultiplexes data input from the TDMA control unit and outputs the demultiplexed data to the terminal interface circuit.
Interface circuit. 2. The N area signals in one frame created by the frame generation circuit correspond to the area information of the N terminal interface circuits, and the time interval of this frame unit is required at least in TDMA satellite communication. The ISDN interface circuit according to claim 1, wherein the frame is set within 5 msec per frame.