JPH0514427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device having a structure in which a plurality of packages mounted using the TAB method are stacked.

BACKGROUND OF THE INVENTION In recent years, the demand for higher density electronic equipment has become a major issue, and the configuration shown in FIG. 5 has been used as a solution to this problem. FIG. 5 is a cross-sectional view of an example of a conventional semiconductor device with high-density packaging. A predetermined wiring pattern and electrodes 21 are provided on both sides of the circuit board 20.
a and 21b are provided, and the wiring patterns on each surface are electrically connected to each other through through holes (not shown). packaged semiconductor chip 22a,
22b are placed on both sides of the circuit board 20.
In such a conventional configuration, by arranging the packages on both sides of the circuit board 20, at least about twice the packaging density can be obtained in the same planar area.

Problems to be Solved by the Invention However, in the conventional configuration, packages are arranged flat on both sides of the circuit board, so only twice the packaging density can be obtained. There was a problem that it could not cope with the increasing density of equipment. The present invention was attempted in view of the above-mentioned problems, and an object of the present invention is to provide a stacked semiconductor package that can achieve a packaging density that is more than twice as high. Another object of the present invention is to provide a structure in which leads of stacked semiconductor devices can be easily connected to a substrate. A further object of the present invention is to obtain a method for easily and highly accurately manufacturing a laminated structure suitable for laminating semiconductor memory devices.

Means for Solving the Problems In the method of the present invention, a semiconductor chip is installed in an outer lead hole, a device hole, and a device hole of a film having holes, and inner leads connected to electrode terminals of the semiconductor chip are provided. The outer lead is separated into a plurality of pieces on the film in the outer lead region connected to the film, and the outer lead is made to extend into the outer lead hole, and the film on which the semiconductor chip is mounted is separated and cut, and the predetermined number of pieces separated into the plurality of pieces is cut. The outer leads of the TAB package are selectively cut at the outer lead hole to form a TAB package, and a plurality of the packages are stacked in multiple stages by inserting a guide member into each of the holes to align the packages. This connects the outer leads of the circuit board and the electrodes on the circuit board.

Function As described above, the present invention allows semiconductor chip packages and leads to be easily and accurately aligned and stacked by inserting guide pins, that is, guide members into alignment holes provided in the film. Furthermore, it is possible to easily stack the packages regardless of the number of packages, the leads can be easily cut, there is no variation in the cut leads, and terminals other than the common terminal can be easily connected to the electrodes of the circuit board. Therefore,
It becomes possible to easily obtain a high-density packaging package in which semiconductor chips are stacked in any number of layers with high accuracy.

Example When multiple LSI memory chips are mounted on the same circuit board, electrodes common to each chip such as power supply and clock signal lines are interconnected by connecting the same electrodes of each chip in common. can be connected with. However, non-common electrodes such as chip selection electrodes must be individually taken out from each chip and connected to specific wiring on the circuit board. There is such a problem when stacking a plurality of LSI memory chips, and an embodiment of the present invention will be described below that takes into account connection processing of common electrodes and non-common electrodes. FIG. 1 is a plan view of a TAB package which is part of the structure of a semiconductor device in one embodiment of the present invention. In this embodiment, a case where four memory LSI chips are stacked will be explained below with reference to FIGS. 3 and 4. 1st
In the figure, at least a device hole 3 and an outer lead hole 4 are opened in a resin film (film carrier tape) 1 made of polyimide, glass epoxy (glass fiber-filled epoxy), etc., and the device hole 3 is formed with copper foil and plated. The inner leads 5 and 7 are configured in a protruding shape. The lead 100 is composed of inner leads 5, 7 and outer leads 5', 8 integrally formed with the leads 5, 7, respectively. The region of the outer lead 8 is formed separately into a plurality of outer leads 8a to 8h. In the configuration example shown in FIG. 1, the chip 2 has eight electrodes, and eight inner leads 5 are connected to each of these electrodes. Figure 1 is an LSI
A state in which the electrodes 6, 10 of the chip 2 and the inner leads 5, 7 are already connected is shown. The LSI chip 2 and the inner leads 5, 7 are formed by bonding the leads 5, 7 to bumps (metal protrusions) formed on the electrodes 6, 10 of the chip 2, or by forming bumps on the leads 5, 7. Connection is made by joining the bulb and the electrodes 6, 10. In each stacked LSI chip, the leads 5 and 5', that is, the common terminal, which process the same signal with the electrodes at the same position on the chip 2, are power supply and clock signal terminals, and are connected to the electrodes of the LSI chip 2. One continuous lead is formed through the inner lead region and the outer lead region following it. On the other hand, in each stacked LSI chip, the electrode 10 at the same position on the chip 2 is used as a lead for processing different signals, that is, a non-common electrode terminal for chip selection used to input and output signals to each chip. is one lead at least in the inner lead region, that is, the inner lead 7, but in the outer lead region 8, there is a lead group (outer lead) 8a in which the inner leads 7 are separated by the number of chips to be stacked.
Formed as ~8h.

Furthermore, holes 9 are provided at arbitrary locations on the film carrier tape 1. In addition, in Figure 1
Although one LSI chip 2 is shown, a large number of chips are installed on the tape 1 in the longitudinal direction as shown in FIG. That is, a large number of LSI chips 2 are successively mounted on the inner leads 5 and 7 of the film carrier tape 1 in the longitudinal direction, and an electrical inspection is performed. In the state shown in FIG. 1, a protective resin film (not shown) is formed on the chip 2, and before it is mounted on a circuit board, it is cut into a predetermined shape, for example, along the chain line L, and individual TAB packages are formed. Created. Second
Figures a to d show how the film shown in Figure 1 is cut into a predetermined shape, and each layer is laminated with LSI chips mounted on it.
FIG. 3 is a plan view showing a state in which a TAB package is formed. In TAB package A mounted with stacked LSI chips, the outer lead of electrode 10 is 8
8b, 8c, 8d, 8f, except for a, 8e leads,
8g and 8h are all cut off (Figure 2a).
In package B in which the stacked LSI chips are mounted, the outer leads 8a, 8c, 8d, 8e, 8g, and 8h of the electrode 10 located at the same position as chip A are cut off, leaving only 8b and 8f (Figure 2b). Similarly, outer leads 8c and 8g of package C mounted with an LSI chip are left, and outer leads 8d and 8h of package D mounted with an LSI chip are left, and the other leads are cut off (Fig. 2 c, d). In this way, the shape of the outer leads 8 after cutting is made different for each stage of stacked LSI chips. This selective cutting of the outer leads 8 can be carried out at the same time, using a punching die, for example, when each chip 2 is cut into a predetermined shape from the film carrier 1 after the LSI chip 2 is mounted on the film as shown in FIG. can. Alternatively, after cutting the chip 2 into a predetermined shape using a certain mold, only the outer leads 8 may be cut in a separate process.

According to the above method, the outer leads are separated on the tape film, and selective cutting of predetermined outer leads is performed at the outer lead hole. Therefore, the outer lead can be easily cut, and the outer lead does not bend or warp after being cut, and a highly accurate outer lead pitch can be maintained.

When all of the TAB packages A to D having the configuration shown in FIG.
B, 8c, 8d, 8e, 8f, 8g, and 8h have a structure in which they are stacked and do not overlap. Therefore,
Signals can be input and output separately to the outer leads in this state. Figure 3 shows the LSI chip implemented.
FIG. 4 is a sectional view showing a mounting state in which TAB packages are stacked, and FIG. 4 is a perspective view of a part of the stacked mounting state. In this structure, a guide pin 50 is inserted into the hole 9 to position the outer lead between each package when stacking tape carrier packages.
TAB packages A to D mounted with LSI chips A, B, C, and D are stacked and installed on the circuit board 30, and the outer leads led out without overlapping as described above are connected to each electrode wiring of the circuit board 30. In FIGS. 3 and 4, each lead 8a, 8b, 8
8c and 8d are respectively connected to the electrode wirings 31a to 31d of the substrate. At this time, the connection is made by instantaneously raising the temperature using, for example, a pulse tool 51, and reflowing the solder layer. Furthermore, the leads of each stacked LSI chip can be easily formed into their own shapes because the leads themselves are thin and soft. In addition, before making this connection, connect the outer leads 8a, 8b, 8c, 8d.
Even if you do not perform the forming process, simply leave it in the state where it is cut from the film carrier 1 (the state in which the leads are led out in the same direction as the chip surface),
When mounting each chip on the circuit board 30, for example, by pressing the leads with the pulse tool 51,
The leads of each chip can also be formed as shown in FIG. Note that the leads 5' led out from the common terminal of each LSI chip 2 are collectively connected to the electrodes of the circuit board while being overlapped at the same position. In this way, multiple extremely thin TAB packages, each with an LSI chip mounted thereon, can be easily and densely stacked on a circuit board. Besides the common terminals of each chip, non-common terminals (outer leads) can be led out to different positions on the circuit board. Furthermore, the outer lead was completed when the TAB package was created,
There is no need for any extra processing or use of other members when mounting on a circuit board. In the examples shown in FIGS. 3 and 4, if the chip is a semiconductor memory chip, first, when inputting/outputting signals to/from chip A, a command signal is input to lead 8a. This makes it possible to input signals only to chip A. Similarly, for example, Chip D
When inputting and outputting signals to, use lead 8d.
Input the command signal by In this way, each stacked chip can be freely selected using the leads 8a to 8d, which are chip selection terminals. For example, the chips include _256K D-RAM, _1M DRAM, _4M
When four DRAMs are stacked using the configurations shown in Figures 3 and 4, the memory capacity is 1M, 4M, and 16M, respectively.
A memory package having DRAM capacity can be obtained. And this mounted body is approximately 445μ per piece.
This is a direct lamination of the TAB package itself, which is approximately 1.5 ft thick, making it extremely compact and thin as a whole, and only takes up the area of one piece. Note that memory chips include not only DRAM but also SRAM,
It goes without saying that the present invention can be applied to things such as ROM, and also to things other than memory chips. In the present invention, the number of laminated layers is not limited to four, but any number of layers from two to more can be laminated.

Effects of the Invention As is clear from the above description, the method of the present invention stacks TAB packages by inserting guide members into alignment holes provided in the film.
Packages and leads can be aligned easily and accurately, making it suitable for stacking multiple chips. Semiconductor chips can be easily stacked in multiple layers on a circuit board, and the lead terminals can be easily connected to the circuit board. . The method of the present invention uses TAB technology to selectively cut multiple outer leads separated on the film from a single inner lead, so deformation of the outer leads is less likely to occur and the outer leads can be cut finely with high precision. It can be formed in pitch, and unnecessary leads can be easily cut off. Therefore, since the method of the present invention allows a large number of chips to be easily stacked, it exhibits an excellent effect in achieving a remarkable improvement in packaging density, and is extremely useful industrially.

[Brief explanation of the drawing]

Fig. 1 is a plan view of a TAB package which is part of the structure of a semiconductor device in an embodiment of the present invention, and Figs. 2 a to d show mounting of stacked LSI chips.
A plan view showing a TAB package cut into a predetermined shape for each layer, Figure 3 is a sectional view showing a stacked TAB package with LSI chips mounted thereon, and Figure 4 is a perspective view of the main parts of the package. , FIG. 5 is a sectional view of a conventional high-density packaged semiconductor device. 1...Resin film, 2...LSI chip, 5,
7... Inner lead, 6, 10, 31... Electrode,
5', 8a to 8h...outer lead, 9...hole,
30...Circuit board, 50...Guide pin.

Claims (1)

[Claims] 1. A semiconductor chip is installed in the device hole of the film in which an outer lead hole, a device hole, and a hole are respectively opened, and the outer lead is connected to the outer lead region connected to the inner lead connected to the electrode terminal of the semiconductor chip. A plurality of outer leads are separated on the film and extended into the outer lead hole, and the film on which the semiconductor chip is mounted is separated and cut, and a predetermined outer lead separated into the plurality of leads is selectively inserted into the outer lead hole. A TAB package is formed by cutting, a plurality of the packages are stacked in multiple stages by inserting a guide member into each hole to align them, and the outer leads of the packages are bonded to the electrodes on the circuit board. A method for mounting a stacked semiconductor, characterized by: