JPH0515088B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital-to-analog converter (hereinafter simply referred to as a D/A converter), and particularly to a charge redistribution type D/A converter. There are various types of D/A converters for converting a binary digital signal with a predetermined number of bits into an analog signal, but a D/A converter with a simple configuration is a so-called charge redistribution type D/A converter. . FIG. 1 is a circuit block diagram of an example of a D/A converter using this charge redistribution method, in which first and second capacitors C 1 and ₂ of equal capacitance are connected at one end to a predetermined reference potential point (for example, ground). _C2 is provided, and control of charging and discharging of these capacitors, etc. is performed by on/off operations of switch elements 1 to 3. Specifically, a switch 1 is provided to control the charging of the capacitor _C1 , and a switch 2 is provided to control the redistribution of the charge charged in the capacitor _C1 to the capacitor _C2 . A switch 3 is provided to discharge and reset the charge of the capacitor _C1 , and each of these switches 1 to 3 outputs control signals B to D generated from the control circuit 5 in response to the digital input signal A. The on/off control is performed by the respective on/off controls. The charge charged in the second capacitor _C2 at the end of a series of predetermined bits of the digital input signal is sampled and held in the sample and hold circuit 4, and the hold output becomes an analog signal corresponding to the digital input signal. 2 and 3 are diagrams showing the timing of control signals B to D with respect to digital signal A in the circuit of FIG. 1. FIG. 2 shows the case where the predetermined bit of the digital input signal A is "1", and FIG. 3 shows the case when the predetermined bit of the digital input signal A is "0". Referring to FIG. 2, when the bit code of the input signal is "1" as shown in FIG. During this time, the capacitor C ₁ is charged to have an electric charge of Q ₁ =C ₁ ·V (1). Note that V is a charging voltage. After that, the control signal C becomes high level for a predetermined period of time, turning on the switch 2. At this time, if the capacitor C 2 has already been charged with a charge Q′ ₂ , the new charge Q _{2 in the capacitor C 2 due} to redistribution by turning on the switch ₂ becomes Q ₂ = {C ₂ / (C ₁ +C ₂ )}・(Q' ₂ +C ₁ V) ...(2). Thereafter, the control signal D becomes high level, the switch 3 is turned on, and the capacitor _C1 is discharged and reset. Next, referring to FIG. 3, when the bit code of the input signal is "0" as shown in FIG.
Since remains at a low level, switch 1 remains off and capacitor C ₁ is not charged. Next, the control signal C goes high for a predetermined period, turning on the switch 2 and redistributing the charge.
The charge on the capacitor C ₂ at this time is Q ₂ = {C ₂ /(C ₁ + C ₂ )}·Q′ ₂ ……(3). Thereafter, the control signal D goes high, turning on the switch 3, and the capacitor _C1 is discharged and reset. Now, if the input digital signal A is a k-bit signal (k is a natural number), the second
Each of the control signals B to D is generated from the control circuit ₅ using the procedure explained using _FIG . It is held in the sample hold circuit 4. This hold output becomes an analog signal corresponding to the digital input signal. Using the above equations (2) and (3), the charge Q ₂ resulting from the finally obtained k-bit digital signal is expressed by the following equation. Q ₂ = _k 〓 ⁱ⁼¹ Q ₁・Z _i {C ₂ / (C ₁ + C ₂ )} ^k-i+1 ...(4) Here, Z _i is when the i-th bit is "1" is 1, and when it is "0", it is 0. What Equation (4) means is that the charge charged in capacitor C ₂ by the i-th bit is multiplied by C ₂ /(C ₁ + C ₂ ) in a geometric series for each subsequent 1-bit operation. It is a gradual decrease. Now, Q ₁ is a constant determined by C ₁ and V, so under the ideal state of Q ₀ and C ₁ = C ₂ , equation (4) becomes Q _0k 〓 ⁱ⁼¹ Z _i・(1/ 2) ^k-i+1 ...(5), and an analog signal is obtained from the output of capacitor _C2 . The above is an ideal case where C ₁ = C ₂ , but in reality, there is an error in the capacitance values C ₁ and C ₂ , so C ₁ = (1-β)C ₀ , C ₂ = (1+β)
Let's consider it as C ₀ . Note that 0<β<1.
In equation (4), by substituting C ₁ and C ₂ above, Q ₂ = (1-β) C ₀ V _k 〓 ⁱ⁼¹ Z _i (1+β) ^k-i+1・(1/2) ^{k- i+1} = (1-β ² ) C ₀ V _k 〓 ⁱ⁼¹ Z _i (1+β) ^ki・(1/2) ^k-i+1 ……(6). Comparing the ideal type equation (5) and the error-considered equation (6), the constant difference of (1-β ² ) is unrelated to linearity in absolute value, and if this is ignored, we get The term (1+β) ^ki in the term 〓 may or may not exist as defined by Z _i , and i
(1+
β) may vary in magnitude, resulting in a deviation from the ideal type, resulting in distortion and noise. Here, if we consider the standardized deviation E, E= _k 〓 ⁱ⁼¹ Z _i・ΔE _i = _k 〓 ⁱ⁼¹ Z _i (1/2) ^k-i+1・{(1+β) ^ki −1 }...(7) The deviation ΔE _i when the i-th bit operates up to the final k-th bit is ΔE _i = (1/2) ^k-i+1・(Aβ+Bβ ² +... …) …(8) becomes. Here, if β≪1, terms of β ² or more can be ignored, so ΔE _i =(1/2) ^k-i+1 ·Aβ −(9). Table 1 shows the values obtained from equation (9).

[Table] In Table 1, the maximum distortion is when Z _i is all "1", and β will be considered under the condition that this does not exceed the minimum unit. The minimum unit for each bit number of k = 4, 8, and 16 is (1/2) ⁴ , (1/2) ⁸ , and (1/2) ¹⁶ , so each value is the maximum distortion.
Assuming that 0.688β, 0.965β and 1.β do not exceed, respectively, the tolerance of β is 0.0909, 0.004 and 1.β, respectively.
Calculated as 0.000015. Since the difference between capacitors C ₁ and C ₂ is 2β, this difference is up to 18% for 4 bits and 0.8 for 8 bits.
% respectively are allowed. However, in 16 bits
Only 0.003% is allowed, so even if a capacitor could be manufactured with an error of 0.1%, it would only be possible to realize a D/A converter of about 10 bits. The present invention greatly reduces output distortion due to the difference in capacitance between two capacitors, and provides highly accurate multi-bit D/D/
The purpose is to provide an A converter. The D/A converter according to the present invention includes first and second capacitors, and control means for controlling charging and discharging of the first and second capacitors according to a digital input signal of a predetermined number of bits, or a charge redistribution type digital-to-analog converter that outputs an analog signal at a level corresponding to the value of the digital input signal based on the charge charged in the second capacitor, wherein the control means outputs an analog signal at a level corresponding to the value of the digital input signal; For each odd (or even) bit of the bit, the first capacitor is charged according to the bit content;
distributing the charge of the capacitor to a second capacitor and then discharging the first capacitor; and for each even (or odd) bit of the digital input signal:
The present invention is characterized in that the second capacitor is charged in accordance with the bit contents, and then the charge of the second capacitor is distributed to the first capacitor, and then the second capacitor is discharged. The present invention will be explained below using the drawings. FIG. 4 is a block diagram of an embodiment of the present invention.
Components equivalent to those in FIG. 1 are designated by the same reference numerals.
In this example, in addition to the configuration shown in Figure 1, a second capacitor
A charging switch 6 for C ₂ and a discharging switch 7 for this capacitor C ₂ are added. Then, in response to the digital input signal A, the control circuit 10 generates control signals B to D and B' and D', respectively,
The switches 6 and 7 are controlled on and off by signals B' and D', respectively. 5 to 8 are timing charts showing the operation of the circuit block in FIG. 4. For example, the operation for odd numbered bits is shown in FIGS. 5 and 6, and the operation for even numbered bits is shown in FIGS. 7 and 8. They are shown in the figure. However, on the contrary, the operations for even bits may correspond to those shown in FIGS. 5 and 6, and the operations for odd bits may correspond to those shown in FIGS. 7 and 8, respectively. If the odd (or even) bit is “1”,
As shown in FIG. 5, the control signal B becomes high level, turning on the switch 1 and charging the first capacitor _C1 . Next, the control signal C becomes high level and the charge is distributed between the capacitors _C1 and _C2 .
After that, the control signal D becomes high level and the capacitor _C1 is discharged. If the odd (or even) bit is "0", control signal B remains at a low level and capacitor _C1 is not charged, as shown in FIG. However, after the control signal C becomes high level and charge distribution is performed, the control signal D becomes high.
is turned on and capacitor _C1 is discharged. When the even (or odd) bit is "1", the control signal B' goes high and the second capacitor _C2 is charged, and then the control signal C goes high, as shown in Figure 7. charge distribution. Then, the control signal D' becomes high level and the second capacitor _C2 is discharged. If the even (odd) bit is “0”, the control signal is
B′ remains at a low level and capacitor C ₂ is not charged. However, the control signal C becomes high level, charge distribution is performed, and then the control signal C becomes high.
D' becomes high level and capacitor _C2 is discharged. That is, the capacitors to be charged and discharged are alternately switched for each bit, and an output corresponding to the charge of the capacitor _C2 is finally derived from the sample and hold circuit 4. Note that the output corresponding to the charge charged in the capacitor _C1 may be derived as an analog signal. Capacitor obtained by the operating procedure described above
Calculate the charge amount Q ₁ of C ₁ . First, capacitor C _2
When there _{is a} charge _{of Q ' 2 in 0} −Q
′ ₂・C ₁ /(C ₁ +C ₂ )……(10) Due to the operation corresponding to bit “0”, Q ₁ =−Q′ ₂・C ₁ /(C ₁ +C ₂ )……(11) Become. However, Q ₀ =VC ₁ C ₂ /(C ₁ +C ₂ ). Similarly, to calculate the amount of charge Q ₂ on capacitor C ₂ ,
When there is a charge Q' ₁ in the capacitor C ₁ , the operation corresponding to the bit "1" results in Q ₂ = Q ₀ - Q' ₁・C ₂ / (C ₁ + C ₂ )...(12 ) Due to the operation corresponding to the bit "0", Q ₂ =-Q' ₁ ·C ₂ /(C ₁ +C ₂ )...(13). For example, when the discharge operation of the first capacitor C ₁ is set to an odd number of bits, the final accumulated charge of the capacitor C ₁ for the digital signal (1011) is calculated from the above formulas as follows: Q ₁ = C ₁ C ₂ V{1 /(C ₁ +C ₂ )−0 +C ₁ C ₂ /(C ₁ +C ₂ ) ³ −C ² ₁ C ₂ /(C ₁ +C ₂ ) ⁴ }
...(14) becomes. That is, if each bit is "1", the corresponding term exists, and if it is "0", the corresponding term also becomes 0 and does not exist. Further, the absolute value of each corresponding term becomes a function in which the values C ₁ /(C ₁ +C ₂ ) and C ₂ /(C ₁ +C ₂ ) are multiplied alternately. It should be noted that the polarity of the charge value of the capacitor _C1 changes depending on whether this value is positive or negative. Generally, the following equation is obtained for a k-bit digital signal. Q ₁ ∝ _k 〓 〓 ⁱ⁼¹ (−1) ^ki・E _i C ^x ₁・C ^y ₂ / (C ₁ + C ₂ ) ^ki-1 ……(15
) Here, Z _i is 1 for bit “1” and 0 for bit “0”, and x+y=k−i+1,
(x, y) is (0, 0), (1, 0), (1, 1),
(2, 1). Here, C ₁ = (1-β)C ₀ , C ₂ = (1+β)C ₀
Then, equation (15) becomes Q ₁ ∝ _k 〓 〓 ⁱ⁼¹ (-1) ^ki・Z _i・(1/2) ^k-i+1・(1−β) ^x・
(1+β) ^y ...(16), and the error is (1-β) ^x・(1+β)
This is the term ^y . Let E be the error from the ideal case where C ₁ = C ₂ , and let ΔE _i be the error for each bit. E= _k 〓 ⁱ⁼¹ ΔE _i = _k 〓 〓 ⁱ⁼¹ (-1) ^ki・Z _i・(1/2) ^ki-1・{1-(1-
β) ^x・(1+β) ^y }……(17) ΔE _i =(−1) ^ki・(1/2) ^k-i+1・{
1-(1-β) ^x・(1+β) ^y }...(18) Here, {1-(1-β) ^x・(1+β) ^y is
If x=y, 1-(1-β) ^x =xβ ² +...x=y
If +1, 1-(1-β)(1-β ² ) ^y = β+yβ ²
+..., and if we ignore terms larger than β ² , an error term of β will be inserted every other bit, and its value will be the number of bits k.
It can be seen that the value does not increase and remains constant as the value increases.

【table】

[Table] Table 2 shows an example of numerical values. In the table,
ΔE _i ≒ (-1) ^ki・(1/2) ^k-i+1・(Aβ+Bβ ² )
= A ₀ β + B ₀ β ² . Calculating the maximum error from Table 2, it is -0.313β + 0.063β ² for 4 bits,
For 8 bits, it is -0.334β+ ^0.105β2 , and for 16 bits, it is -0.335β+ ^0.11β2 . On the other hand, in the conventional circuit system shown in FIG. 1, as shown in Table 1,
The maximum error is 0.688β for 4 bits and 0.688β for 8 bits.
0.965β, 1β for 16 bits, and therefore it can be seen that the circuit system of the present invention has an error of about 1/3 compared to the conventional system. For reference, Tables 3 and 4 show the distribution of errors when k=4 bits; Table 3 is based on the conventional method shown in FIG. 1, and Table 4 is based on the method of the present invention. In the table, the shaded area indicates that the bit is "0" and no error occurs, and the lined area indicates that there is no error in the primary term of β.

【table】

【table】

[Table] In the method of the present invention, two capacitors C ₁ and C ₂
In order to alternately switch the usage method for each bit, it becomes necessary to invert the digital input signal A every other bit. For example, in the case of even numbered bits, the odd numbered bits are inverted, and in the case of odd numbered bits, the even numbered bits are inverted.
Tables 5 and 6 show the aspects.

【table】

【table】

[Table] After sampling and holding the charge charged in one of the first and second capacitors obtained by the above operation, the above operation is repeated again using the same digital input signal to charge the other of the first and second capacitors. After the charged charges are sampled and held by another sample and hold circuit, the previous hold output and the subsequent hold output may be added. Such double operation increases the conversion time, but the error is about 1/20 of that of the conventional example, so the effect is significant. As described above, according to the present invention, it is possible to reduce the influence of output signal distortion caused by variations in the capacitance values of two capacitors. In particular, D/A converters that use a ladder resistor network require a trimming process to improve the accuracy of resistance values, making adjustments complicated and increasing costs. However, according to the present invention, a special A low-cost D/A converter can be obtained without requiring adjustment. Incidentally, the control circuit can be easily realized by a program using a computer such as a microprocessor.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a conventional D/A converter, FIGS. 2 and 3 are timing charts explaining the operation of the blocks in FIG. 1, and FIG. 4 is a circuit block diagram of an embodiment of the present invention. 5 to 8 are timing charts illustrating the operation of the circuit shown in FIG. 4. Explanation of symbols of main parts: C ₁ , C ₂ ... capacitor, 1 to 3, 6, 7 ... switch, 10 ... control circuit.

Claims (1)

[Scope of Claims] 1 comprising first and second capacitors and control means for controlling charging and discharging of the first and second capacitors according to a digital input signal of a predetermined number of bits,
A digital-to-analog converter of a charge redistribution type that outputs an analog signal of a level corresponding to the value of the digital input signal based on the charge of the first or second capacitor, wherein the control means For each odd (or even) bit of the digital input signal, the first capacitor is charged according to the bit content, and then the charged charge of the first capacitor is distributed to the second capacitor, and then the charge of the first capacitor is distributed to the second capacitor. the first capacitor is discharged, and the even (or odd) number of the digital input signals is
The bit is characterized in that the second capacitor is charged for each bit in accordance with the contents of the bit, the charge of the second capacitor is then distributed to the first capacitor, and then the second capacitor is discharged. Digital
analog converter.