JPH05150979A - Immediate operand extension method - Google Patents

Abstract

(57) [Summary] [Purpose] To enable specification of an immediate operand of a size that exceeds the size of the immediate operand field that can be secured in an instruction word, with a smaller instruction repertoire and without degrading performance. [Structure] When an immediate expansion instruction is held in, for example, the field 32 of the instruction fields 31 to 34 of the instruction register 3,
The mask signal M2 from the decoding circuit 42 becomes "1", and 26 bits of the extended immediate operand field i26 of this immediate extended instruction are guided to the upper side of the 32-bit immediate data line 61 through the gate 52. At this time, if it is assumed that an immediate value addition instruction is held in the instruction field 31, 6 bits of the immediate value operand field i6 are unconditionally guided to the lower side of the immediate data line 61, and expanded immediate data 71 is generated. To be done. This immediate data 71 is selectively output to the arithmetic unit 91 by the selector 81 and used for the specified arithmetic operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for handling a specific instruction having an immediate operand, and more particularly to an immediate operand extension method for extending an immediate operand.

[0002]

2. Description of the Related Art One of various instructions (instruction words) handled by an information processing apparatus such as a computer system is an instruction having an immediate operand. The instruction having the immediate operand has fields such as an instruction code (OP code) field and a destination field in addition to the immediate operand field. Therefore, the size of the immediate operand field that can be secured in the instruction word is limited.

Therefore, conventionally, in order to specify an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word, each function (each function such as addition operation and subtraction operation using an immediate operand) is specified. A method such as preparing an instruction corresponding to the size of an immediate operand has been applied.

There is also a method of preparing an instruction for modifying an immediate operand and replacing the immediate operand in a specific instruction word with an immediate operand of a larger size designated by the instruction.

In addition, there is also a method in which an immediate operand is divided into upper and lower parts, a dedicated load instruction is prepared for each, and a large immediate value is used via a register.

[0006]

However, in order to specify an immediate operand having a size exceeding the size of the immediate operand field that can be secured in the instruction word, an instruction corresponding to the size of the immediate operand is prepared for each function. However, the method has a problem that the number of instructions increases and the instruction system becomes complicated. Also, in this method, the size of the OP code field in the instruction word becomes large, so that the size of the operand designation field is pressed.

Further, in the system in which the immediate operand specified in the instruction word is simply replaced with the immediate operand specified by the dedicated instruction, there is a problem that the immediate operand having a size larger than the instruction word size cannot be specified.

Further, in the method of dividing the immediate operand and using it via the register, there is a problem that the overhead of one fetch cycle or more is involved because the immediate operand is used. In addition, this system has a problem that the performance may be deteriorated due to register hazard in the pipeline control system information processing apparatus.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word.
An object of the present invention is to provide an immediate operand extension method that can be specified with a smaller instruction repertoire (type of OP code) and without degrading performance.

Another object of the present invention is that in an information processing apparatus of a parallel processing system, an immediate operand having a size exceeding the size of an immediate operand field that can be secured in an instruction word causes the number of instruction fetch cycles to increase. There is no need to specify it.

[0011]

SUMMARY OF THE INVENTION According to the present invention, there is provided storage means in which an immediate expansion instruction for designating an immediate expansion portion of a specific instruction having an immediate operand field is arranged immediately before or after the specific instruction, and the specific instruction. Before executing the instruction, there is provided connection means for connecting the contents of the immediate operand field of the instruction with an immediate extension part specified by the immediate extension instruction arranged immediately before or after the instruction,
It is characterized in that a specific instruction is executed by using the immediate operands connected by the connecting means.

[0012]

[Operation] The operation in the above-mentioned configuration is performed by VLIW (Very L
An example will be described in which the invention is applied to an information processing device (parallel operation processing device) of a parallel system (VLIW system) of the long instruction word type. In addition, in the VLIW type information processing device,
It is processed in units of a predetermined number of fixed length instructions. This set of a predetermined number of instructions is called a VLIW type instruction (or VLIW type instruction word).

First, in the VLIW type information processing apparatus,
A VLI consisting of a fixed number of fixed-length instructions (to be processed in parallel
W type instruction) is fetched from a storage unit such as a main memory or an instruction cache. Here, if it is assumed that a VLIW type instruction including the specific instruction and the immediate extension instruction is fetched, the immediate extension portion specified by the immediate extension instruction (the OP code of the immediate extension instruction is (first selection Selected by the means) and led to the connecting means. The contents of the immediate operand field of the specific instruction placed immediately before or after the immediate extension instruction are also led to this connecting means. As a result, the extension part of the immediate value designated by the immediate value extension instruction and the content of the immediate value operand field of the specific instruction are linked by the linking means, and the immediate value operand is extended. If there is no immediate value extension instruction, instead of the immediate value extension part, for example, data with all values of 0 is guided to the concatenation means and concatenated with the contents of the immediate value operand field.

The data linked by the linking means (extended immediate value operand if an immediate value extension instruction exists) is fetched from the storage means when the specific instruction is executed (selected by the second selecting means). VLIW
It is supplied to the arithmetic unit at the position corresponding to the above specific instruction in the type instruction. As a result, when a VLIW type instruction including the specific instruction and the immediate extended instruction arranged immediately before or after the specific instruction is fetched, the immediate extended portion specified by the immediate extended instruction and the immediate operand field of the specific instruction are held. The specified operation is performed using the operand concatenated with the contents of, that is, the extended immediate operand.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of the essential part showing an embodiment of an information processing device (parallel arithmetic processing device) of the VLIW system and the pipeline control system to which the present invention is applied.
Note that the pipeline in this embodiment is assumed to have a four-stage configuration including a fetch (instruction fetch) stage F, a decode (instruction decode) stage D, an execution stage E, and a write back (write result) stage W.

In FIG. 1, 1 is a main memory that provides a storage area for various programs and data, and 11 is a main memory 1.
Is a VLIW type instruction stored in. This VLIW
The type instruction 11 is a compound instruction composed of four 32-bit instructions I # 1 to I # 4. Reference numeral 2 is an instruction cache in which a copy of a part of the instruction group stored in the main memory 1 is placed.

Reference numeral 3 is a 128-bit instruction register for holding the VLIW type instruction fetched from the instruction cache 2 in the fetch stage F. The instruction register 3 has four instruction fields 41 to 44 in which four instructions forming a VLIW type instruction are held.

In FIG. 1, an immediate value addition instruction having an OP code "add.i" designating immediate value addition is an instruction field 3
The OP code "i" that specifies the extension of the immediate operand is set to 1.
An immediate value extension instruction having "ext" is placed in the instruction field 32,
(Similar to instruction field 31) OP code "add.
The immediate addition instruction with i ”is in the instruction field 33, and the subtraction instruction with the OP code“ sub ”that specifies normal subtraction without using an immediate value (subtraction using register data of the register file as an operand) is in the instruction field 34. , The respective retained states are shown.

FIG. 2 shows the format of the essential parts of the above three types of instructions (immediate value addition instruction, immediate value extension instruction, subtraction instruction). As is clear from FIG. 2, the immediate addition instruction is executed in the 6-bit immediate operand field i6 (bits 26 to 3).
1), the immediate extended instruction has an extended immediate operand field i2 in which a 26-bit extended immediate operand, which is an extended portion of an immediate value (6-bit immediate operand), is set.
6 (bits 6 to 31).

The OP code of the instruction word of each instruction is basically composed of 9 bits of bits 0 to 8 (upper 9 bits). However, the OP code “iext” of the immediate value extension instruction is substantially only 5 bits of bits 0 to 4 in order to secure the above-mentioned 26-bit extended immediate value operand field i26 (bits 6 to 31). Can be specified, and the contents of the 4 bits of bits 5 to 9 are not affected.

In this embodiment, only when there is an immediate operation instruction among the four VLIW instructions and the immediate operation instruction is the first or third instruction of the VLIW instructions. The immediate value operand of the immediate value operation instruction can be expanded. The immediate extension instruction that specifies the extension of the immediate operand is placed immediately after the instruction having the immediate operand to be extended (immediate operation instruction), that is, the second or fourth of the four VLIW instructions. It is designed so that it can be played.

Referring again to FIG. 1, 41 to 44 are provided corresponding to the instruction fields 31 to 34 of the instruction register 3, and the OP of the instruction held in the fields 31 to 34 is OP.
A decoding circuit (DEC) that decodes a code and outputs various decode signals. Of the four decode circuits 41 to 44, the decode circuits 42 and 44 corresponding to the instruction fields 32 and 34 are OP to be decoded.
When the code is "iext", there is no operation operation for the specific signals (called mask signals) M2 and M4 of logic "1", and the operation units 92 and 94 described later, that is, NOP (no operation). ) Output signal (not shown). The decoding circuits 41 and 43 may have the same decoding function as the decoding circuits 42 and 44.

Reference numerals 52 and 54 designate an input A for inputting the output of the lower 26 bits (bits 6 to 31) of the instruction fields 32 and 34 of the instruction register 3 and the decoding circuits 42 and 4.
AND having a mask input M for inputting mask signals M2 and M4 from 4 and a 26-bit output Y
It is a gate. The AND gates 52 and 54 output the 26 bits of the input A as they are when the mask input M is "1".
When the mask input M is "0", all 26 bits of the output Y are set to "0".

Reference numeral 61 is an immediate value for connecting 26 bits of the output Y of the AND gate 52 to the output of the lower 6 bits (bits 26 to 31) of the instruction field 31 of the instruction register 3 and transmitting it as immediate data 71 of 32 bits. Data line,
Reference numeral 62 denotes 26-bit “0” data, and the lower 6 bits (bits 26 to 31) of the instruction field 32 of the instruction register 3
Is an immediate data line for connecting to the output of and transmitting as 32-bit immediate data 72. 63 is an immediate data line for connecting 26 bits of the output Y of the AND gate 54 to the output of the lower 6 bits (bits 26 to 31) of the instruction field 33 of the instruction register 3 and transmitting it as immediate data 73 of 32 bits, Reference numeral 64 is an immediate data line for connecting 26-bit "0" data to the output of the lower 6 bits (bits 26 to 31) of the instruction field 34 of the instruction register 3 and transmitting it as 32-bit immediate data 74.

Reference numerals 81 to 84 are provided corresponding to the instruction fields 31 to 34 of the instruction register 3, and an input R for inputting 32-bit operand data fetched from a register file (not shown) and an immediate data line 61. Up to 64, input I for inputting 32-bit immediate data 71 to 74, 32-bit output Y, and instruction fields 31 to 31.
4 indicates whether the instruction held in 4 is an immediate operation instruction (having an immediate operand) (decoding circuits 41 to 4).
4 is a selector having an input S to which a specific decode signal from 4 is introduced). The selectors 81 to 84 switch the output Y to the input I or the input R according to the state of the input S.

Reference numerals 91 to 94 are provided corresponding to the instruction fields 31 to 34 of the instruction register 3, and the field 31 is provided.
Is a computing unit that executes the computations designated by 34 to 34 according to the decoding results of the decoding circuits 41 to 44. Computing unit 91-
32 bits of the output Y of the selectors 81 to 84 are supplied to 94.

Next, the operation of the configuration shown in FIG. 1 will be described. First, the instructions in the main memory 1 pass through the instruction cache 2 and are fetched into the instruction register 3 in groups of 4 instructions (that is, in units of VLIW type instructions) at the fetch stage (fetch cycle) F of the instruction pipeline. Get caught. This gives V
The first instruction of the LIW type instruction is the instruction field 31 of the instruction register 3, the second instruction is the same instruction field 32, the third instruction is the instruction field 33, and the fourth instruction is the instruction field 34. Retained respectively.

In the next decode stage (decode cycle) D, the instruction fields 31 to 3 of the instruction register 3
The decoding circuits 41 to 44 perform a process of decoding the OP code of each instruction held in No. 4. In this decode stage D, the immediate data lines 61 to 64 are 32
Bit immediate data 71 to 74 are generated. And
The immediate data 71 to 74 or the data from the register file is switched by the selectors 81 to 84 in accordance with the instruction in the instruction fields 31 to 34 (a specific decode signal output from the decode circuits 41 to 44 based on the instruction fields 31 to 34).
It is passed to the arithmetic units 91 to 94 for the next execution stage E.

Here, details of generation of the immediate data 71 to 74 will be described. First, the instruction fields 31 to 34
In the instruction fields 32 and 34, there is a possibility that the immediate value extension instruction having the OP code “iext” is held as described above. The decoding circuits 42 and 44 execute the instruction when the OP code of the instruction held in the instruction fields 32 and 34 is “iext” (when the upper 5 bits of the OP code is a specific value unique to “iext”), that is, the instruction. If the instruction held in the fields 32 and 34 is an immediate extended instruction, mask signals M2 and M4 for validating the contents (26 bits of bits 6 to 31) of the extended immediate operand field i26 in the instruction. , And the computing unit 92,
A signal for instructing NOP to 94 is output.

The mask signals M2 and M4 from the decoding circuits 42 and 44 are led to the mask input M of the AND gates 52 and 54. The lower 26 bits of the instruction fields 32 and 34 (bits 6 to 3) are input to the inputs A of the AND gates 52 and 54.
1) is introduced.

The AND gates 52 and 54 receive the mask input M.
Is "1", that is, when the instruction held in the instruction fields 32 and 34 is an immediate extended instruction (having the OP code "iext"), 26 bits of the input A, that is, the instruction fields 32 and 34 Extended immediate operand field i26 which is the lower 26 bits (bits 6 to 31) of
The contents of are output to the output Y as they are.

On the other hand, when the mask input M is "0", that is, when the instruction held in the instruction fields 32 and 34 is not the immediate extension instruction, the AND gate 52 outputs the output Y.
26 bits are set to "0" regardless of the contents of the input A.

The 26 bits of the output Y of the AND gates 52 and 54 are led to the upper side of the 32-bit immediate data lines 61 and 63. The remaining lower 6 of the immediate data lines 61 and 63
On the bit side, the contents of the lower 6 bits (bits 26 to 31) of the instruction fields 31 and 33 located immediately before the instruction fields 32 and 34 are introduced, and the 32-bit immediate data on the same data lines 61 and 63. 71 and 73 are generated.

As a result, if the instruction fields 32, 34
If the immediate value extension instruction is held in, the upper 26 bits of the immediate value data 71, 73 generated on the immediate value data lines 61, 63 are the contents of the extended immediate value operand field i26 of the immediate value extension instruction (bits 6 to 31). 26 bits). The remaining lower 6 bits of the immediate data 71, 73 are the immediate operand field i6 of the instruction (in this case, always an immediate operation instruction) held in the instruction fields 31, 33 immediately before the instruction fields 32, 34. (6 bits of bits 26 to 31) itself.

That is, the instruction field 3 of the instruction register 3
If an immediate operation instruction is held in 1, 33, the immediate operand of the instruction (6 in the immediate operand field i6
Bit) is concatenated with the extended immediate operand of the immediate extended instruction (26 bits of the extended immediate operand field i26 of bits 6 to 31) if the instruction held in the instruction fields 32 and 34 is an immediate extended instruction. , 6
It is extended from 32 bits to 32 bits.

On the other hand, if the instructions held in the instruction fields 32 and 34 are other than the immediate extended instructions, the immediate data 71 and 73 generated on the immediate data lines 61 and 63 are generated.
The upper 26 bits of all are "0". The remaining lower 6 bits of the immediate data 71, 73 are the 6 bits of bits 26 to 31 of the instruction held in the instruction fields 31, 33 (the contents of the immediate operand field i6 in the case of an immediate operation instruction). Become.

Therefore, when the instruction fields 31 and 33 hold the immediate operation instructions and the instruction fields 32 and 34 hold instructions other than the immediate extension instructions, the immediate data 71 on the immediate data lines 61 and 63 are stored. , 73 are 6 bits of the immediate operand field i6 of the immediate operation instruction of the instruction fields 31 and 33, which are expanded as they are to 32 bits as unsigned data (the upper 26 bits are all “0”).

In the example of FIG. 1, in the instruction fields 31, 32, 33, and 34 of the instruction register 3, an immediate addition instruction having an immediate operand, an immediate extension instruction having an extended immediate operand, and an immediate addition instruction having an immediate operand are provided. ，
It holds a normal subtraction instruction that has no immediate operands. In the decode stage D in the state of FIG. 1, the mask signal M2 from the decode circuit 42 corresponding to the immediate extension instruction is "1", and the mask signal M4 from the decode circuit 44 corresponding to the subtraction instruction is "0". .. Further, the decoding circuit 42 outputs a signal instructing NOP to the arithmetic unit 92.

When the mask signal M2 from the decoding circuit 42 is "1", the 26 bits of the extended immediate operand field i26 of the immediate extended instruction of the instruction field 32 are A
It is directly output to the upper side of the immediate data line 61 by the ND gate 52. To the remaining lower 6 bits of the immediate data line 61, 6 bits of the immediate operand field i6 of the immediate addition instruction of the instruction field 31 are introduced. As a result, 32-bit immediate data 71 is generated on the immediate data line 61 by expanding the 6-bit immediate operand of the immediate addition instruction of the instruction field 31 with the 26-bit extended immediate operand of the immediate extended instruction of the instruction field 32. FIG. 3 shows the relationship between the immediate operand of the immediate addition instruction and the extended immediate operand of the immediate extension instruction and the immediate data (71).

The immediate data 71 on the immediate data line 61 is led to the input I of the selector 81. Input S of selector 81
A specific decode signal from the decode circuit 41 indicating that the instruction held in the instruction field 31 is an immediate value operation instruction (here, an immediate value addition instruction) is guided to. In this case, the selector 81 switches the output Y to the input I side.
As a result, the expanded immediate data 71 guided to the input I of the selector 81 is selectively output from the output Y and passed to the arithmetic unit 91, and the arithmetic operation (addition in this case) in the next execution stage E is performed. Calculation).

As described above, in the present embodiment, the immediate value addition instruction (immediate value operation instruction) and the immediate value extension instruction are combined, and it is as if
The specified operation (addition operation) can be performed using the expanded immediate value as if it were one instruction having a 2-bit immediate value.

When the mask signal M4 from the decoding circuit 44 is "0", the output Y of the AND gate 54 is 26.
All bits are set to "0". This 26-bit "0"
The data is guided to the upper side of the immediate data line 63. In the remaining lower 6 bits of the immediate data line 63, the immediate operand field i6 of the immediate addition instruction of the instruction field 33
6 bits are derived. As a result, the immediate data line 63
Above, the 6-bit immediate operand of the immediate addition instruction in the instruction field 33 is simply expanded to 32 bits as unsigned 6-bit data (upper 26 bits are all "0").
Generated immediate data 73 is generated.

The immediate data 73 on the immediate data line 63 is led to the input I of the selector 83. Input S of selector 83
A specific decode signal from the decode circuit 43 indicating that the instruction held in the instruction field 33 is an immediate value operation instruction (here, an immediate value addition instruction) is introduced to the. In this case, the unexpanded immediate data 73 led to the input I of the selector 83 is selectively output from the output Y and passed to the arithmetic unit 93, and the arithmetic operation at the next execution stage E (here, It is used for addition operation).

Next, the instruction field 3 of the instruction register 3
In the arithmetic unit 92 corresponding to 2, the operation is not performed by the signal instructing the NOP output from the decoding circuit 42 in response to the immediate extension instruction held in the instruction field 32. In this case, the immediate data 7 on the immediate data line 62
2 is discarded.

Next, the instruction field 3 of the instruction register 3
In the selector 84 corresponding to 4, the data of the register file designated by the normal subtraction instruction (in the register designation field) held in the instruction field 34 is input R
Be led to. A specific decode signal from the decode circuit 44 indicating that the instruction held in the instruction field 34 is not an immediate operation instruction is introduced to the input S of the selector 84. In this case, the selector 84 switches the output Y to the input R side. As a result, the data of the register file guided to the input R of the selector 84 is selectively output from the output Y and passed to the arithmetic unit 94, and the arithmetic operation at the next execution stage E (subtraction arithmetic here) is performed. Be offered to. In this case, the immediate data 74 on the immediate data line 64 is discarded.

According to this embodiment, assuming that there are six kinds of operations (functions) of immediate value operation instructions, the number of kinds of instructions to be increased increases the 6-bit immediate value operand of the immediate value operation instruction to 32 bits. There is only one type of immediate extension instruction that specifies that. On the other hand, in the conventional method in which the instruction corresponding to the size of the immediate operand is prepared for each function, the number of types of instructions to be increased is 6 for the type of operation (function) of the immediate value operation, that is, 6. Five types of instructions are required more than this method.

In the above embodiment, the case where the instruction to be expanded (having an immediate value) by the immediate value expansion instruction is the immediate value addition instruction is explained. However, the target instruction is an immediate value subtraction instruction, an immediate value multiplication instruction, or the like. Other immediate value calculation instructions may be used, and the function of immediate value calculation does not matter.

In the above embodiment, the case where the extension target instruction by the immediate extension instruction is arranged immediately before the immediate extension instruction has been described, but the present invention is not limited to this. For example, as shown in FIG. 4, it is applicable even when it is arranged immediately after. In this case, the decoding circuit 4 corresponds to the position in the VLIW type instruction in which the immediate value extension instruction is allowed to exist.
Decode circuits corresponding to 2, 44, AND gate 52,
An AND gate corresponding to 54 (a selector for selecting either the contents of the extended immediate operand field i26 of the immediate extended instruction or 26-bit data of all "0") may be provided and the instruction position immediately before that may be provided. Of course, it is necessary to provide immediate data lines corresponding to the immediate data lines 61 and 63.

Further, in the above-mentioned embodiment, the present invention is applied to VLIW.
The case where the present invention is applied to the information processing apparatus of the method has been described. However, an information processing apparatus that executes instructions one by one, particularly RI
It is also applicable to an information processing device adopting the SC type architecture. In this case, the arrangement of the extension target instruction (for example, immediate value addition instruction) and the immediate value extension instruction, and the generation of the immediate data (extended immediate value) will be briefly described with reference to FIGS. To do. It should be noted that FIG. 5A shows that when the instruction array is in the order of immediate value addition instruction and immediate value extension instruction, FIG.
(B) is a case where the instruction array is in the order of immediate expansion instruction and immediate addition instruction.

First, in the case of FIG. 5A, the immediate value addition instruction is decoded, and at the same time, the next immediate value extension instruction is fetched. Immediately after fetching this immediate expansion instruction, this instruction immediately executes the immediate operand (i
Recognize that it is an instruction for extending 6), delay the execution stage of the immediately preceding instruction (immediate value addition instruction), and replace the immediate value operand with the extended one in the meantime, or until the next pipeline cycle. The immediate operand is replaced with the expanded immediate operand, the pipeline is advanced as it is, and the operation is executed using the expanded immediate operand (immediate data).

Next, in the case of FIG. 5B, it is recognized that the immediate value extension instruction is decoded and the immediate value operand of the next instruction (immediate value addition instruction) is extended, and the next instruction (immediate value addition instruction) is executed.
Before execution of, the immediate operand of the instruction (immediate addition instruction) is replaced with the expanded immediate operand (immediate data). In the method of FIG. 5B, compared with the method of FIG. 5A, from the recognition of the expansion to the replacement with the expanded immediate value,
A margin of 2 pipeline cycles can be secured.

In the above embodiment, the case where the size of the extended immediate operand set in the immediate extended instruction is limited to 26 bits has been described. However, the size is not limited to this, and a plurality of predetermined sizes are used. One of them may be set. However, it is necessary to prepare a plurality of types of immediate immediate extension instructions corresponding to the sizes of extended immediate operands. Further, connection means (immediate data line) for connecting the immediate operand of the immediate operation instruction and the extended immediate operand of the immediate extension instruction is provided for each type of the size of the extended immediate operand, and one of them is provided depending on the immediate extension instruction. Must be selected.

In this method, assuming that the operation (function) type of the immediate operation instruction is 6, and the size of the immediate operand is three types, that is, an immediate operand without extension and two extended immediate operands, the instruction types that increase Is 2 which is the number of types of extended immediate operand size (for two types of immediate extended instructions). On the other hand, in the conventional method in which an instruction corresponding to the size of an immediate operand is prepared for each function, the number of types of instructions to be increased is: operation (function) type x number of types of extended immediate operand size = 6 x 2 = 12 Yes, 10 more instructions are required than this method. This difference in instruction type increases as the number of types of extended immediate operand sizes increases.

[0054]

As described in detail above, according to the present invention,
An immediate value extension instruction that specifies an immediate value extension part of a specific instruction (immediate value operation instruction) having an immediate operand field is provided and placed immediately before or after the specific instruction. When executing this specific instruction, first The extended immediate operand specified by the immediate extended instruction placed immediately before or after the immediate operand of the instruction is concatenated with the contents of the immediate operand field to generate an extended immediate operand. Since the specific instruction is executed by using the configuration, the following effects can be obtained.

(1) Regardless of the type of instruction having an immediate value (immediate value operation instruction), immediate value extension can be performed by an immediate value extension instruction of the same type, so an instruction repertoire (type of OP code)
Can be minimized. Therefore, OP
The size of the code field does not increase, and the size of the operand designating field is not restricted.

(2) When applied to an information processing apparatus of a parallel processing system, an immediate operation instruction and an immediate extension instruction for expanding the immediate instruction (immediate operand of the same instruction) are combined, and it is as if having an extended immediate operand. Since it can be treated as if it were one instruction, an immediate operand having a size exceeding the size of the immediate operand field that can be secured in the instruction word can be specified without increasing the number of instruction fetch cycles.

(3) An immediate immediate extended instruction can be specified just before or after an ordinary immediate arithmetic operation instruction, and an extended immediate operand can be specified, and an immediate immediate operand alone can specify an immediate operand of the instruction itself. Therefore, the instruction system, and hence the hardware configuration, can be simplified as compared with the conventional method in which the instruction repertoire significantly increases.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a main part showing an embodiment of an information processing device (parallel arithmetic processing device) of a VLIW system and a pipeline control system to which the present invention is applied.

FIG. 2 is a diagram showing a format of essential parts of an immediate value addition instruction, an immediate value extension instruction, and a subtraction instruction used in the embodiment.

FIG. 3 is a diagram showing a relationship between an immediate operand of an immediate addition instruction and an extended immediate operand of an immediate extended instruction arranged immediately after the instruction in the embodiment, and immediate data.

FIG. 4 shows the positions of immediate value addition instructions and immediate value extension instructions.
7 is a diagram showing the relationship between the immediate operand of the immediate addition instruction and the extended immediate operand of the immediate extended instruction, and the immediate data in the case opposite to the example of FIG.

FIG. 5 is a diagram showing a relationship between an immediate value operand of an immediate addition instruction and an extended immediate operand of an immediate extension instruction and immediate data in an information processing apparatus adopting a RISC type architecture.

[Explanation of symbols]

1 ... main memory, 2 ... instruction cache, 3 ... instruction register,
31-34 ... Instruction field, 41-44 ... Decode circuit, 52, 54 ... AND gate (first selecting means), 6
1-64 ... Immediate data line (connecting means), 71-74 ... Immediate data, 81-84 ... Selector (second selecting means),
91-94 ... Operation unit.

[Procedure amendment]

[Submission date] January 24, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (2)

[Claims] 1. An immediate value extension instruction for designating an immediate extension part of a specific instruction having an immediate operand field is arranged immediately before or after the specific instruction, and a storage means before executing the specific instruction. A linking unit for linking the contents of the immediate operand field of the instruction with an extended portion of the immediate value designated by the immediate extended instruction placed immediately before or after the same instruction, and connected by the linking unit. An immediate operand extension method characterized in that the specific instruction is executed using an immediate operand. 2. In an information processing apparatus of a parallel processing system having the same number of arithmetic units for processing a plurality of fixed-length instructions in parallel, an immediate value designating an immediate portion of a specific instruction having an immediate operand field. When an extended instruction is arranged in pairs with the specific instruction, and a plurality of instructions including a pair of the specific instruction and the immediate extended instruction are fetched from the storage means as instructions to be processed in parallel, A first selecting means for selecting an immediate portion to be specified by the immediate extending instruction; and an output of the first selecting means as contents of an immediate operand field of the specific instruction paired with the immediate extending instruction. Concatenation means for concatenation, and the operation for executing the operation designated by the instruction by selecting the immediate operands concatenated by the concatenation means when the specific instruction is executed Second; and a selection means, the immediate operand extension method being characterized in that so as to execute the specific instruction using an immediate operand which is connected by said connecting means for outputting the.