JPH051509B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a switched capacitor integration circuit using an operational amplifier, and particularly to an improvement in the circuit in which the offset voltage of the operational amplifier is compensated for.

[Technical background of the invention]

As is well known, in the above-mentioned integrating circuit, it is necessary to compensate the offset voltage of the operational amplifier so that it does not affect the output voltage. That is, FIG. 1 shows a conventionally widely known integrating circuit, which is composed of an operational amplifier 11, a resistor _R1 , and a capacitor _C1 . In this case, if the operational amplifier 11 is assumed to be ideal and its offset voltage _VOS is equivalently replaced with the DC voltage source 12 as shown, the input voltage
The output voltage V _OUT with respect to V _IN is V _OUT = -1/SR ₁ C ₁ V _IN + (1 + 1/SR ₁ C ₁ ) V _OS in the S dimension, and when SR ₁ C ₁ ≪1, the operational amplifier 11 The offset voltage V _OS is approximately multiplied by the gain of the integrating circuit and appears in the output voltage V _OUT .

Furthermore, in recent years, many so-called switched capacitor integrating circuits have appeared, in which a switched capacitor is used as an impedance circuit in place of the resistor _R1 , in order to improve the accuracy of the integrating circuit. In this case as well, the offset voltage V _OS of the operational amplifier 11 is approximately equal to the input voltage V _IN (1
+C′/C ₁ ) and appears in the output voltage V _OUT .

Therefore, as a measure to compensate for the offset voltage V _OS of the operational amplifier 11, a means as shown in USP-4365204 has been considered. That is, as _shown in _FIG .
1 - and applied to the capacitor C ₁ ,
The output voltage V _OUT is obtained via the buffer circuit 17. When compensating the offset voltage _VOS , the switches 18 to 20 are turned on by the clock signal that initializes the circuit, the capacitor _C3 is charged with the offset voltage _VOS , and the switch is sent via the buffer circuit 21 and the switch 20. By supplying it to the docapacitor circuit 16, the offset voltage _VOS is subtracted from the input voltage _VIN for compensation.

[Problems with background technology]

However, in the conventional offset voltage compensation means as described above, although the offset voltage V _OS of the operational amplifier 11 is compensated, the buffer circuit 17
Since no consideration is given to the offset voltage of the buffer circuit 17, there is a problem in that the offset voltage of the buffer circuit 17 ends up influencing the output voltage _VOUT .

[Purpose of the invention]

This invention has been made in consideration of the above circumstances, and it is possible to compensate for the offset voltage of an operational amplifier with a simple structure and without using a circuit where offset voltage is a problem, such as a buffer circuit. The object of the present invention is to provide an extremely good switched capacitor integration circuit.

[Summary of the invention]

That is, the switched capacitor integrating circuit according to the present invention includes: a first capacitor; a first switch connected between one end of the first capacitor and an input terminal; a second switch connected to the other end of the capacitor, a third switch connected between one end of the first capacitor and the constant potential source, and a third switch connected between the other end of the first capacitor and the constant potential source. It has an impedance circuit composed of a fourth switch connected between it and the potential source. Further, a second capacitor has one end connected to the second switch of the impedance circuit, an inverting input end connected to the other end of the second capacitor, and a non-inverting input end connected to the constant potential source. a fifth switch connected between the output terminal and the inverting input terminal of the operational amplifier; and a sixth switch connected between one end of the second capacitor and the constant potential source. a feedback load circuit connected between the output end of the operational amplifier and one end of the second capacitor; and a feedback load circuit that periodically controls the first and second switches with a first signal having a constant period. The third to the third switches are controlled to be in the on state or the off state, and the third to the third switches are controlled to be in the on state or the off state, and the switches are controlled to be in the on state when the first and second switches are in the off state by a second signal synchronized with the first signal. and a control circuit that periodically controls the switch No. 6 to turn on or off.

According to the above configuration, the impedance circuit in the integrating circuit includes the first to fourth switches and the first switch.
A switched capacitor is used, and a fifth and sixth switch and a second capacitor are connected to the inverting input terminal of the operational amplifier. Then, the first
The switching of the first to sixth switches is controlled by the second signal. As a result, it is possible to provide an extremely good switched capacitor integration circuit which has a simple configuration and can reliably compensate for the offset voltage of an operational amplifier without using a circuit such as a buffer circuit where offset voltage is a problem. Furthermore, since a switched capacitor is used, offset drift of the amplifier does not occur even during long-time operation.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 3, 31 is an input terminal to which an input signal voltage V _IN is applied. This input terminal 31 is connected to a switched capacitor circuit 36 as an impedance circuit consisting of switches 32 to 35 and a capacitor _C11 , and a capacitor C11.
It is connected to the inverting input terminal (-) of the operational amplifier 37 via _C12 in series. The non-inverting input terminal (+) of this operational amplifier 37 is connected to a ground terminal as a reference potential terminal. Further, the output terminal of the operational amplifier 37 is connected to an output terminal 38 for obtaining the output signal voltage V _OUT of the integrating circuit.

Here, a switch 39 is connected between the side of the capacitor _C12 connected to the inverting input terminal (-) of the operational amplifier 37 and the output terminal of the operational amplifier 37.
is mediated. Further, a capacitive element is included between the side of the capacitor C ₁₂ connected to the switched capacitor circuit 36 and the output terminal of the operational amplifier 37, so that the operational amplifier 37 operates as an integrating circuit. A feedback load circuit 40 is interposed. Furthermore, among the above capacitor C ₁₂ ,
The side connected to the switched capacitor circuit 36 is grounded via a switch 41.

And each of the above switches 32 to 35, 39,
41 is controlled to turn on and off by clock signals φ ₁ and φ ₂ that do not overlap with each other, as shown in FIG. That is, the switches 32 and 33 are turned on when the clock signal _φ1 is at the H (high) level, and turned off when the clock signal φ1 is at the L (low) level. Also, other switches 3
4, 35, 39, and 41, the clock signal φ ₂ is H.
It is turned on when it is at level, and turned off when it is at L level.

The operation of the above configuration will be described below with reference to the timing diagram shown in FIG.
That is, assuming that the input signal voltage V _IN as shown in FIG. 5 is applied to the input terminal 31, the switches 39 and 41 are turned on during the period when the lock signal φ ₂ is at the H level, so that Since the operational amplifier 37 has a voltage follower configuration, the offset voltage V _OS of the operational amplifier 37 is outputted to the output terminal 38. At this time, the capacitor
Since the side connected to the switched capacitor circuit 36 is grounded through the switch 41, _C12 is charged with the offset voltage _VOS . Also, at this time, since the switches 34 and 35 are on, both ends of the capacitor _C11 of the switched capacitor circuit 36 are grounded, so that the capacitor C11 is in a discharged state.

Next, during the period when the clock signal _φ1 is at H level,
Switches 32 and 33 are turned on, and the input signal voltage V _IN is applied to the capacitor C11 via the capacitor _C11 .
It is applied to the side connected to the switched capacitor circuit 36 of _C12 . However, as mentioned above,
Since the offset voltage _VOS of the operational amplifier 37 is held charged in the capacitor _C12 ,
Eventually, the voltage V _IN -V _OS obtained by subtracting the offset voltage V _OS from the input signal voltage V _IN is applied to the inverting input terminal (-) of the operational amplifier 37, and a normal integration operation is performed. The output signal voltage V _OUT as shown in FIG. 5 is generated. That is, during the period when the clock signal φ ₁ is at H level, the side of the capacitor C ₁₂ connected to the switched capacitor circuit 36 is kept at a constant potential due to the feedback action of the feedback load circuit 40, and the operational amplifier 3
The voltage applied to the inverting input terminal (-) of No. 7 is obtained by calculating the offset voltage V _OS from the input signal voltage V _IN . Therefore, the output signal voltage V _OUT during the period when the clock signal φ ₁ is at H level is not affected by the offset voltage V _OS .

Therefore, according to the configuration of the above embodiment, the switches 39, 41 and the capacitor _C12 are extremely simple, without using a circuit where offset voltage is a problem like the conventional buffer circuit 17. The offset voltage V _OS of the operational amplifier 37 can be reliably compensated with a simple configuration. Furthermore, the output signal voltage V _OUT is equal to the offset voltage V _OS during the period when the clock signal φ ₂ is at H level.
Therefore, in order to remove the output voltage during this period, a circuit that samples and holds the output signal voltage V _OUT at the falling edge of the clock signal φ ₁ may be connected to the output terminal 38. Furthermore, when the above-mentioned integrating circuits are connected in series in multiple stages, a switched capacitor circuit that is not easily affected by offset voltage is connected to the final stage, and the high level of the clock signal _φ1 is connected.
It is only necessary to input the output signal voltage to the switched capacitor circuit during the level period. Further, in the above embodiment, the switched capacitor circuit 36 is used as the impedance circuit, but this impedance circuit may be simply replaced with a capacitor, or an equivalent negative resistance formed by a switched capacitor may be used. It is a good thing.

Further, in the above embodiment, each switch 32 to 35, 39, 41 is clocked by two clock signals φ ₁ and φ ₂
Although switching control is carried out in this embodiment, this may be controlled by using three non-overlapping clock signals φ ₁ to φ ₃ as shown in FIG. That is, the switches 32 and 33 are turned on when the clock signal φ ₁ is at the H level, and turned off when the clock signal φ 1 is at the L level, and the switches 34 and 35 are turned on when the clock signal φ ₂ is at the H level, and turned off when the clock signal φ 2 is at the H level. Even if the switches 39 and 41 are set to be in the off state when the clock signal _φ3 is at the high level, and the switches 39 and 41 are set to be in the on state when the clock signal φ3 is at the high level, and are turned off when the clock signal is at the low level, substantially the same operation as described above will be performed. be able to.

Next, FIGS. 7 to 9 show specific examples of the feedback load circuit 40, respectively. First, what is shown in Figure 7 is the capacitor _C13 and switch 4.
2 are connected in series. In this case, switch 42 allows the integrator circuit to output two clock signals φ ₁ ,
When using _φ2 , the clock signal _φ1 is turned on when it is at H level, and when three clock signals _φ1 to φ3 are used, clock signal _φ3 is _at H level.
It is controlled so that it is in the off state when it is at the level.

Furthermore, the one shown in FIG. 8 uses a switched capacitor circuit 47 consisting of switches 43 to 46 and a capacitor ₁₄ . In this case, no matter which of the clock signals shown in FIG. 4 or FIG. 6 is used by the integrating circuit, the switches 43 and 44 are turned on when the clock signal φ ₁ is at H level, and the switches 45 and 46 are turned on. is controlled so that the clock signal _φ2 is turned on when it is at H level.

Furthermore, the circuit shown in FIG. 9 is a combination of the circuit shown in FIG. 7 and the circuit shown in FIG. In this case, the on/off control of each of the switches 42 to 46 is performed in the same manner as explained in FIGS. 7 and 8, respectively. Here, FIG. 10 shows the feedback load circuit 40 of the circuit shown in FIG.
9 shows the overall circuit configuration when the circuit shown in FIG. 9 is used.

Next, FIG. 11 shows an example of use in a case where a band rejection filter circuit is constructed using the integrating circuit according to the present invention. That is, this band elimination filter circuit includes an integrating circuit 52 consisting of capacitors C ₁₅ to C ₁₇ , switches 48 to 50, and an operational amplifier 51, to which the output of this integrating circuit 52 is supplied, a switched capacitor circuit 53, and a capacitor C ₁₈ , C ₁₉ , switches 54 to 56 and an operational amplifier 57;
a switched capacitor circuit 59 and a capacitor C ₂₀ for feeding back the output of 8 to the integrating circuit 52;
It depends on this. The switched capacitor circuit 53 includes switches 60 to 63 and a capacitor _C21 , and the switched capacitor circuit 59 includes switches 64 to 67 and a capacitor _C22 .

Here, when operating the circuit shown in FIG. 11 as a band elimination filter, switches 48, 49,
54, 55 are turned off, switch 56 is turned on, switches 60, 63 to 65 are turned on when clock signal _φ1 is at H level, and switches 61, 62, 66, 67 are set to the clock signal. It is controlled so that it is turned on when φ ₂ is at H level. In this case, since the outputs of the operational amplifiers 51 and 57 are sampled even when either of the two clock signals φ ₁ or φ ₂ is at H level,
Switch 48, 4 for offset voltage compensation
9, 50, 54 to 56 are clock signals φ ₁ , φ ₂
It is necessary to control with a third clock signal _φ3 that does not overlap with the clock signal φ3. In other words, clock signal _φ3 is high.
When the level is reached, switches 48, 49, 54, and 55 are turned on, and switches 50 and 56 are turned off.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as detailed above, according to the present invention, it is possible to eliminate the need for using a circuit where offset voltage is a problem, such as a buffer circuit, for example.
It is possible to provide an extremely good switched capacitor integration circuit which has a simple configuration and can reliably compensate for the offset voltage of an operational amplifier.

[Brief explanation of the drawing]

1 and 2 are block circuit configuration diagrams showing conventional integration circuits, FIG. 3 is a block circuit configuration diagram showing an embodiment of the switched capacitor integration circuit according to the present invention, and FIG. 4 is the same. A timing diagram showing clock signals for switch control in the embodiment,
FIG. 5 is a timing diagram for explaining the operation of the same embodiment, FIG. 6 is a timing diagram showing a modified example of the clock signal for switch control of the same embodiment, and FIGS. FIG. 10 is a block circuit diagram showing a specific example of the feedback load circuit of the example, FIG. 10 is a block circuit diagram showing a state in which the feedback load circuit shown in FIG. 9 is connected in the same embodiment, and FIG. FIG. 2 is a block circuit configuration diagram showing an example of use when applied to a filter circuit. 31...Input terminal, 32-35...Switch,
36... Switched capacitor circuit, 37... Operational amplifier, 38... Output terminal, 39... Switch, 40... Feedback load circuit, 41-46... Switch, 47... Switched capacitor circuit, 48
~50... Switch, 51... Operational amplifier, 52
...Integrator circuit, 53...Switched capacitor circuit, 54-56...Switch, 57...Operation amplifier, 58...Integrator circuit, 59...Switched capacitor circuit, 60-67...Switch.

Claims (1)

[Claims] 1. A first capacitor, a first switch connected between one end of the first capacitor and an input terminal, and a first switch connected to the other end of the first capacitor. a second switch, and a third switch connected between one end of the first capacitor and the constant potential source, and a third switch connected between the other end of the first capacitor and the constant potential source. a second capacitor having one end connected to the second switch of the impedance circuit; an inverting input end connected to the other end of the second capacitor; an operational amplifier whose non-inverting input terminal is connected to the constant potential source; a fifth switch connected between the output terminal of the operational amplifier and the inverting input terminal; one end of the second capacitor and the constant potential source; a sixth switch connected between the potential source; a feedback load circuit connected between the output terminal of the operational amplifier and one end of the second capacitor; and a first signal having a constant period. a second switch that periodically controls the first and second switches to be on or off, and is synchronized with the first signal;
The third to sixth switches are switched on so that the first and second switches are turned on when the first and second switches are off.
1. A switched capacitor integration circuit comprising: a control circuit for periodically controlling a switch to an on state or an off state. 2 The control circuit periodically switches the third and fourth switches using a second signal synchronized with the first signal so that the switches are turned on when the first and second switches are off. a third signal that is controlled to be in an on state or an off state and synchronized with the first signal;
The fifth and sixth switches are switched on so that the first to fourth switches are turned on when they are off with a signal of
2. The switched capacitor integration circuit according to claim 1, wherein the switch is periodically controlled to be on or off. 3 The feedback load circuit has a seventh circuit connected in series.
and a third capacitor, and the seventh switch is controlled to be on or off by the first signal. The switched capacitor integrator circuit described in Sec. 4 The feedback load circuit has an input end and an output end, and includes a third capacitor, a seventh switch connected between one end of the third capacitor and the input end, and a seventh switch connected between one end of the third capacitor and the input end. an eighth switch connected between the other end of the capacitor and the output end;
a ninth switch connected between one end of the third capacitor and the constant potential source; and a tenth switch connected between the other end of the third capacitor and the constant potential source. The seventh and eighth switches are controlled to be on or off by the first signal, and the ninth and tenth switches are controlled to be on or off by the second signal. 3. The switched capacitor integration circuit according to claim 1 or 2, wherein the switched capacitor integration circuit is controlled to be in an OFF state.