JPH0515438U - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0515438U JPH0515438U JP060426U JP6042691U JPH0515438U JP H0515438 U JPH0515438 U JP H0515438U JP 060426 U JP060426 U JP 060426U JP 6042691 U JP6042691 U JP 6042691U JP H0515438 U JPH0515438 U JP H0515438U
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor device
- present
- stress
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】 半導体装置のダイパット２下部に水分が存在
した場合、実装時の熱により、ダイパット２下部におい
て水蒸気爆発が発生する。そのことによってダイパット
２端辺に応力が集中しパッケージクラックへと発展する
が、本発明はパッケージクラックを防止することができ
る半導体装置を提供するものである。
【構成】 ダイパット２およびリード端子１内部先端の
下部にシート６を接着した。このことにより、ダイパッ
ト２の下部に水分が存在していて、それが、実装時の加
熱で水蒸気となってダイパット２の端辺に集中的に応力
が発生したとしても、その応力が分散されて、パッケー
ジクラックの発生が防止される。
(57) [Abstract] [Purpose] When moisture is present under the die pad 2 of a semiconductor device, a steam explosion occurs under the die pad 2 due to heat during mounting. As a result, stress concentrates on the edges of the die pad 2 and develops into package cracks. The present invention provides a semiconductor device capable of preventing package cracks. [Structure] A sheet 6 is bonded to the lower part of the inner tip of the die pad 2 and the lead terminal 1. As a result, even if water is present in the lower part of the die pad 2 and it becomes steam due to the heating during mounting and stress is intensively generated at the edge of the die pad 2, the stress is dispersed. The generation of package cracks is prevented.
Description
【０００１】[0001]
本考案の半導体装置の製造工程においてダイパットおよび、リード端子内部先 端の下部を覆うシートの接着を伴う半導体装置に関するものである。 The present invention relates to a semiconductor device in which a die pad and a sheet covering a lower portion of a leading end of a lead terminal are attached in a manufacturing process of the semiconductor device of the present invention.
【０００２】[0002]
近年、電子機器の小型化にともない半導体装置の小型軽量化，ファインピッチ 化が必須となっている。しかしながら半導体素子に対して半導体装置のパッケー ジ外形の小型化によって、実装時に生ずるパッケージクラックが問題となってい る。図２は、従来の半導体装置の断面図で、１はリード端子、２はダイパット、 ３は半導体素子、４は半導体素子３と外部リード端子とを電気的につなぐＡｌ線 、５は封止樹脂である。現在のところ、図２に示すような構造が工程の単純化と いう点で最善であると考えられてきた。 In recent years, along with the miniaturization of electronic devices, it has become essential to reduce the size and weight of semiconductor devices and achieve finer pitch. However, with the miniaturization of the package outline of the semiconductor device with respect to the semiconductor element, package cracks that occur during mounting have become a problem. 2 is a sectional view of a conventional semiconductor device, 1 is a lead terminal, 2 is a die pad, 3 is a semiconductor element, 4 is an Al wire for electrically connecting the semiconductor element 3 and an external lead terminal, and 5 is a sealing resin. Is. At present, the structure shown in FIG. 2 has been considered to be the best in terms of process simplification.
【０００３】[0003]
しかしながら、上記従来の構造では、ダイパット２の下部に十分な水分が存在 した場合、製造実装時に熱により水蒸気爆発を起こすため、応力がダイパット２ の端辺部分に集中し、パッケージクラックに発展する可能性があるという欠点を 有している。 However, in the above-mentioned conventional structure, when sufficient moisture exists in the lower part of the die pad 2, a steam explosion occurs due to heat at the time of manufacturing and mounting, so stress concentrates on the edge part of the die pad 2 and a package crack may develop. It has the disadvantage that
【０００４】 本考案は、このような従来品にあった問題を解決するもので、実装時にダイパ ット２の端辺にかかる応力を分散しパッケージクラックを防止するものである。The present invention solves the above-described problems in the conventional products, and disperses the stress applied to the edges of the die pad 2 during mounting to prevent package cracks.
【０００５】[0005]
この目的を達成するために、本考案の半導体装置にはダイパットの下部および リード端子内部先端の下部を覆うシートを接着した構造を有している。 In order to achieve this object, the semiconductor device of the present invention has a structure in which a sheet covering the lower part of the die pad and the lower part of the inner end of the lead terminal is bonded.
【０００６】[0006]
【作用】 この構造によって製品実装時の熱によりダイパット２の端辺に発生する応力を 分散させることができ、パッケージクラックを防止することができる。With this structure, the stress generated at the edge of the die pad 2 due to the heat at the time of mounting the product can be dispersed, and the package crack can be prevented.
【０００７】[0007]
以下本考案の実施例について、図面を参照しながら説明する。 Embodiments of the present invention will be described below with reference to the drawings.
【０００８】 図１は本考案の一実施例の断面図で、前述の図２の従来例と同一符号は同等部 分を示し、その説明は重複を避ける。本実施例に示すように、ダイパット２およ びリード端子１内部先端の下部にシート６を接着した構造を取っている。シート ６は耐熱性に優れた、たとえばポリイミドシートを用いればよい。FIG. 1 is a cross-sectional view of an embodiment of the present invention, in which the same reference numerals as those in the conventional example of FIG. 2 denote the same parts, and the description thereof will be omitted. As shown in this embodiment, a structure is adopted in which a sheet 6 is bonded to the lower part of the inner tip of the die pad 2 and the lead terminal 1. As the sheet 6, for example, a polyimide sheet having excellent heat resistance may be used.
【０００９】[0009]
以上のように本考案は、ダイパット２およびリード端子内部先端の下部にシー ト６を接着することにより、実装時の水蒸気爆発により生ずるダイパット端辺の 応力を分散させることができ、パッケージクラックの発生を防止することが実現 できるすぐれた構造を有するものである。 As described above, according to the present invention, by bonding the sheet 6 to the lower part of the tip of the die pad 2 and the inside of the lead terminal, the stress on the edge of the die pad caused by the steam explosion at the time of mounting can be dispersed, and the package crack is generated. It has an excellent structure that can prevent the above.
【図１】本考案における実施例における半導体装置の断
面図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】従来の半導体装置の断面図FIG. 2 is a sectional view of a conventional semiconductor device.
１ リード端子 ２ ダイパット ３ 半導体素子 ４ Ａｌ線 ５ 封止樹脂 ６ シート 1 Lead terminal 2 Die pad 3 Semiconductor element 4 Al wire 5 Sealing resin 6 Sheet
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/31 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/31
Claims (1)
パットおよびリード端子内部先端の下部を覆うシートを
備えた半導体装置。1. A semiconductor device sealed with a resin, comprising a die pad and a sheet for covering a lower part of a tip of an inside of a lead terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP060426U JPH0515438U (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP060426U JPH0515438U (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0515438U true JPH0515438U (en) | 1993-02-26 |
Family
ID=13141888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP060426U Pending JPH0515438U (en) | 1991-07-31 | 1991-07-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0515438U (en) |
-
1991
- 1991-07-31 JP JP060426U patent/JPH0515438U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5859387A (en) | Semiconductor device leadframe die attach pad having a raised bond pad | |
| KR960012449A (en) | Semiconductor device | |
| KR940016632A (en) | Semiconductor device and manufacturing method | |
| JPH07147347A (en) | Integrated circuit device | |
| EP0750342A2 (en) | Semiconductor device having the inner end of connector leads placed onto the surface of semiconductor chip | |
| JPH079961B2 (en) | Resin-sealed semiconductor device | |
| JPH088388A (en) | Lead frame and semiconductor device constructed using the same | |
| JPH0823068A (en) | Lead frame and semiconductor device constructed using the same | |
| JPS61237458A (en) | Resin-sealed type semiconductor device | |
| JPS62115752A (en) | Semiconductor device | |
| JPH0447966Y2 (en) | ||
| JPH0637230A (en) | Semiconductor device | |
| JPH05190735A (en) | Semiconductor device | |
| JP3013611B2 (en) | Method for manufacturing semiconductor device | |
| JPS6365655A (en) | Resin-sealed semiconductor device | |
| JPS5826176B2 (en) | Resin-encapsulated semiconductor device | |
| JPS6244531Y2 (en) | ||
| JP2941479B2 (en) | Semiconductor device | |
| JPH05291460A (en) | Resin-sealed semiconductor flat package | |
| JP2845600B2 (en) | Lead frame | |
| JP2834192B2 (en) | Resin-sealed semiconductor device | |
| JPH02205056A (en) | Integrated circuit package | |
| JPH0739237Y2 (en) | Semiconductor device | |
| JPH06244335A (en) | Resin-sealed semiconductor device | |
| JPH03116767A (en) | Package of ic |