JPH05165657A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize the semiconductor integrated circuit equipped with a program run-away detecting and controlling circuit to stop a peripheral equipment connected to the input/output terminal of a microcontroller in a safe state by detecting the generation of CPU program run-away and initializing a system concerning the microcontroller system equipped with a CPU. CONSTITUTION:A watchdog timer 5, memory control circuit part 7 and memory 8 are installed, the run-away is detected by the watchdog timer 5, a CPU 6 is inset and at the same time, the control of an address bus/data bus in the system is moved from the CPU 6 to the output of the memory 8. After the peripheral equipment is stopped in the safe state by using the input/output terminal, the reset state of the CPU 6 is released.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for detecting runaway of a program in a semiconductor integrated circuit having a CPU to ensure the safety of the entire system.

[0002]

2. Description of the Related Art Conventionally, a counter circuit section 2 for dividing and clocking a system clock 1 as shown in FIG. 2 has been installed as a program runaway detection circuit. This counter is controlled by the value of the control register 4 which is subjected to write / read control by the address selection circuit 3 to execute the clocking operation and clear the counter value. Program runaway detection is performed as follows. That is, at the time of program development, the time required for program execution is calculated for all cases including the generation of interrupt requests, and the program is programmed so that the counter value is cleared at a predetermined cycle. In the system, if a program runaway occurs, the counter value is not cleared in the above cycle, so the counter continues to count time and finally overflows. With this overflow signal, the CPU is reset to ensure safety.

[0003]

However, according to this configuration, there is a problem that the CPU is only reset after the program runaway is detected and the safety of the peripheral device connected to the input / output terminal 14 cannot be always ensured. ..

[0004]

In order to solve the above problems and to realize a semiconductor integrated circuit in which the safety of the entire system can be ensured when a program goes out of control, the present invention provides means for detecting a runaway of a program and its detection signal. It has means for receiving and disconnecting the CPU from the bus, and means for stopping the peripheral device in a predetermined state at the same time when the CPU is disconnected from the bus.

In the semiconductor integrated circuit of the present invention, a counter for counting the system clock, a means for resetting the counter at a constant cycle during normal operation, a CPU and a bus are disconnected when the counter overflows. , And means for stopping the peripheral device in a predetermined state.

Further, in a preferred embodiment of the present invention, the means for stopping the peripheral device in a predetermined state includes a memory means for storing data for stopping the peripheral device in a predetermined state and a counter. And a means for controlling the memory means while connecting the memory means to the bus when an overflow occurs.

[0007]

[Operation] According to the above configuration, when the program goes out of control, the CP
Not only is U reset, but a means for stopping the peripheral devices connected to the input / output terminals in a prescribed state is also provided, so that it is possible to stop the peripheral devices in a safe state, and during program runaway. A semiconductor integrated circuit that ensures the safety of peripheral devices is realized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the functional block diagram of FIG. A watchdog timer 5 which divides the system clock 1 to measure the time, an RS flip-flop 9 set by the overflow of the watchdog timer 5, and a memory control circuit unit 7 and a memory activated by an output 10 of the RS flip-flop 9. Control circuit section 7
It is composed of a memory 8 to which an address and a timing signal are given by, and an address bus buffer 11, a data bus buffer 12 and a bus buffer 13 for transferring control of the address bus and the data bus from the CPU 6 to the memory 8.

When the watchdog timer 5 detects a program runaway, that is, when the counter 2 overflows, the CPU 6 is reset by the CPU reset signal 17.

At the same time, the output 10 of the RS flip-flop 9 which has been reset by the reset terminal 15 when the system is started up is set.

As a result, the tri-state bus buffers in the CPU address and data bus buffers 11 and 12 become high impedance, and the CPU 6 sets the data bus 1
9 and the address bus 20.

On the other hand, the tristate bus buffer of the bus buffer 13 becomes active. At the same time, the memory control circuit section 7 is activated and supplies address and timing signals to the memory 8.

The memory 8 outputs a signal from the input / output terminal 14 by operating the input / output control circuit 18 through the address bus 20 and the data bus 19, and a small amount for stopping the connected peripheral equipment in a safe state. The data of is stored.

The peripheral equipment means an object connected to and controlled by a semiconductor integrated circuit. For example, when the semiconductor integrated circuit is used for controlling a cooking utensil, a heater element or the like is applicable. When used in the body of a personal computer, a hard disk drive connected to the body,
Peripheral devices such as flexible disk drives are applicable.

Further, stopping the peripheral device in a safe state means stopping the heater element in the non-energized state in the above example, and in the case of a hard disk drive or a flexible drive. It means to stop the head when it is sufficiently separated from the disk.

At the end of the above operation, the memory 8 outputs the operation end signal 16 to the RS flip-flop 9 and resets the output 10 of the operation end signal 16. As a result, the address bus 20 and the data bus 19 are again controlled by the CPU 6, the CPU 6 is released from the reset state, and the program execution is restarted.

[0017]

As described above, according to the present invention, when a program runaway occurs, the CPU is reset and at the same time the peripheral devices connected to the input / output terminals are stopped in a safe state. It becomes possible to protect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 System Clock 5 Watchdog Timer 6 CPU 7 Memory Control Circuit Section 8 Memory 9 RS Flip-Flop 10 RS Flip-Flop Output 11 Address Bus Buffer 12 Data Bus Buffer 13 Bus Buffer 14 Input / Output Terminal 16 Operation End Signal 17 CPU Reset Signal 18 I / O control circuit 19 Data bus 20 Address bus

Claims (3)

[Claims] 1. A means for detecting runaway of a program, means for disconnecting a CPU from a bus in response to the detection signal, and means for stopping a peripheral device in a predetermined state at the same time when the CPU is disconnected from the bus. Semiconductor integrated circuit. 2. A counter for counting a system clock, a means for resetting the counter at a constant cycle during normal operation, a CPU and a bus are disconnected when the counter overflows, and peripheral devices are kept in a predetermined state. And a means for stopping. 3. A means for stopping a peripheral device in a predetermined state, a memory means storing data for stopping the peripheral device in a predetermined state, and the memory means connected to a bus when a counter overflows. 3. The semiconductor integrated circuit according to claim 2, further comprising means for controlling the memory means.