JPH05166854A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a semiconductor device which has a small thermal resistance at a joint portion between a semiconductor chip and a ceramic insulator and which can prevent burnout of the semiconductor chip. [Structure] The bonding layer between the ceramic insulator 14 and the semiconductor chip 15 before soldering is structured as follows. A metallization layer 20 is formed on the ceramic insulator 14, and a nickel plating layer 22 and a gold plating layer 24 are formed in this order on the surface thereof. Then, the metal on the back surface of the semiconductor chip 15 is placed on the vanadium layer 2 from the side closer to the semiconductor chip 15.
6, the nickel layer 27, and the gold layer 28 are arranged in this order. The nickel layer 27 has a thickness of 1000 to 2000 angstroms. Gold-germanium-antimony solder 16 is sandwiched between the gold plating 24 and the gold layer 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a high-power semiconductor chip is mounted on a ceramic insulator, and more particularly to the structure of the backside metal of the semiconductor chip.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing the structure of a semiconductor device in which the semiconductor device is mounted on a ceramic insulator. A backside metal 11 is formed on the ceramic wiring board 10.
Then, the ceramic wiring board 10 is placed on the metal heat dissipation plate 12.
Are soldered with tin-nullary solder 13. Then, a ceramic insulator 14 is soldered to the portion of the heat dissipation plate 12 surrounded by the ceramic wiring board 10 with solder 13. Further, a semiconductor chip 15 is soldered on the surface of the ceramic insulator 14 with gold-germanium-antimony solder 16. Then, electrical elements 17, 17, ... Such as transistors, capacitors, and chip resistors, and leads 1
, 18, ... Are soldered onto the surface of the ceramic wiring board 10. These electric elements 17, 17, ... And semiconductor chip
The electrodes (not shown) above 15 are connected by thin metal wires 19, 19, ....

FIG. 1 is a sectional view showing a conventional structure before soldering of a bonding layer between a semiconductor chip 15 and a ceramic insulator 14 in the semiconductor device having the above structure. Metallized layers 20 and 21 are formed on the front and back surfaces of the ceramic insulator 14 by titanium nitride, for example.
Nickel plated layers 22 and 23 are formed on the respective surfaces. Further, gold plating layers 24 and 25 are formed on the surfaces of the nickel plating layers 22 and 23, respectively. Then, the back surface metal of the semiconductor chip 15 is arranged in the order of the vanadium layer 26, the nickel layer 27, and the gold layer 28 from the side closer to the chip 15. The thickness of these backside metal layers is 400 Å for the vanadium layer 26 and 50 for the nickel layer 27, respectively.
0 angstrom, gold layer 28 is 1000 angstrom. A gold-germanium-antimony solder (gold 92.42) is provided between the gold plating 24 and the gold layer 28.
5%, germanium 7.5%, antimony 0.075
%) 16 are sandwiched. The semiconductor chip 15 and the ceramic insulator 14 are mounted at 395 ° C ± 10 ° C by a mounting device.
It is heated in a nitrogen atmosphere and soldered.

A state of the bonding layer after the soldering is shown in a sectional view of FIG. The nickel layer 27 provided on the back surface of the semiconductor chip 15 disappears, and vanadium 26 and nickel plating 22
A eutectic alloy layer 29 made of gold-germanium eutectic and gold-silicon eutectic is formed between and. This gold-silicon eutectic is a semiconductor chip because the nickel layer 27 has disappeared.
The silicon constituting 14 passes through the vanadium layer 26 and is melted with the gold contained in the gold layer 28, the gold plating 24 and the solder 15.

[0005]

When the silicon impregnated from the semiconductor chip 15 reacts with the nickel plating 22 in the bonding layer between the semiconductor chip 15 and the ceramic insulator 14, a brittle layer of nickel silicide is formed. ..
Since this layer contains voids, it has high thermal resistance. Therefore, there is a problem that the semiconductor chip will be burned out if the power supply voltage is applied and the device is operated after completion. The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor device capable of preventing a semiconductor chip from being burnt.

[0006]

A semiconductor device according to the present invention has a metal insulating layer, a nickel layer and a gold layer formed on one surface of a ceramic insulating substrate on which a metal layer, a nickel layer and a gold layer are sequentially formed. A semiconductor device in which sequentially formed semiconductor elements are joined using gold-germanium-antimony solder, and the thickness thereof is set in advance so that the nickel layer on the semiconductor element side remains after the joining. Is characterized by.

[0007]

The silicon of the semiconductor chip is prevented from entering the bonding layer between the semiconductor chip and the silicon insulator.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings by means of an embodiment. The ceramic insulator 14 and the semiconductor chip 15 of the semiconductor device having the structure described with reference to FIG. 3 are joined by soldering. The structure of the semiconductor chip 15 and the ceramic insulator 14 before soldering is shown in the sectional view of FIG. Metallization layers 20 and 21 are formed on the front and back surfaces of the ceramic insulator 14 by titanium nitride, for example, and nickel plating layers 22 and 21 are formed on the surfaces of the metallization layers 20 and 21, respectively.
23 are formed. Furthermore, nickel plating layers 22, 23
Gold plated layers 24 and 25 are formed on the respective surfaces. Then, as the back surface metal of the semiconductor chip 15, the vanadium layer 26, the nickel layer from the side closer to the semiconductor chip 15
27 and the gold layer 28 are arranged in this order. The vanadium layer 26 has a thickness of 400 Å and the gold layer 28 has a thickness of 1000 Å, respectively. Further, the nickel layer 27 is set to 1000 angstroms or more, which is thicker than the conventional 500 angstroms so as to remain after soldering, and 2000 angstroms or less so that the heat dissipation characteristics of the semiconductor device completed after soldering can be secured. Gold-germanium-antimony solder 16 is sandwiched between the gold plating 24 and the gold layer 28. In order to improve the wetting property of the solder, the germanium content of the solder 15 is changed from 7.5% in the past to 11%.
Then, the semiconductor chip 15 and the ceramic insulator 14
Is heated by a mount device in a nitrogen atmosphere at 395 ° C. ± 10 ° C. and soldered.

The state of the bonding layer between the semiconductor chip 15 and the ceramic insulator 14 after the soldering is shown in the sectional view of FIG. Both the nickel layer 27 on the back surface of the semiconductor chip 15 and the nickel plating 22 on the ceramic insulator 14 remain.
Since the nickel layer 27 does not pass through silicon of the semiconductor chip, the layer sandwiched between the nickel layer 27 and the nickel plating 22 is the gold-germanium-antimony solder alloy layer 30. For this reason, since the silicon and nickel have reacted, the brittle layer containing the void of nickel silicide, which has been conventionally formed, is not formed in this bonding layer. Therefore, the thermal resistance of this bonding layer is smaller than that of the conventional one.

[0010]

As described above, according to the present invention,
It is possible to provide a semiconductor device capable of reducing the thermal resistance of the bonding layer between the semiconductor chip and the ceramic insulator and preventing the semiconductor chip from burning.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a semiconductor chip and a ceramic insulator before soldering.

FIG. 2 is a sectional view showing a structure after soldering of a semiconductor chip and a ceramic insulator according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a main portion of a semiconductor device.

FIG. 4 is a cross-sectional view showing a structure of a conventional semiconductor chip and a ceramic insulator after soldering.

[Explanation of symbols]

12 ... Heat sink, 13 ... Tin-null solder, 14 ... Ceramic insulator, 15 ... Semiconductor chip, 16 ... Gold-germanium-antimony solder, 20, 21 ... Metallization layer, 22, 23 ... Nickel plating layer, 24, 25 … Gold plated layer, 26… Vanadium layer, 27
... nickel layer, 28 ... gold layer, 29 ... eutectic alloy layer, 30 ... gold-germanium-antimony solder alloy layer.

Claims (2)

[Claims] 1. A semiconductor device in which a metal layer, a nickel layer, and a gold layer are sequentially formed on one surface on a ceramic insulating substrate having a metal layer, a nickel layer, and a gold layer sequentially formed on the surface, A semiconductor device joined by using germanium-antimony solder, wherein the thickness is set in advance so that the nickel layer on the semiconductor element side remains after the joining. 2. The semiconductor device according to claim 1, wherein the thickness of the nickel layer on the semiconductor element side is set within the range of 1000 angstroms to 2000 angstroms before bonding.