JPH05175121A - Manufacture of soi substrate and semiconductor device - Google Patents
Manufacture of soi substrate and semiconductor deviceInfo
- Publication number
- JPH05175121A JPH05175121A JP34498691A JP34498691A JPH05175121A JP H05175121 A JPH05175121 A JP H05175121A JP 34498691 A JP34498691 A JP 34498691A JP 34498691 A JP34498691 A JP 34498691A JP H05175121 A JPH05175121 A JP H05175121A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layer
- insulating film
- opening
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000013078 crystal Substances 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010574 gas phase reaction Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 1
- 229910018540 Si C Inorganic materials 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229960001730 nitrous oxide Drugs 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁基板上に半導体結晶
層を形成した、いわゆるＳＯＩ基板の製法に関する。さ
らに詳しくは、半導体基板上に形成した絶縁膜上に、該
半導体基板の半導体結晶をシードとしてエピタキシャル
成長により半導体結晶層を形成するＳＯＩ基板の製法お
よびその基板を使用した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a so-called SOI substrate in which a semiconductor crystal layer is formed on an insulating substrate. More specifically, the present invention relates to a method for manufacturing an SOI substrate in which a semiconductor crystal layer of the semiconductor substrate is formed by epitaxial growth on an insulating film formed on the semiconductor substrate as a seed, and a semiconductor device using the substrate.
【０００２】なお、本明細書においては、ＳＯＩを絶縁
膜上の半導体結晶層の意味で使用し、絶縁膜上のシリコ
ン半導体に限定されず、広く半導体を含む意味で使用す
る。In this specification, SOI is used to mean a semiconductor crystal layer on an insulating film, and is not limited to a silicon semiconductor on an insulating film, but is used broadly to include a semiconductor.
【０００３】[0003]
【従来の技術】絶縁基板上に半導体結晶層を形成したＳ
ＯＩ基板の製法の一つに、半導体基板上に形成した絶縁
膜に開口部を形成し、露出した半導体基板の半導体結晶
をシードとして絶縁膜上に半導体結晶層をエピタキシャ
ル成長させる方法がある。2. Description of the Related Art S having a semiconductor crystal layer formed on an insulating substrate
One of the methods of manufacturing an OI substrate is a method of forming an opening in an insulating film formed on a semiconductor substrate and epitaxially growing a semiconductor crystal layer on the insulating film using the exposed semiconductor crystal of the semiconductor substrate as a seed.
【０００４】従来のこの方法によりエピタキシャル成長
したＳＯＩ基板の断面図を図７に示す。このＳＯＩ基板
の製法は半導体基板21上に絶縁膜22を形成し、前記絶縁
膜22の一部を除去して開口部23を形成する。つぎに開口
部23により露出した半導体結晶をシードとして、前記半
導体結晶と同種あるいは異種のエピタキシャル層を成長
させると、まず開口部23内に半導体結晶層24が形成され
る。さらにエピタキシャル成長を続けると、絶縁膜22上
を横方向にエピタキシャル成長し、絶縁膜２の上に半導
体結晶層24が成長する。FIG. 7 shows a sectional view of an SOI substrate epitaxially grown by this conventional method. In this method of manufacturing an SOI substrate, an insulating film 22 is formed on a semiconductor substrate 21, a part of the insulating film 22 is removed, and an opening 23 is formed. Next, using the semiconductor crystal exposed through the opening 23 as a seed, an epitaxial layer of the same kind or different kind as the semiconductor crystal is grown, and first, the semiconductor crystal layer 24 is formed in the opening 23. When the epitaxial growth is further continued, lateral epitaxial growth is performed on the insulating film 22, and the semiconductor crystal layer 24 is grown on the insulating film 2.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来の横方向
エピタキシャル成長法によりＳＯＩ基板をうる方法は、
絶縁膜上に半導体結晶層をエピタキシャル成長させると
き、絶縁膜上を横方向にエピタキシャル成長するだけで
なく縦方向にも成長が進むため、図７に示すように開口
部の形成された部分が厚く形成され、結晶層の厚さが不
均一になるという問題がある。そのため、均一な厚さで
大面積の半導体結晶層をうることができない。However, the conventional method for obtaining the SOI substrate by the lateral epitaxial growth method is as follows.
When the semiconductor crystal layer is epitaxially grown on the insulating film, not only the epitaxial growth in the lateral direction but also the growth in the vertical direction on the insulating film occurs. Therefore, as shown in FIG. 7, the portion where the opening is formed is thickly formed. However, there is a problem that the thickness of the crystal layer becomes uneven. Therefore, a semiconductor crystal layer having a uniform thickness and a large area cannot be obtained.
【０００６】本発明はこのような状況に鑑み、表面が平
担な半導体結晶層を有するＳＯＩ基板を形成する方法を
提供することを目的とする。In view of such a situation, an object of the present invention is to provide a method for forming an SOI substrate having a semiconductor crystal layer whose surface is flat.
【０００７】[0007]
【課題を解決するための手段】本発明によるＳＯＩ基板
の製法は、半導体基板上に第１の絶縁膜を形成し、第１
の開口部を形成する工程と、第１の開口部および第１の
絶縁膜上にダミー層を形成し、第２の開口部を形成する
工程と、第２の開口部およびダミー層上に第２の絶縁膜
を形成し、第３の開口部を形成する工程と、第３の開口
部から前記ダミー層をエッチング除去し空洞を形成する
工程と、前記空洞内に前記半導体基板をシードとして半
導体結晶層をエピタキシャル成長させる工程と、前記半
導体結晶層上の第２の絶縁膜を除去する工程とからなる
ことを特徴とする。According to the method of manufacturing an SOI substrate of the present invention, a first insulating film is formed on a semiconductor substrate, and a first insulating film is formed.
Forming an opening of the first opening and the first insulating film, forming a dummy layer on the first insulating film and forming a second opening, and forming a second opening on the second opening and the dummy layer. Second insulating film to form a third opening, a step of etching away the dummy layer from the third opening to form a cavity, and a semiconductor using the semiconductor substrate as a seed in the cavity. It is characterized by comprising a step of epitaxially growing the crystal layer and a step of removing the second insulating film on the semiconductor crystal layer.
【０００８】[0008]
【作用】本発明によれば、絶縁膜上の半導体結晶層を形
成する場所にあらかじめ絶縁膜で空洞を形成しておき、
その空洞内に半導体結晶層をエピタキシャル成長させる
ため、エピタキシャル成長層の縦方向成長である上面は
絶縁膜で規制され、平担に形成される。According to the present invention, a cavity is formed in advance in the insulating film at the place where the semiconductor crystal layer is formed,
Since the semiconductor crystal layer is epitaxially grown in the cavity, the upper surface of the epitaxial growth layer, which is vertically grown, is regulated by the insulating film and formed flat.
【０００９】また空洞を形成するためのダミー層はＣＶ
Ｄ法やスパッタリングなどで形成でき膜厚を制御し易
く、膜厚を充分制御された空洞部にエピタキシャル成長
するため、エピタキシャル成長層の厚さも非常に正確に
形成できる。The dummy layer for forming the cavity is CV.
The thickness of the epitaxial growth layer can be formed very accurately because it can be formed by the D method or sputtering and the film thickness can be easily controlled and the film is epitaxially grown in the cavity where the film thickness is sufficiently controlled.
【００１０】[0010]
【実施例】つぎに、図面を参照しながら本発明について
詳細に説明する。図１〜６は本発明の一実施例であるＳ
ＯＩ基板の製法を示す工程説明図である。The present invention will be described in detail with reference to the drawings. 1 to 6 show S which is an embodiment of the present invention.
It is process explanatory drawing which shows the manufacturing method of an OI board | substrate.
【００１１】まず図１の工程に示すように、半導体基板
上に形成した第１の絶縁膜の一部を除去して第１の開口
部３を形成する。具体例としては、(100) 面のシリコン
基板１を基板温度約1000℃で熱酸化し、100nm の第１の
絶縁膜である第１のシリコン酸化膜２を形成した。つぎ
に第１のシリコン酸化膜２の一部を通常のホトレジスト
工程により除去して第１の開口部３を形成し、シリコン
基板１の一部を露出させた。First, as shown in the step of FIG. 1, a part of the first insulating film formed on the semiconductor substrate is removed to form a first opening 3. As a specific example, a (100) plane silicon substrate 1 was thermally oxidized at a substrate temperature of about 1000 ° C. to form a 100 nm first silicon oxide film 2 as a first insulating film. Next, a part of the first silicon oxide film 2 was removed by a normal photoresist process to form a first opening 3, and a part of the silicon substrate 1 was exposed.
【００１２】つぎに図２の工程に示すように、第１の絶
縁膜の表面全面にダミー層を形成したのち、ダミー層の
シード部（第１の開口部）周辺の一部を除去して第２の
開口部５を形成する。具体例としては、前工程により第
１の開口部３を形成したシリコン基板１を反応炉に入
れ、基板温度を400 ℃にしてシラン（ＳｉＨ4 ）ガスを
導入し60分間プラズマＣＶＤを行い、アモルファスシリ
コン４をシリコン基板１の表面全面に200nm 堆積させ
た。つぎにアモルファスシリコン４の表面をエッチバッ
クにより平担にして、第１の開口部に隣接する前記アモ
ルファスシリコン層４の一部をホトレジスト工程で反応
性イオンエッチング（以下、ＲＩＥという）法によりフ
ッ化炭素（ＣＦ4 ）ガスおよび塩素（Ｃｌ2 ）ガスを使
用して選択エッチングし、第２の開口部５を形成し、第
１のシリコン酸化膜２を露出させた。Next, as shown in the step of FIG. 2, after forming a dummy layer on the entire surface of the first insulating film, a part of the dummy layer around the seed portion (first opening) is removed. The second opening 5 is formed. As a specific example, the silicon substrate 1 having the first opening 3 formed in the previous step is placed in a reaction furnace, the substrate temperature is set to 400 ° C., silane (SiH 4 ) gas is introduced, and plasma CVD is performed for 60 minutes to obtain an amorphous material. 200 nm of silicon 4 was deposited on the entire surface of the silicon substrate 1. Next, the surface of the amorphous silicon 4 is flattened by etching back, and a part of the amorphous silicon layer 4 adjacent to the first opening is fluorinated by a reactive ion etching (hereinafter referred to as RIE) method in a photoresist process. Selective etching was performed using carbon (CF 4 ) gas and chlorine (Cl 2 ) gas to form the second opening 5, and the first silicon oxide film 2 was exposed.
【００１３】つぎに図３の工程に示すように、ダミー層
の表面全面に第２の絶縁膜を形成したのち、第２の開口
部周辺の第２の絶縁膜の一部を除去して第３の開口部７
を形成する。具体例としては、シラン（ＳｉＨ4 ）ガス
と酸化二チッ素（Ｎ2 Ｏ）ガスを導入して800 ℃で気相
反応させ、第２の絶縁膜である第２のシリコン酸化膜６
を400nm 堆積させた。このとき第２のシリコン酸化膜６
は、前記第２の開口部５内部にも形成されるので第１の
シリコン酸化膜２と第２のシリコン酸化膜６は連結され
る。そののち、第２の開口部部分に隣接し、アモルファ
スシリコン層４の端部部分にあたる第２のシリコン酸化
膜６の一部を腐蝕除去し第３の開口部７を形成して前記
アモルファスシリコン層４の一部を露出させた。この第
３の開口部７はシード部とする第１の開口部部分から２
μｍの場所に形成した。Next, as shown in the step of FIG. 3, after forming a second insulating film on the entire surface of the dummy layer, a part of the second insulating film around the second opening is removed to form a second insulating film. 3 openings 7
To form. As a specific example, a silane (SiH 4 ) gas and a dinitrogen oxide (N 2 O) gas are introduced to cause a gas phase reaction at 800 ° C., and a second silicon oxide film 6 serving as a second insulating film is formed.
Was deposited to 400 nm. At this time, the second silicon oxide film 6
Is also formed inside the second opening 5, so that the first silicon oxide film 2 and the second silicon oxide film 6 are connected to each other. After that, a part of the second silicon oxide film 6 which is adjacent to the second opening portion and which is the end portion of the amorphous silicon layer 4 is corroded and removed to form a third opening portion 7 to form the amorphous silicon layer. Part 4 was exposed. This third opening portion 7 is formed from the first opening portion 2 to be the seed portion.
It was formed at a position of μm.
【００１４】つぎに図４に示すように、第３の開口部７
からダミー層４を腐蝕除去して、後述する半導体結晶層
をエピタキシャル成長するための空洞８を形成する。具
体例としては、反応炉内に常温で塩化水素ガスを導入す
ると、第３の開口部７から順次アモルファスシリコン層
４のみがエッチング除去され、空洞８が形成された。こ
の空洞８のシリコン半導体基板１側は前述の第１の開口
部３と一致し、シリコン半導体基板が露出した。Next, as shown in FIG. 4, the third opening 7
Then, the dummy layer 4 is corroded and removed to form a cavity 8 for epitaxially growing a semiconductor crystal layer described later. As a specific example, when hydrogen chloride gas was introduced into the reaction furnace at room temperature, only the amorphous silicon layer 4 was sequentially removed by etching from the third opening 7 to form a cavity 8. The silicon semiconductor substrate 1 side of this cavity 8 coincided with the above-mentioned first opening 3, and the silicon semiconductor substrate was exposed.
【００１５】つづいて図５に示すように、空洞８により
露出した半導体基板をシードとして、空洞の内部でエピ
タキシャル成長を行って、半導体結晶層を形成する。具
体例としては、エピタキシャル成長ガスとして、ジシラ
ン（Ｓｉ2 Ｈ6 ）を0.15sccmおよびアセチレン（Ｃ2 Ｈ
2 ）を0.15sccm並びにキャリアガスとして水素（Ｈ2 ）
ガスを３slm 、エッチング剤として塩化水素（ＨＣｌ）
ガスを10sccm混合したガスを用いて、基板温度1350℃、
10分間の条件で基板表面で反応させた。このとき、気相
成長ガスは第３の開口部７から空洞８内部に入り、空洞
８のシリコン半導体基板１の露出面をシードとしてエピ
タキシャル成長が行われ、空洞８内に炭化ケイ素（Ｓｉ
Ｃ）結晶層９が形成された。この際空洞８上部の第２の
シリコン酸化膜６が縦方向のエピタキシャル成長を規制
するため、炭化ケイ素結晶層９の上部は平担化される。
ここで、気相成長ガスの流量比を調整しておくことによ
りエピタキシャル成長を行う際、第２のシリコン酸化膜
６の表面には成長せず、シリコン基板からのみ成長す
る。すなわち、エピタキシャル成長時には第２のシリコ
ン酸化膜６の表面にも堆積しようとするが、密着性が良
くないため、混合ガスの中の塩化水素ガスによりエッチ
ングされ堆積されず、シリコン基板から成長する部分は
密着性がよくエッチングされないで成長が進む。したが
って塩化水素の流量比をこの目的に合うように定める。Subsequently, as shown in FIG. 5, the semiconductor substrate exposed by the cavity 8 is used as a seed to perform epitaxial growth inside the cavity to form a semiconductor crystal layer. As a specific example, disilane (Si 2 H 6 ) of 0.15 sccm and acetylene (C 2 H) are used as an epitaxial growth gas.
2 ) 0.15 sccm and hydrogen (H 2 ) as carrier gas
3 slm gas, hydrogen chloride (HCl) as etching agent
Using a gas mixture of 10 sccm gas, the substrate temperature 1350 ℃,
The reaction was carried out on the substrate surface under the condition of 10 minutes. At this time, the vapor phase growth gas enters the inside of the cavity 8 through the third opening 7, and epitaxial growth is performed using the exposed surface of the silicon semiconductor substrate 1 of the cavity 8 as a seed, and the silicon carbide (Si
C) Crystal layer 9 was formed. At this time, since the second silicon oxide film 6 on the upper part of the cavity 8 regulates the epitaxial growth in the vertical direction, the upper part of the silicon carbide crystal layer 9 is flattened.
Here, when epitaxial growth is performed by adjusting the flow rate ratio of the vapor growth gas, it does not grow on the surface of the second silicon oxide film 6, but only from the silicon substrate. That is, during epitaxial growth, an attempt is made to deposit on the surface of the second silicon oxide film 6, but since the adhesion is poor, the portion that grows from the silicon substrate will not be etched and deposited by the hydrogen chloride gas in the mixed gas. Adhesion is good and growth proceeds without being etched. Therefore, the flow ratio of hydrogen chloride is determined to meet this purpose.
【００１６】最後に図６に示すように第２の絶縁膜を除
去して半導体結晶層を露出させる。具体例としては、フ
ッ酸によりエッチングを行って第２のシリコン酸化膜６
を除去した。Finally, as shown in FIG. 6, the second insulating film is removed to expose the semiconductor crystal layer. As a specific example, the second silicon oxide film 6 is formed by etching with hydrofluoric acid.
Was removed.
【００１７】以上により、絶縁膜上に平担な半導体結晶
層がえられ、ＳＯＩ基板の形成が完了する。なお、半導
体結晶層の厚さはアモルファス半導体層の厚さにより定
まり、アモルファス半導体層の厚さは比較的コントロー
ルし易いため、半導体結晶層の膜厚も比較的容易に制御
できる。As described above, a flat semiconductor crystal layer is obtained on the insulating film, and the formation of the SOI substrate is completed. Since the thickness of the semiconductor crystal layer is determined by the thickness of the amorphous semiconductor layer and the thickness of the amorphous semiconductor layer is relatively easy to control, the thickness of the semiconductor crystal layer can also be relatively easily controlled.
【００１８】以上の実施例では空洞を形成するのにダミ
ー層としてアモルファスシリコンを堆積して絶縁膜形成
後にアモルファスシリコンを腐蝕除去する例で説明した
が、この方法はアモルファスシリコンに限定されない。In the above-described embodiments, an example is described in which amorphous silicon is deposited as a dummy layer to form a cavity and the amorphous silicon is corroded and removed after forming an insulating film, but this method is not limited to amorphous silicon.
【００１９】すなわち、堆積が容易で、のちに絶縁膜や
半導体基板を腐蝕しないで、この層だけを腐蝕除去でき
るものであればよく、絶縁膜に二酸化ケイ素を用いたば
あい、アモルファスシリコン層の代りにアモルファス炭
化ケイ素層など他のアモルファス半導体層、チッ化ケイ
素膜、アルミニウム膜などを使用することもできる。な
お、アルミニウム膜のばあいには、膜形成時に段差が残
ったり、アルミニウム膜上の絶縁膜は低温で形成できる
ものでなければならないし、シード部分に傷をつけない
ようにしなければならないなどの問題があるが、これら
を克服すれば充分に使用できる。That is, any material can be used as long as it is easy to deposit and can corrode and remove only this layer without corroding the insulating film and the semiconductor substrate later. When silicon dioxide is used for the insulating film, the amorphous silicon layer Alternatively, another amorphous semiconductor layer such as an amorphous silicon carbide layer, a silicon nitride film, an aluminum film, or the like can be used. In the case of an aluminum film, a step remains during film formation, the insulating film on the aluminum film must be one that can be formed at a low temperature, and the seed portion must be protected from scratches. There are problems, but if these are overcome, it can be used sufficiently.
【００２０】チッ化ケイ素膜で行うばあい、形成するに
はシラン（ＳｉＨ4 ）ガスとアンモニア（ＮＨ3 ）ガス
を導入して350 ℃で気相反応することにより平担な層が
形成でき、また腐蝕除去するには熱リン酸を使用するこ
とにより他の絶縁膜などを腐蝕しないでチッ化膜のみを
腐蝕除去できる。In the case of using a silicon nitride film, a flat layer can be formed by introducing silane (SiH 4 ) gas and ammonia (NH 3 ) gas and performing a gas phase reaction at 350 ° C. In addition, by using hot phosphoric acid for corrosion removal, only the nitride film can be removed by corrosion without corroding other insulating films.
【００２１】また絶縁膜としてチッ化膜を使用すれば、
酸化ケイ素膜を空洞形成用材料として使用することもで
きる。If a nitride film is used as the insulating film,
A silicon oxide film can also be used as a cavity forming material.
【００２２】さらに前記具体的実施例では半導体結晶層
として炭化ケイ素の例で説明したが、シリコンなど他の
半導体結晶層でも同様に形成できる。Further, in the above-mentioned specific embodiments, the semiconductor crystal layer is described as an example of silicon carbide, but other semiconductor crystal layers such as silicon can be formed in the same manner.
【００２３】前述の方法により形成されたＳＯＩ基板
は、部分的に半導体基板と連結されているが、半導体結
晶層が絶縁膜で仕切られ、島状の半導体領域が形成され
ており、各半導体領域に通常のプロセスで半導体回路を
形成することにより、集積回路を組み込んだ半導体装置
をえられる。このばあい、各半導体領域は完全な独立し
た島領域にはなっていないが、半導体基板と半導体結晶
層の導電型を変えることにより各半導体領域を電気的に
分離でき、しかも半導体基板と連結されている部分の面
積は少ないため、寄生容量などは最小限に抑えられ、素
子間分離が充分になされ、高速動作などにもすぐれてい
る。The SOI substrate formed by the above method is partially connected to the semiconductor substrate, but the semiconductor crystal layer is partitioned by an insulating film to form island-shaped semiconductor regions, and each semiconductor region is formed. By forming a semiconductor circuit by a normal process, a semiconductor device incorporating an integrated circuit can be obtained. In this case, each semiconductor region is not a completely independent island region, but each semiconductor region can be electrically separated by changing the conductivity type of the semiconductor substrate and the semiconductor crystal layer, and is connected to the semiconductor substrate. Since the area of the part in which the element is formed is small, parasitic capacitance and the like can be minimized, element isolation is sufficiently performed, and high speed operation is also excellent.
【００２４】さらに、このようにして製造された半導体
装置表面のパシベーション膜を平担にして前述と同様の
方法により半導体結晶層を成長させることにより２階部
分に半導体回路を形成することができる。この方法をさ
らに繰り返すことにより複数段形成でき、３次元構造の
半導体装置をうることができ、一層素子の高集積化を図
ることができる。Further, a semiconductor circuit can be formed on the second floor by growing the semiconductor crystal layer in the same manner as described above with the passivation film on the surface of the semiconductor device manufactured as described above being flat. By repeating this method further, a plurality of stages can be formed, a semiconductor device having a three-dimensional structure can be obtained, and higher integration of elements can be achieved.
【００２５】[0025]
【発明の効果】以上説明したように、本発明によれば、
半導体基板の絶縁膜上に第２の絶縁膜により空洞を形成
して、その空洞内に半導体結晶層をエピタキシャル成長
するため、縦方向のエピタキシャル成長は空洞の上壁で
規制され、横方向にエピタキシャル成長されて上面が平
担な半導体結晶層を絶縁膜上に形成でき、精度の高い回
路形成をできる。As described above, according to the present invention,
Since the cavity is formed by the second insulation film on the insulation film of the semiconductor substrate and the semiconductor crystal layer is epitaxially grown in the cavity, the epitaxial growth in the vertical direction is restricted by the upper wall of the cavity and the epitaxial growth is performed in the lateral direction. A semiconductor crystal layer having a flat upper surface can be formed on the insulating film, and a highly accurate circuit can be formed.
【００２６】さらに本発明によれば、空洞を形成するの
にアモルファス半導体層やチッ化シリコン膜などを形成
して型どりしているため、これらの膜厚制御が比較的容
易で、絶縁膜上に正確な厚さの半導体結晶層を形成でき
るという効果がある。Further, according to the present invention, since the amorphous semiconductor layer, the silicon nitride film, etc. are formed and shaped to form the cavity, it is relatively easy to control the film thickness of these and the insulating film is formed on the insulating film. There is an effect that a semiconductor crystal layer having an accurate thickness can be formed.
【００２７】その結果、このＳＯＩ基板を使用して半導
体結晶層に半導体回路を形成することにより、絶縁膜で
素子間分離された絶縁特性の良い半導体装置をえられる
という効果がある。As a result, by using this SOI substrate to form a semiconductor circuit in a semiconductor crystal layer, there is an effect that a semiconductor device having good insulation characteristics can be obtained which is isolated from each other by an insulating film.
【図１】本発明の一実施例であるＳＯＩ基板の製法の製
造工程を示す説明図である。FIG. 1 is an explanatory diagram showing a manufacturing process of an SOI substrate manufacturing method according to an embodiment of the present invention.
【図２】本発明の一実施例であるＳＯＩ基板の製法の製
造工程を示す説明図である。FIG. 2 is an explanatory diagram showing a manufacturing process of an SOI substrate manufacturing method according to an embodiment of the present invention.
【図３】本発明の一実施例であるＳＯＩ基板の製法の製
造工程を示す説明図である。FIG. 3 is an explanatory diagram showing a manufacturing process of a method for manufacturing an SOI substrate which is an embodiment of the present invention.
【図４】本発明の一実施例であるＳＯＩ基板の製法の製
造工程を示す説明図である。FIG. 4 is an explanatory diagram showing a manufacturing process of a method for manufacturing an SOI substrate which is an embodiment of the present invention.
【図５】本発明の一実施例であるＳＯＩ基板の製法の製
造工程を示す説明図である。FIG. 5 is an explanatory diagram showing a manufacturing process of a method for manufacturing an SOI substrate which is an embodiment of the present invention.
【図６】本発明の一実施例であるＳＯＩ基板の製法の製
造工程を示す説明図である。FIG. 6 is an explanatory diagram showing a manufacturing process of a method for manufacturing an SOI substrate which is an embodiment of the present invention.
【図７】従来のエピタキシャル成長法により製造したＳ
ＯＩ基板の断面説明図である。FIG. 7: S manufactured by a conventional epitaxial growth method
It is a section explanatory view of an OI substrate.
１ 半導体基板 ２ 第１のシリコン酸化膜 ３ 第１の開口部 ４ アモルファスシリコン層 ５ 第２の開口部 ６ 第２のシリコン酸化膜 ７ 第３の開口部 ８ 空洞 ９ 半導体結晶層 1 Semiconductor Substrate 2 First Silicon Oxide Film 3 First Opening 4 Amorphous Silicon Layer 5 Second Opening 6 Second Silicon Oxide Film 7 Third Opening 8 Cavity 9 Semiconductor Crystal Layer
Claims (4)
第１の開口部を形成する工程、 第１の開口部および第１の絶縁膜上にダミー層を形成
し、第２の開口部を形成する工程、 第２の開口部およびダミー層上に第２の絶縁膜を形成
し、第３の開口部を形成する工程、 第３の開口部から前記ダミー層をエッチング除去し空洞
を形成する工程、 前記空洞内に前記半導体基板をシードとして半導体結晶
層をエピタキシャル成長する工程および前記半導体結晶
層上の第２の絶縁膜を除去する工程からなるＳＯＩ基板
の製法。1. A first insulating film is formed on a semiconductor substrate,
Forming a first opening, forming a dummy layer on the first opening and the first insulating film and forming a second opening, forming a second opening on the second opening and the dummy layer A step of forming a second insulating film and forming a third opening, a step of etching away the dummy layer from the third opening to form a cavity, and a semiconductor crystal layer using the semiconductor substrate as a seed in the cavity. A method for manufacturing an SOI substrate, which comprises a step of epitaxially growing a substrate and a step of removing the second insulating film on the semiconductor crystal layer.
層、チッ化ケイ素膜、酸化ケイ素膜およびアルミニウム
膜よりなる群から選ばれたいずれか１種で形成されてな
る請求項１記載のＳＯＩ基板の製法。2. The method for manufacturing an SOI substrate according to claim 1, wherein the dummy layer is formed of any one selected from the group consisting of an amorphous semiconductor layer, a silicon nitride film, a silicon oxide film and an aluminum film. ..
は炭化ケイ素結晶層であることを特徴とする請求項１記
載のＳＯＩ基板の製法。3. The method for manufacturing an SOI substrate according to claim 1, wherein the semiconductor crystal layer is a silicon crystal layer or a silicon carbide crystal layer.
Ｉ基板の半導体結晶層に半導体回路が形成されてなる半
導体装置。4. SO obtained by the method according to claim 1.
A semiconductor device having a semiconductor circuit formed on a semiconductor crystal layer of an I substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34498691A JP3206943B2 (en) | 1991-12-26 | 1991-12-26 | Method of manufacturing SOI substrate and semiconductor device |
| US08/226,841 US5525536A (en) | 1991-12-26 | 1994-04-13 | Method for producing SOI substrate and semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34498691A JP3206943B2 (en) | 1991-12-26 | 1991-12-26 | Method of manufacturing SOI substrate and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05175121A true JPH05175121A (en) | 1993-07-13 |
| JP3206943B2 JP3206943B2 (en) | 2001-09-10 |
Family
ID=18373505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34498691A Expired - Lifetime JP3206943B2 (en) | 1991-12-26 | 1991-12-26 | Method of manufacturing SOI substrate and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3206943B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663588A (en) * | 1994-07-12 | 1997-09-02 | Nippondenso Co., Ltd. | Semiconductor device having an SOI structure of mesa isolation type and manufacturing method therefor |
| CN103280425A (en) * | 2013-05-27 | 2013-09-04 | 中国科学院物理研究所 | Composite substrate with isolating layer and manufacturing method of composite substrate |
| WO2014126055A1 (en) * | 2013-02-15 | 2014-08-21 | 国立大学法人東京大学 | Semiconductor integrated circuit board and method for manufacturing same |
| JP2025519797A (en) * | 2022-06-21 | 2025-06-26 | ヒタチ・エナジー・リミテッド | Method for manufacturing a power semiconductor device and a power semiconductor device |
-
1991
- 1991-12-26 JP JP34498691A patent/JP3206943B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5663588A (en) * | 1994-07-12 | 1997-09-02 | Nippondenso Co., Ltd. | Semiconductor device having an SOI structure of mesa isolation type and manufacturing method therefor |
| WO2014126055A1 (en) * | 2013-02-15 | 2014-08-21 | 国立大学法人東京大学 | Semiconductor integrated circuit board and method for manufacturing same |
| CN103280425A (en) * | 2013-05-27 | 2013-09-04 | 中国科学院物理研究所 | Composite substrate with isolating layer and manufacturing method of composite substrate |
| JP2025519797A (en) * | 2022-06-21 | 2025-06-26 | ヒタチ・エナジー・リミテッド | Method for manufacturing a power semiconductor device and a power semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3206943B2 (en) | 2001-09-10 |
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