JPH05181561A - Clock signal switching system - Google Patents

Abstract

PURPOSE:To eliminate hindrance to the supply of a clock signal regardless of which signal generator gets out of order by making a selecting circuit stop selecting the clock signal of a clock signal generator corresponding to a switching signal received from a break detecting circuit when this signal is received and select and output a signal other than the clock signal. CONSTITUTION:Clock generating circuits 1-3 normally select and output the clock signals of their clock generators 1A-3A, but if, for example, the clock signal generator 3A gets out of order, the break detecting circuit 4D detects information on the break of a signal f3 and the clock signal of the clock signal generator 3A is switched to the clock signal (g) of the selecting circuit 4C with the switching signal e3. At this time, when the clock signal (g) is the selection result of a signal f1 or f2, the selecting circuit 4C performs no switching, but when the clock signal (g) is f3, the clock signal is switched to the signal f1 or f2 under the control of the break detecting circuit 4D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal switching system, and more particularly to a clock switching system having a plurality of clock signal generating circuits.

[0002]

2. Description of the Related Art In a conventional clock switching system, as shown in FIG. 2, selector circuits are provided for clock signals 1f1, 1f2, 1f3 generated by clock signal generators 11A, 12A, 13A of clock signal generator circuits 11-13. Enter in 14,
Clock signals 1f1, 1f2, 1f are generated by the selector 14B.
Select one of 3 and branch to the outside (1h1, 1h
2, 1h3) It is outputting. Here, the selector 14B is controlled by the switching signals 1e1, 1e2, 1e3 of the clock signal disconnection detection circuits 11c, 12c, 13c, and 1f1 ,.
When the clock signal selected from 1f2 and 1f3 is disconnected, the other clock signal is switched to be selected.

[0003]

In this conventional clock switching system, when the selected clock signal is cut off, the selection circuit selects another clock signal. Therefore, for all the output clock signals. There was a problem that switching would occur.

An object of the present invention is to provide a clock signal switching system which does not hinder the supply of the clock signal even if one of the clock signal generators fails.

[0005]

According to the present invention, there are provided a plurality of clock signal generating circuits and a clock signal selecting means for selecting the outputs of these clock signal generating circuits,
The clock signal generation circuit, a clock signal generator,
And a switching circuit connected to the switching circuit, wherein the clock signal selection means is connected to the clock signal generator and the switching circuit and selects one of the clock signals from the clock signal generator to select the switching circuit. A select circuit to be provided, the clock signal generator, the switching circuit, and the select circuit are connected to the select circuit to detect that the clock signal from the clock signal generator is no longer generated, and to provide the switch signal to the select circuit and the switch circuit. A disconnection detection circuit, and when the selection circuit receives a switching signal from the disconnection detection circuit, the selection circuit stops the selection of the clock signal of the clock signal generator corresponding to the switching signal, and a clock signal other than the clock signal. When the switching circuit receives the switching signal from the disconnection detection circuit, the switching circuit outputs the clock signal sent from the selection circuit. Clock signal switching method, wherein the door is obtained.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of the present invention will be described in detail with reference to FIG.

As shown in FIG. 1, according to the clock signal switching system of the present invention, a plurality of clock signal generating circuits 1, 2, 3 are provided.
And a clock signal selecting means 4 for selecting the outputs of these clock signal generating circuits 1, 2 and 3. The clock signal generation circuits 1, 2 and 3 include clock signal generators 1A, 2A and 3A and a switching circuit 1 connected thereto.
B, 2B, 3B. The clock signal selection means 4 is connected to the clock signal generators 1A, 2A, 3A and the switching circuits 1B, 2B, 3B and selects one of the clock signal generators 1A, 2A, 3A. As the clock signal g, the switching circuits 1B and 2
B, 3B, a selection circuit 4C, the clock signal generators 1A, 2A, 3A, the switching circuits 1B, 2B, 3B, and the selection circuit 4C, which are connected to the clock signal generator 1A,
It is detected that the clock signals from 2A and 3A are no longer generated, and the switching signals e1, e2 and e3 are set to the selection circuit 4 described above.
C and disconnection detection circuit 4D for switching circuits 1B, 2B and 3B
And have. When the selection circuit 4C receives a disconnection signal from the disconnection detection circuit 4D, the selection circuit 4C stops the selection of the clock signals of the clock signal generators 1A, 2A, 3A corresponding to this disconnection signal and selects a clock signal other than the clock signal. select. The switching circuits 1B, 2B, 3B output the clock signal sent from the selection circuit 4C when receiving the disconnection signal from the disconnection detection circuit 4D. The switching circuits 1B, 2B and 3B send the selected clock signals to the outside as output signals h1, h2 and h3, respectively.

Normally, the clock generation circuits 1, 2 and 3 select and output the clock signals of their own clock signal generators 1A, 2A and 3A. For example, when the clock signal generator 3A fails. , F3 is disconnected, the disconnection detection circuit 4D detects the information, and the switching signal e3 switches the clock signal of the clock signal generator 3A to the clock signal g. At this time, if the clock signal g is the selection result of f1 or f2, switching does not occur in the selection circuit 4C, but if the clock signal g is f3, it is switched to f1 or f2 by the control of the disconnection detection circuit 4D.

[0009]

As described above, according to the clock signal switching system of the present invention, even if any of the clock generators fails,
It does not hinder the supply of the clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional clock signal switching system.

[Explanation of symbols]

 1-3 Clock signal generation circuit 1A-3A Clock signal generator 1B-3B Switching circuit 4 Selection means 4C selection circuit 4D Disconnection detection circuit

Claims (1)

[Claims] 1. A plurality of clock signal generating circuits and clock signal selecting means for selecting outputs of these clock signal generating circuits, wherein the clock signal generating circuit is connected to the clock signal generator. And a switching circuit, wherein the clock signal selection means is connected to the clock signal generator and the switching circuit, selects one of the clock signals of the clock signal generator, and supplies it to the switching circuit. A disconnection detection circuit which is connected to the clock signal generator, the switching circuit and the selection circuit and which detects that the clock signal from the clock signal generator is no longer generated and gives a switching signal to the selection circuit and the switching circuit. Have
When the selection circuit receives the switching signal from the disconnection detection circuit, it stops selecting the clock signal of the clock signal generator corresponding to the switching signal and selects a clock signal other than the clock signal, and the switching circuit is A clock signal switching system, wherein a clock signal sent from the selection circuit is output when a switching signal is received from the disconnection detection circuit.