JPH051821Y2 - - Google Patents

Description

[Detailed explanation of the idea]

(Field) The present invention relates to a constant measuring device that measures impedance using a vector voltage ratio. (Background) Conventional constant measuring devices of this type include a measurement circuit that applies a constant AC voltage to an impedance element to be measured via a range resistor, and a voltage signal and a current signal that respond to the impedance of the element to be measured. A detection circuit that generates a signal, a PLL circuit that generates a signal synchronized with the phase of one of these detection signals,
a phase signal generator that generates phase signals representing various phase periods from the synchronization signal; a phase discriminator that uses the phase signals to extract components of specific phase periods of the voltage signal and the current signal; It includes a calculator that calculates an impedance value from the extracted voltage signal component and current signal component.
Additionally, conventional measuring devices are equipped with an automatic range switching circuit that switches a range resistor to obtain optimal measurement conditions. The automatic range switching circuit responds to overflow and underflow signals generated from the computing unit as a result of calculations, and switches the range resistor to provide more suitable measurement conditions each time it receives these signals. In conventional devices having such a structure, generation of an overflow or underflow signal is essential for the automatic range switching circuit to operate. Therefore, it is necessary to actually repeat measurements and calculations until an appropriate range among the many prepared measurement ranges is reached, and as a result, there is a drawback that measurement takes time. Furthermore, in order to actually perform calculations, the PLL circuit must be locked and generate a phase signal under any measurement conditions or in any measurement range. Under certain measurement conditions, the input voltage to the PLL circuit can be very small, so the input sensitivity of the PLL circuit is made high so that it can be reliably locked even with this small voltage. However, if the input sensitivity is increased, it becomes weaker against external noise, resulting in malfunctions. Furthermore, in conventional equipment,
Since either the voltage signal or the current signal detected by the PLL is manually selected as the reference signal with which the phase is synchronized, completely automatic measurement cannot be performed, which is inconvenient. (Objective) The object of the present invention is to provide a constant measuring device that does not have the above drawbacks. Another object is to provide a constant measuring device equipped with an automatic range switching circuit that takes a short range switching time. Furthermore, another object is to provide a constant measuring device that automatically selects a series equivalent circuit and a parallel equivalent circuit during measurement. (Summary) In order to achieve the above object, the constant measuring device of the present invention includes a lock detecting means for detecting the presence or absence of a lock in a PLL circuit that generates a phase synchronized signal and generating a signal representing the lock, and and means for use as a control signal for automatic range switching. Furthermore, selection means is provided for selecting a predetermined equivalent circuit configuration in response to a range designation signal for automatic range switching and a signal indicating the type of impedance element to be measured. (Embodiment) FIG. 1 is a block diagram of an embodiment of a constant measuring device according to the present invention. First, the overall configuration of the constant measuring device will be explained. Incidentally, since the feature of the present invention lies in the measurement control circuit 40, other parts will be briefly explained. The impedance element Z _X measured by the constant measuring device is a measurement signal source 10
and range resistance R _R and range resistance selection switch 11
connected in a circuit consisting of. For convenience of explanation,
In this embodiment, eight measurement ranges are prepared, and the range resistor R _R is made up of five resistors a to e having different values for setting the eight measurement ranges. The voltage across element _Z
The current flowing _{through element Z} These voltage signal V _U and current signal _VR are connected to input terminals of an equivalent circuit changeover switch 20, which outputs either V _U or _VR depending on the state of another control input. When the current signal V _R is selected by the switch 20, it is a series equivalent circuit measurement, and the other voltage signal
When V _U is selected, parallel equivalent circuit measurement is performed.
Specifically, when there is a relationship of 10Z _X R _R , the circuit current i is determined by R _R , so V _R becomes a constant voltage, and V _U changes in proportion to the value of Z _X. Therefore,
Select series equivalent circuit measurement by using V _R as a reference signal, and convert i to V _R with voltage conversion.
The value of _ZX can be found by taking the vector voltage ratio with _VU . On the other hand, when Z _X 100R _R ,
V _U is a constant voltage, and V _R changes depending on the value of Z _X. At this time, the value of _ZX can be found by selecting a parallel equivalent circuit by using _VU as a reference signal, and also by taking the vector voltage ratio of both. The PLL circuit 22 is selected as a reference signal.
Generates a signal with four times the frequency that is phase synchronized with V _U or V _R. Phase signal generator 24 receiving this
is a 0° phase signal (0° to 180°) by performing appropriate frequency division.
generates a phase signal such as a 90° phase signal (indicating a phase period of 90° to 270°), a 180° phase signal (indicating a phase period of 180° to 360°), etc. Signal V _U
and V _R , phase discriminators 16 and 18 respectively receive
Signals V _U ′ and V _R ′ of the phase portion specified by the appropriate phase signal from the phase signal are provided to the arithmetic unit 26 . For example, in the case of measuring a capacitor, the phase discriminator 16 is given a 0° phase signal, and the phase discriminator 1
8 is given a 90° phase signal. The computing unit 26 is
The impedance value of Z _X is calculated by integrating the received V _U ′ and V _R ′ and taking the vector voltage ratio. The arithmetic unit has a terminal that outputs an overflow or underflow signal resulting from the arithmetic operation. Furthermore, the arithmetic unit is usually equipped with a reset terminal, and when the reset terminal is energized, the operation is stopped. The measurement control circuit 40, which is a feature of the present invention, is as follows:
PLL. It is connected to receive the signal from the circuit 22 and the overflow signal F5 and underflow signal F6 from the arithmetic unit 26, and the impedance type display 30 indicates whether the measured impedance _ZX is L, C, or R. receive a signal indicating that According to these input signals, the control circuit 40 controls the range resistance changeover switch 11 and the equivalent circuit changeover switch 20. Next, details of the measurement control circuit 40 will be explained with reference to FIG. FIG. 3 shows this control circuit 4.
FIG. 2 is a diagram showing the timing of operation of 0; As shown, the measurement control circuit 40 includes a PLL lock detection section 42, a range selection section 44, and an equivalent circuit selection section 46. The PLL lock detection section 42 includes a NAND gate 421 that receives a phase lead signal and a phase lag signal from a phase comparator (not shown) in the PLL circuit 22 via lines 23a and 23b, a diode 422,
It consists of a capacitor 423, a resistor 424, and a Schmitt circuit 425, and generates a lock signal F2. This lock signal F2 is high when the PLL circuit 22 is not locked and there is a phase lag or phase lead, and is low when the PLL circuit 22 is locked and there is neither a phase lag nor a phase lead. The range selection section 44 includes a clock generator 441 that generates a clock signal F1, a counter 442 having an up count input terminal, a down count input terminal, and eight output terminals indicating each of ranges 1 to 8. A range decoder 443 is connected to the eight output terminals of the counter 442 and generates a signal for selecting one of the range resistors a to e corresponding to the selected range. The selection unit 44 further includes an AND gate 4 that receives an overflow signal F5 from the arithmetic unit 26.
44 and AND which receives the underflow signal F6
A gate 445 is provided. These overflow signal F5 and underflow signal F6 are
It is provided to the up count input and down count input of counter 442 via OR gate 446 and OR gate 447, respectively. Counter 442, which generates a high signal at one of its eight output terminals, counts up and outputs a high signal from output terminal 1 (range 1) every time a pulse is applied to the up count input. Shift toward terminal 8 (range 8). On the other hand, when a pulse is applied to the down count input, the down count is reversed to that described above and the high signal is shifted from output terminal 8 to output terminal 1. In the conventional constant measuring device, range switching was performed only by the overflow signal F5 and underflow signal F6 generated by the arithmetic unit 26. In addition to this, the present invention uses the lock signal F2 generated by the PLL lock detector 42 for range switching. In detail, the lock signal F2 is
Provided to AND gates 448 and 449.
AND gate 448 is further supplied with a signal from OR gate 450 via inverter 451, and AND gate 449 is also supplied with a signal from OR gate 450.
The signal from 0 is input directly. OR gate 45
0 has its input connected to output terminals 5-8 of counter 442 and generates a high signal when ranges 5-8 are currently selected. In this embodiment, one of the series and parallel equivalent circuit measurements is selected for ranges 1-4, and the other is selected for ranges 5-8. When the output of OR gate 450 is high, the high state of lock signal F2 (PLL non-lock state) energizes the down count input through AND gate 449 and OR gate 447, thereby Do down. On the other hand, when the output of OR gate 450 is low, the high state of lock signal F2 is output via AND gate 448 and OR gate 446.
Activates the count input and performs range up.
The up count enable signal produced at the output of OR gate 446 by this lock signal and overflow signal F5 is shown as F3, and is ORed by lock signal F2 and underflow signal F6.
The down count enable signal produced at the output of gate 447 is designated as F4. As is clear from the above, this lock signal F2 of the present invention is
When the amplitude of the reference signal input to the circuit 22 is too small to be locked, the range is switched in a direction in which the amplitude of the reference signal becomes larger. Since the lock signal F2 is also applied to the reset terminal of the arithmetic unit 26, when the lock signal F2 is high indicating a non-locked state, the arithmetic unit is reset, and as a result, the arithmetic unit does not actually perform an operation and an overflow occurs. Signal F5 or underflow signal F
6 will never occur. The measurement control circuit 40 further includes an equivalent circuit selection section 46
It is equipped with The selection unit 46 receives signals from output terminals 1 to 8 of the counter 442 as input.
The selection section 46 further includes an impedance type display section 3.
Receives signal from 0. The indicator 30 consists of a resistor 31 and a switch 32 connected in series between the high +V voltage and ground. When _ZX is an inductance L and a pure resistance R, switch 32 is closed and produces a low signal; when _ZX is a capacitance, switch 32 is open and produces a high signal. When the impedance to be measured _Z
A high signal F7 is applied to the control input of switch 20 through AND gate 464 and OR gate 466, toggling switch 20 upward and selecting series equivalent circuit measurement. On the other hand, currently range 5
.about.8 is selected, a low signal F7 is applied to switch 20 through OR gate 466, thereby toggling switch 20 downward and selecting parallel equivalent circuit measurement. Also, _Z
When is capacitance, the opposite to the case of L or R above, when ranges 1 to 4 are selected, signal F7 becomes low and parallel equivalent circuit measurement is selected, and ranges 5 to 8 are selected. If so, signal F7 goes high and series equivalent circuit measurement is selected. In this way, the equivalent circuit selection section 46
An appropriate equivalent circuit measurement is automatically selected in response to the currently selected range and the type of impedance currently being measured. The range decoder 443 receives a signal indicating a range from output terminals 1 to 8 of the counter 442 and a signal from the impedance type display 30, and selects a predetermined range resistor a for each range setting.
Select one of ~e. As an example, the table below shows the relationship between each range, equivalent circuit, measurement range, and range resistor used when _ZX is L or R.

[Table] Next, the operation of the measurement control circuit 40 will be explained with reference to FIG. In addition, in Fig. 3, range 3
It shows the timing of switching from to range 6, and it is assumed that impedance measurement can be performed properly in range 6. First of all, counter 44
When output terminal 3 of 2 is high and range 3 is selected, signal F7 (not shown in FIG. 3) selects one equivalent circuit, such as series equivalent circuit measurement, and the voltage signal V _U is output to the PLL circuit. It will be put in at 22. Since this reference signal does not have the amplitude necessary to lock the PLL, a high lock signal F2 is generated indicating an out-of-lock condition. This signal F2 disables the operation of the arithmetic unit 26, and at the same time, the range up signal F3 becomes high at the clock pulse C1 of the clock signal F1, and the counter 4
Count up 42, resulting in range 4
is selected. In this range 4, series equivalent circuit measurement is still performed. At this time,
Since the amplitude of the reference signal _VU is small and the PLL does not lock, the lock signal remains high, and at the next pulse C2 of clock F1, the range up signal F3 goes high again, causing range 5 to be selected. When range 5 is selected, the equivalent circuit selection section 46 inverts the state of the signal F7 and selects the parallel equivalent circuit, so that the current signal V _R is used as the reference signal.
The signal is input to the PLL circuit 22. At this time, the PLL circuit 22 locks for the first time due to the increase in the amplitude of the reference signal, and the lock signal F2 becomes low. This low lock signal F2 releases the reset state of the arithmetic unit and causes the arithmetic operation to be executed for the first time. Assume that as a result of this calculation, an overflow occurs and the overflow signal F5 becomes high, and the optimum measurement conditions are not yet obtained. At this time, overflow signal F5 causes range up signal F3 to go high during pulse C4 of clock F1, causing counter 4 to
42 selects range 6. In this range 6, the PLL circuit is locked and the arithmetic unit 26 performs the calculation again, thereby making a proper impedance measurement. In the above explanation, the timing at the time of range up has been explained. On the other hand, during range down operation, range down signal F4 and underflow signal F6 are used to perform range switching and equivalent circuit switching in the same way. In the constant measuring device of the present invention described in detail above, the lock state of the PLL circuit 22 is determined and the measurement range is switched without performing calculations until the lock state is obtained. The range switching time can be shortened. Further, since the PLL circuit 22 is configured to determine whether the PLL circuit is locked, it is not necessary for the PLL circuit 22 to lock even to a small amplitude reference signal, and therefore a PLL circuit with low sensitivity can be used. Furthermore, since the sensitivity can be lowered, malfunctions of the constant measuring device due to noise can be prevented. Furthermore, since it is equipped with an equivalent circuit selection section 46, completely automatic measurement is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of a constant measuring device according to the present invention. FIG. 2 is a circuit diagram showing the measurement control circuit of the circuit of FIG. 1 in detail. FIG. 3 is a timing diagram showing the timing of the operation of the measurement control circuit of FIG. 2. Description of symbols, 10... Measurement signal source, 11... Range resistance selection switch, 12, 14... Amplifier, 1
6, 18... Phase discriminator, 20... Equivalent circuit changeover switch, 22... PLL circuit, 24... Phase signal generator, 26... Arithmetic unit, 30... Impedance type display, 40... Measurement control Circuit, 42...
...PLL lock detection section, 44...range selection section,
46...Equivalent circuit selection section.

Claims (1)

[Claims for Utility Model Registration] 1. A constant measuring device for measuring the impedance value of an impedance to be measured, which includes: (a) a range resistor R _R and a controllable range resistance switching means 11 for selecting the range resistor; (b) a type display means 30 that generates a type signal representing the type of the impedance to be _measured ; and (c) a detection circuit to which the impedance to be measured is connected. a first sensing output V _U that generates a parallel equivalent circuit measurement output representing the magnitude of the voltage across the
a detection circuit 12 having a second detection output V _R that generates a series equivalent circuit measurement output representing the magnitude of the current flowing through the impedance element to be measured;
14; d) controllable equivalent circuit switching means 20 which receives the first and second detection outputs and outputs either one as a reference signal; e) receives the reference signal from the equivalent circuit switching means; a PLL circuit 22 that generates a phase-synchronized output that is phase-synchronized with the reference signal when in the lock state; g) a first phase discriminator 16 that receives the first detection output and the first phase signal and generates a first phase discrimination output; 2 detection output and the second
a second phase discriminator 18 that receives the phase signal and generates a second phase discrimination output, h) an input terminal that receives the first and second phase discrimination outputs, an overflow output terminal, and an underflow output terminal. , a reset input terminal, and calculates the value of the impedance to be measured; and (i) a measurement control circuit 40 that includes: a) detecting whether or not the PLL circuit is in a lock state, and detecting whether or not the PLL circuit is in a lock state; Generate signal F2
PLL lock detection means 42; b) selection range 44 according to the type signal;
range selection means 44 for controlling the range resistance switching means to select three range resistors;
and c) the range selection means 44 for determining whether or not the selected range should be changed in response to the overflow signal F5 or underflow signal F6 from the arithmetic unit and the lock state signal; c) the type; A constant measuring device comprising: an equivalent circuit selection means 46 for controlling the equivalent circuit switching means in response to a signal and the selected ranges 461 and 462 of the range selection means; and the measurement control circuit 40. 2 Utility Model Registration Scope of the Claims In the device according to claim 1, the PLL lock detection means supplies the lock state signal F2 to the reset terminal of the arithmetic unit to detect when the PLL circuit is not in the lock state. A constant measuring device characterized in that the arithmetic unit is deenergized. 3 Utility Model Registration Scope of Claims 1. The device according to claim 1, wherein the range selection means also responds to the current selection range 450 to determine whether the selection range should be changed. Device. 4 Utility Model Registration In the device according to claim 1, the PLL circuit has a phase lead signal 2.
3a or a phase-lag signal 23b, and the PLL lock detection means generates the lock state signal in response to the phase-lead signal and the phase-lag signal.