JPH05182996A - Semiconductor device, its base material and bonding method - Google Patents
Semiconductor device, its base material and bonding methodInfo
- Publication number
- JPH05182996A JPH05182996A JP4000662A JP66292A JPH05182996A JP H05182996 A JPH05182996 A JP H05182996A JP 4000662 A JP4000662 A JP 4000662A JP 66292 A JP66292 A JP 66292A JP H05182996 A JPH05182996 A JP H05182996A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- melting point
- base material
- low
- point solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/381—Auxiliary members
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
(57)【要約】
【目的】 半導体チップを基材上にボンディングしてな
る半導体装置のダイボンド時間を短縮すること、及び後
工程での半導体チップの剥離を防止すること。
【構成】 三層構造の半田材料の四辺を囲むような突起
部分又は溝部分を基材に形成し、ダイボンド荷重により
流れ出た余剰低融点半田を半田材料側面と分離する。あ
るいは、ダイボンド荷重により半田材料側面に流れ出た
余剰低融点半田を酸化凝固させる。
【効果】 余剰低融点半田が拡散し終わるまでの時間が
不要となり、ボンディング時間が短縮でき、後工程での
溶融した余剰低融点半田の浸透による半導体チップの剥
離が防止できる。
(57) [Abstract] [Purpose] To reduce the die-bonding time of a semiconductor device in which a semiconductor chip is bonded onto a base material, and to prevent peeling of the semiconductor chip in a later step. A protrusion portion or a groove portion that surrounds four sides of a solder material having a three-layer structure is formed on a base material, and excess low melting point solder that has flown out due to a die bond load is separated from a side surface of the solder material. Alternatively, the excess low melting point solder that has flowed to the side surface of the solder material due to the die bond load is oxidized and solidified. [Effect] The time until the excess low melting point solder is diffused is not required, the bonding time can be shortened, and the peeling of the semiconductor chip due to the permeation of the melted excess low melting point solder in the subsequent step can be prevented.
Description
【０００１】[0001]
【産業上の利用分野】この発明は半導体装置、その基
材、及びその接合方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, its base material, and its bonding method.
【０００２】[0002]
【従来の技術】図６は従来の三層構造の半田材料による
ダイボンド時の構成図である。図において、１は半導体
チップ、７は例えば、リードフレームのような基材、３
は三層構造の半田材料の母材である高融点半田、４ａ，
４ｂは母材両面に配設された低融点半田、５は図示はし
ていないダイボンド荷重により側面に流れ出た余剰低融
点半田である。前記のような三層構造の半田を用いて、
液相拡散接合を行うと、半導体素子に作用する熱応力を
小さくすることができ、かつ接合部の耐温性は高温を保
つことができる。2. Description of the Related Art FIG. 6 is a block diagram of a conventional three-layer structure when a die bonding is performed using a solder material. In the figure, 1 is a semiconductor chip, 7 is a base material such as a lead frame, 3
Is a high melting point solder which is a base material of a three-layer structure solder material, 4a,
Reference numeral 4b is a low melting point solder disposed on both surfaces of the base material, and 5 is an excessive low melting point solder which flows out to the side surface due to a die bond load (not shown). Using the three-layer structure solder as described above,
By performing liquid phase diffusion bonding, the thermal stress acting on the semiconductor element can be reduced, and the temperature resistance of the bonded portion can be kept at a high temperature.
【０００３】次に詳細な製造方法について述べる。半導
体チップ１と基材７との間に半田３，４ａ，４ｂを挟ん
で加圧し、低融点半田の融点以上で、かつ高融点半田の
融点以下の温度に加熱して低融点半田４ａ，４ｂを溶融
させ、その後、温度を保持しておくことにより、低融点
半田４ａ，４ｂ中のＳｎが高融点半田３へ拡散し、最終
的には高融点半田３部と低融点半田４ａ，４ｂ部とが同
一組成になり、加熱温度より高い融点の半田を有する半
導体チップ１と基材７との接合が行われていた。Next, a detailed manufacturing method will be described. The solder 3, 4a, 4b is sandwiched between the semiconductor chip 1 and the base material 7 and pressed, and heated to a temperature higher than the melting point of the low melting point solder and lower than the melting point of the high melting point solder 4a, 4b. By melting and then maintaining the temperature, Sn in the low melting point solder 4a, 4b diffuses into the high melting point solder 3 and finally the high melting point solder 3 part and the low melting point solder 4a, 4b part The semiconductor chip 1 and the base material 7 having the same composition and solder having a melting point higher than the heating temperature are bonded to each other.
【０００４】[0004]
【発明が解決しようとする課題】従来の接合方法では、
溶融した低融点半田４ａ，４ｂがダイボンド荷重により
半導体チップ１や基材７との界面から外へ流れ出し、余
剰低融点半田５を形成していた。この余剰低融点半田５
を拡散させるためには長時間の熱処理が必要であり、仮
に拡散されていない部分があると、後のワイヤボンド，
モールド工程で再び余剰部分が溶融し、半導体チップ１
や基材７と三層構造の半田材料３，４ａ，４ｂとの界面
に浸透し、剥離を起こすなどの問題点があった。In the conventional joining method,
The melted low melting point solders 4a and 4b flowed out from the interface with the semiconductor chip 1 and the base material 7 due to the die bond load, and the surplus low melting point solder 5 was formed. This surplus low melting point solder 5
Requires a long heat treatment, and if there is a portion that has not been diffused, wire bonding,
The surplus portion is melted again in the molding process, and the semiconductor chip 1
Also, there is a problem in that it penetrates into the interface between the base material 7 and the solder material 3, 4a, 4b of the three-layer structure and causes peeling.
【０００５】この発明は上記のような問題点を解消する
ためになされたもので、ダイボンド時間が短縮できると
ともに、後のワイヤボンド，モールド工程での半導体チ
ップの剥離を防止することを目的とする。The present invention has been made to solve the above problems, and an object thereof is to shorten the die bonding time and prevent the semiconductor chip from being peeled off in the subsequent wire bonding and molding steps. ..
【０００６】[0006]
【課題を解決するための手段】この第１の発明に係る半
導体装置及び基材は、余剰低融点半田を三層構造の半田
材料の側面より分離するよう、基材のダイパッド部分に
半田材料四辺を囲むように周状突起部を形成させたもの
である。A semiconductor device and a base material according to the first aspect of the present invention have four sides of a solder material on a die pad portion of the base material so that an excess low melting point solder is separated from a side surface of a solder material having a three-layer structure. A circumferential projection is formed so as to surround the.
【０００７】また、第２の発明に係る半導体装置及び基
材は、余剰低融点半田が三層構造の半田材料の側面に溜
まらないよう、基材のダイパッド部分に半田材料四辺を
囲むように溝部分を形成させたものである。Further, in the semiconductor device and the base material according to the second aspect of the present invention, the die pad portion of the base material is provided with grooves so as to surround the four sides of the solder material so that excess low melting point solder does not collect on the side surfaces of the solder material of the three-layer structure. It is a part formed.
【０００８】さらに、第３の発明に係る接合方法は、三
層構造の半田材料の側面に溜まった余剰低融点半田に対
しこれを酸化させる処理を行い、融点を高くし凝固させ
るものである。Further, in the joining method according to the third aspect of the present invention, the excess low melting point solder accumulated on the side surface of the solder material having a three-layer structure is oxidized to increase the melting point and solidify it.
【０００９】[0009]
【作用】この発明においては、三層構造の半田材料四辺
を囲むような周状突起部又は溝部分を基材に形成させ、
ダイボンド荷重により流れ出た余剰低融点半田を半田材
料の側面より分離する、又は、半田材料の側面に溜まっ
た余剰低融点半田に対しこれを酸化させる処理を行い、
融点を高くし凝固させるようにしたので、余剰低融点半
田の拡散が不必要となり、熱処理時間が短縮できるとと
もに、再溶融による半導体チップの剥離が防止できる。In the present invention, the peripheral projections or grooves surrounding the four sides of the three-layer structure solder material are formed on the base material,
Excessive low melting point solder that has flowed out due to the die bond load is separated from the side surface of the solder material, or the excess low melting point solder accumulated on the side surface of the solder material is oxidized.
Since the melting point is increased and solidified, the excess low melting point solder does not need to be diffused, the heat treatment time can be shortened, and the peeling of the semiconductor chip due to remelting can be prevented.
【００１０】[0010]
【実施例】以下、この発明の一実施例を図について説明
する。図１は本発明の第１の実施例による半導体装置を
示す構成図である。図において、１は半導体チップ、２
は例えばワードフレームのような基材、３は三層構造の
半田材料の母材である高融点半田、４ａ，４ｂは母材両
面に配設された低融点半田、５はダイボンド荷重により
側面に流れ出た余剰低融点半田で、基材２には半田材料
３，４ａ，４ｂと余剰低融点半田５を分離するための周
状突起部が形成されている。また、図２は本発明の第１
の実施例による半導体装置の基材の外観を示す図であ
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a semiconductor device according to a first embodiment of the present invention. In the figure, 1 is a semiconductor chip, 2
Is a base material such as a word frame, 3 is a high melting point solder which is a base material of a three-layer structure solder material, 4a and 4b are low melting point solders arranged on both sides of the base material, and 5 is a side surface due to a die bond load. With the surplus low-melting-point solder that has flowed out, the base material 2 is formed with circumferential protrusions for separating the solder materials 3, 4a, 4b and the surplus low-melting-point solder 5. Further, FIG. 2 shows the first part of the present invention.
FIG. 3 is a diagram showing an appearance of a base material of a semiconductor device according to the example of FIG.
【００１１】本実施例１の半導体装置においては、半導
体チップ１と基材２とを半田材料３，４ａ，４ｂを挟ん
で加圧し、還元性雰囲気中で低融点半田の融点以上で、
かつ高融点半田の融点以下の温度に加熱して低融点半田
４ａ，４ｂを溶融させ、その後温度を保持しておくこと
により低融点半田４ａ，４ｂ中のＳｎが高融点半田３へ
拡散し、最終的には高融点半田３部と低融点半田４ａ，
４ｂ部とが同一組成になり、加熱温度より高い融点の半
田を生成させることにより、半導体チップ１と基材２と
が接合される。この時、加圧により流れ出た余剰低融点
半田５は基材２に半田材料３，４ａ，４ｂの四辺を囲む
ように形成された周状突起部により半田材料３，４ａ，
４ｂの側面より分離される。In the semiconductor device of the first embodiment, the semiconductor chip 1 and the base material 2 are pressed with the solder materials 3, 4a and 4b sandwiched therebetween, and the pressure is higher than the melting point of the low melting point solder in a reducing atmosphere.
In addition, the low melting point solders 4a and 4b are melted by heating to a temperature equal to or lower than the melting point of the high melting point solder, and then the temperature is maintained so that Sn in the low melting point solders 4a and 4b diffuses into the high melting point solder 3, Finally, 3 parts of high melting point solder and 4 m of low melting point solder,
The semiconductor chip 1 and the base material 2 are bonded to each other by forming the solder having the same composition as that of the portion 4b and having a melting point higher than the heating temperature. At this time, the excess low-melting-point solder 5 that has flowed out due to the pressure is applied to the solder material 3, 4a, 4a, 4b by the circumferential projections formed on the base material 2 so as to surround the four sides of the solder material 3, 4a, 4b.
It is separated from the side surface of 4b.
【００１２】以上のように本実施例によれば、余剰低融
点半田が半田材料側面へ接触しないので、余剰低融点半
田の拡散が不必要になるためボンディング時間が短縮で
き、また、後のワイヤボンド，モールド工程での半導体
チップの剥離を防止できる。As described above, according to this embodiment, since the surplus low melting point solder does not contact the side surface of the solder material, the diffusion of the surplus low melting point solder is unnecessary, so that the bonding time can be shortened and the subsequent wire It is possible to prevent peeling of semiconductor chips during the bonding and molding processes.
【００１３】図３は本発明の第２の実施例による半導体
装置を示す構成図である。また，図４は本発明の第２の
実施例による半導体装置の基材の外観を示す図である。
上記実施例１では基材に周状突起部を形成したものを示
したが、実施例２では図３の基材６の如く、半田材料
３，４ａ，４ｂの周囲に溝部分を形成させている。ダイ
ボンド荷重により、流れ出た余剰低融点半田５はこの溝
に流れ込み、半田材料３，４ａ，４ｂの側面に溜まるこ
とを防止できる。このように、本第２の実施例において
も、余剰低融点半田が半田材料側面へ接触しないので、
上記第１の実施例と同じ効果を得ることができる。FIG. 3 is a block diagram showing a semiconductor device according to a second embodiment of the present invention. In addition, FIG. 4 is a view showing the outer appearance of the base material of the semiconductor device according to the second embodiment of the present invention.
In the first embodiment, the base material is formed with the circumferential protrusions, but in the second embodiment, the groove portions are formed around the solder materials 3, 4a, 4b as in the base material 6 of FIG. There is. It is possible to prevent the excess low melting point solder 5 that has flowed out by the die bond load from flowing into this groove and accumulating on the side surfaces of the solder materials 3, 4a, 4b. As described above, also in the second embodiment, since the surplus low melting point solder does not contact the side surface of the solder material,
The same effect as the first embodiment can be obtained.
【００１４】図５は本発明の第３の実施例による接合方
法を示す図である。図５に示すように、構成は従来のも
のと同じである。実施例３では、半導体チップ１と基材
２とを半田材料３，４ａ，４ｂを挟んで加圧し、還元性
雰囲気中で低融点半田の融点以上で、かつ高融点半田の
融点以下の温度に加熱して低融点半田４ａ，４ｂを溶融
させ、その後温度を保持しておくことにより低融点半田
４ａ，４ｂ中のＳｎが高融点半田３へ拡散し、最終的に
は高融点半田３部と低融点半田４ａ，４ｂ部とが同一組
成になり、加熱温度より高い融点の半田を生成させるこ
とにより、半導体チップ１と基材２とが接合される時の
加圧により流れ出た余剰低融点半田５の未拡散部分に対
し、低融点半田４ａ，４ｂの拡散終了時に、酸化させる
処理を行い，これにより、融点を高くし凝固させてい
る。余剰低融点半田５の融点が高くなったため、余剰低
融点半田５を拡散させるための長時間の熱処理は不必要
となり、又、再溶融による半導体チップの剥離が防止で
きる。FIG. 5 is a diagram showing a joining method according to a third embodiment of the present invention. As shown in FIG. 5, the configuration is the same as the conventional one. In the third embodiment, the semiconductor chip 1 and the base material 2 are pressed against each other with the solder materials 3, 4a, 4b interposed therebetween, and the temperature is set to a temperature higher than the melting point of the low melting point solder and lower than the melting point of the high melting point solder in a reducing atmosphere. By heating and melting the low melting point solders 4a and 4b, and then maintaining the temperature, Sn in the low melting point solders 4a and 4b diffuses into the high melting point solder 3, and finally the high melting point solder 3 part is formed. The low melting point solders 4a and 4b have the same composition, and by generating a solder having a melting point higher than the heating temperature, excess surplus low melting point solder which flows out due to pressure when the semiconductor chip 1 and the base material 2 are bonded At the end of diffusion of the low-melting-point solders 4a and 4b, the undiffused portion 5 is subjected to oxidation treatment, thereby increasing the melting point and solidifying. Since the melting point of the surplus low-melting point solder 5 becomes high, the heat treatment for a long time for diffusing the surplus low-melting point solder 5 is unnecessary, and the peeling of the semiconductor chip due to remelting can be prevented.
【００１５】[0015]
【発明の効果】以上のように、この発明によれば、余剰
低融点半田の半田材料側面への接触をなくす、または半
田材料側面の余剰低融点半田を酸化凝固させることによ
り、余剰低融点半田の拡散が不必要になるためボンディ
ング時間が短縮でき、また、後のワイヤボンド，モール
ド工程での半導体チップの剥離を防止できる効果があ
る。As described above, according to the present invention, the surplus low melting point solder is eliminated from contact with the side surface of the solder material, or the surplus low melting point solder on the side surface of the solder material is oxidized and solidified. Since there is no need for diffusion, the bonding time can be shortened, and peeling of the semiconductor chip in the subsequent wire bonding and molding steps can be prevented.
【図１】この発明の第１の実施例を示す構成図。FIG. 1 is a configuration diagram showing a first embodiment of the present invention.
【図２】突起部分を形成させた基材の外観図。FIG. 2 is an external view of a base material on which protrusions are formed.
【図３】この発明の第２の実施例を示す構成図。FIG. 3 is a configuration diagram showing a second embodiment of the present invention.
【図４】溝部分を形成させた基材の外観図。FIG. 4 is an external view of a base material in which a groove portion is formed.
【図５】この発明の第３の実施例を示す構成図。FIG. 5 is a configuration diagram showing a third embodiment of the present invention.
【図６】従来の例を示す構成図。FIG. 6 is a configuration diagram showing a conventional example.
１ 半導体チップ ２ 突起部分を形成した基材 ３ 高融点半田 ４ａ 低融点半田 ４ｂ 低融点半田 ５ 余剰低融点半田 ６ 溝部分を形成した基材 ７ 従来の基材 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Base material with protruding portion 3 High melting point solder 4a Low melting point solder 4b Low melting point solder 5 Surplus low melting point solder 6 Base material with groove portion 7 Conventional base material
───────────────────────────────────────────────────── フロントページの続き (72)発明者 冨田 至洋 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (72)発明者 一山 秀之 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (72)発明者 大前 誠蔵 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Tomita 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture Mitsubishi Electric Corporation Kita-Itami Works (72) Hideyuki Ichiyama 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. Kita Itami Works (72) Inventor Seizo Ohmae 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. Kita Itami Works
Claims (5)
に低融点半田を配設した三層構造の半田材料を用いて、
低融点半田の融点以上、かつ高融点半田の融点以下の温
度で半導体チップを基材上にダイボンドしてなる半導体
装置において、 上記基材は、該基材上に上記三層構造の半田材料の四辺
を囲むように設けられた周状突起部を有し、 ダイボンド荷重により上記低融点半田の側面より該周状
突起部を越えてその外側に流れ出た余剰低融点半田が上
記半田側面より分離されてなることを特徴とする半導体
装置。1. A solder material having a three-layer structure in which a low melting point solder is provided on both surfaces of a high melting point solder formed as a base material,
In a semiconductor device in which a semiconductor chip is die-bonded onto a base material at a temperature not lower than the melting point of the low-melting point solder and not higher than the melting point of the high-melting point solder, the base material is a solder material of the three-layer structure on the base material. It has a peripheral projection provided so as to surround the four sides, and the surplus low-melting-point solder that has flowed out of the side surface of the low-melting solder over the peripheral projection by the die bonding load is separated from the solder side surface. A semiconductor device characterized by the following.
に低融点半田を配設した三層構造の半田材料を用いて、
低融点半田の融点以上、かつ高融点半田の融点以下の温
度で半導体チップを基材上にダイボンドしてなる半導体
装置の基材において、 該基材上に上記三層構造の半田材料の四辺を囲むように
設けられた周状突起部を有し、 ダイボンド荷重により上記低融点半田の側面より該周状
突起部を越えてその外側に流れ出た余剰低融点半田が上
記半田側面より分離されるようにしたことを特徴とする
半導体装置の基材。2. A solder material having a three-layer structure in which low melting point solder is provided on both surfaces of a high melting point solder formed as a base material,
In a base material for a semiconductor device, in which a semiconductor chip is die-bonded onto a base material at a temperature not lower than the melting point of the low-melting point solder and not higher than the melting point of the high-melting point solder, the four sides of the three-layered solder material are provided on the base material. It has a peripheral projection provided so as to surround it, so that excess low-melting-point solder that flows out from the side surface of the low-melting-point solder outside the side surface of the low-melting-point solder due to the die-bonding load to the outside is separated from the side surface of the solder. A base material for a semiconductor device characterized in that
に低融点半田を配設した三層構造の半田材料を用いて、
低融点半田の融点以上、かつ高融点半田の融点以下の温
度で半導体チップを基材上にダイボンドしてなる半導体
装置において、 上記基材は、該基材上に上記三層構造の半田材料の四辺
を囲むように設けられた溝部分を有し、 ダイボンド荷重により上記低融点半田の側面より流れ出
た余剰低融点半田は、上記溝部に流れ込み、上記半田側
面より分離されてなることを特徴とする半導体装置。3. A solder material having a three-layer structure in which low melting point solder is provided on both surfaces of a high melting point solder formed as a base material,
In a semiconductor device in which a semiconductor chip is die-bonded onto a base material at a temperature not lower than the melting point of the low-melting point solder and not higher than the melting point of the high-melting point solder, the base material is a solder material of the three-layer structure on the base material. It has a groove portion provided so as to surround four sides, and the surplus low melting point solder flowing out from the side surface of the low melting point solder due to a die bond load flows into the groove portion and is separated from the solder side surface. Semiconductor device.
に低融点半田を配設した三層構造の半田材料を用いて、
低融点半田の融点以上、かつ高融点半田の融点以下の温
度で半導体チップを基材上にダイボンドしてなる半導体
装置の基材において、 該基材上に上記三層構造の半田材料の四辺を囲むように
設けられた溝部分を有し、 ダイボンド荷重により上記低融点半田の側面より流れ出
た余剰低融点半田は、上記溝部に流れ込み、上記半田側
面より分離されるようにしたことを特徴とする半導体装
置の基材。4. A three-layer structure solder material in which low melting point solder is provided on both surfaces of high melting point solder formed as a base material,
In a base material for a semiconductor device, in which a semiconductor chip is die-bonded onto a base material at a temperature not lower than the melting point of the low-melting point solder and not higher than the melting point of the high-melting point solder, the four sides of the three-layered solder material are provided on the base material. It is characterized in that it has a groove portion provided so as to surround it, and surplus low-melting-point solder that flows out from the side surface of the low-melting-point solder due to a die bond load flows into the groove part and is separated from the solder side surface. Base material for semiconductor devices.
に低融点半田を配設した三層構造の半田材料を用いて、
低融点半田の融点以上、かつ高融点半田の融点以下の温
度で半導体チップを基材上にダイボンドする工程と、 上記ダイボンドにおいて、ダイボンド荷重により半田側
面に流れ出た余剰低融点半田に対しこれを酸化させる処
理を行い、これにより上記流れ出た半田の融点を高くし
凝固させる工程とを含むことを特徴とする接合方法。5. A solder material having a three-layer structure in which low melting point solder is provided on both surfaces of a high melting point solder formed as a base material,
A step of die-bonding a semiconductor chip onto a base material at a temperature not lower than the melting point of the low-melting point solder and not higher than the melting point of the high-melting point solder, and in the die bonding, oxidation of the excess low-melting point solder flowing to the solder side surface due to the die bond load And a step of increasing the melting point of the solder that has flowed out and solidifying the solder.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4000662A JP2997593B2 (en) | 1992-01-07 | 1992-01-07 | Semiconductor device, base material thereof, and bonding method |
| US07/955,307 US5372295A (en) | 1991-10-04 | 1992-10-01 | Solder material, junctioning method, junction material, and semiconductor device |
| US08/335,995 US5609287A (en) | 1991-10-04 | 1994-11-08 | Solder material, junctioning method, junction material, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4000662A JP2997593B2 (en) | 1992-01-07 | 1992-01-07 | Semiconductor device, base material thereof, and bonding method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05182996A true JPH05182996A (en) | 1993-07-23 |
| JP2997593B2 JP2997593B2 (en) | 2000-01-11 |
Family
ID=11479939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4000662A Expired - Lifetime JP2997593B2 (en) | 1991-10-04 | 1992-01-07 | Semiconductor device, base material thereof, and bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2997593B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019071412A (en) * | 2017-10-06 | 2019-05-09 | 財團法人工業技術研究院Ｉｎｄｕｓｔｒｉａｌ Ｔｅｃｈｎｏｌｏｇｙ Ｒｅｓｅａｒｃｈ Ｉｎｓｔｉｔｕｔｅ | Chip package |
| JP2024515156A (en) * | 2021-03-10 | 2024-04-05 | ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト | Substrate having sidewall, power semiconductor module including the substrate, and method for manufacturing the substrate |
-
1992
- 1992-01-07 JP JP4000662A patent/JP2997593B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019071412A (en) * | 2017-10-06 | 2019-05-09 | 財團法人工業技術研究院Ｉｎｄｕｓｔｒｉａｌ Ｔｅｃｈｎｏｌｏｇｙ Ｒｅｓｅａｒｃｈ Ｉｎｓｔｉｔｕｔｅ | Chip package |
| US11387159B2 (en) | 2017-10-06 | 2022-07-12 | Industrial Technology Research Institute | Chip package |
| JP2024515156A (en) * | 2021-03-10 | 2024-04-05 | ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト | Substrate having sidewall, power semiconductor module including the substrate, and method for manufacturing the substrate |
| US12568838B2 (en) | 2021-03-10 | 2026-03-03 | Hitachi Energy Ltd | Base plate having sidewall, power semiconductor module comprising the base plate and method for producing the base plate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2997593B2 (en) | 2000-01-11 |
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