JPH05183132A - Semiconductor rom cell programmed by using source mask - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] ROM that does not rely on using a gate oxide or field oxide to program a ROM cell under "on" or "off" conditions.
A method of manufacturing a cell structure and a ROM cell structure. [Structure] ROM cell 24 programmed to ON is N +
LD bridging the gap between the source and the N channel
It has N + source implants 26, 32 that are spaced a predetermined distance from the gate at D28, 30. ROM cell 40 programmed off has P + 56 implanted in this gap to completely override the LDD in this gap. The P + prevents the N channel from forming an ohmic connection to the N + source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is "on" or "off".
It relates to a ROM cell structure and a method of manufacturing a ROM cell structure that does not rely on using a gate oxide or field oxide to program the ROM cell under conditions.

[0002]

2. Description of the Related Art Read-only memory (ROM) is a semiconductor memory that has permanently stored information that can be read but cannot be erased or rewritten. In most applications, the information stored in ROM is written into memory during the manufacture of ROM memory devices. FIG. 1 shows a conventional ROM in the xz plane.
It is a schematic sectional drawing of a semiconductor device. The device shown here
It has a first cell 1 adapted to store a "1" and a second cell 2 adapted to store a "0". Each cell has a highly doped portion 4 and a lightly doped portion 6
And a source region having a gate electrode 8 and a highly doped portion 10 and a lightly doped portion 12. Cells 1 and 2 are separated from each other by a field oxide region 16. The gate 8 of each cell is insulated from the source 10 and drain 6 by oxide layers 17, 18, 19 as shown.

In cell 2, the thickness of oxide layer 19 below gate 8 of cell 1 is significantly smaller than the thickness of oxide layer 17 below gate 8 of cell 1. This difference represents the information content of the cell. When a suitable positive voltage is applied to the gate 8 of the cell 2, an electric field of sufficient magnitude is generated to form a temporary N-type channel (not shown) between the regions 6 and 10. Therefore, when a voltage is applied to the gate 8, the cell 2
An electric current flows through the transistor device. The transistor of cell 2 is "on" or active and it stores "0".

When the voltage applied to the gate 8 of cell 2 is applied to the gate 8 of cell 1, the greater thickness of oxide layer 17 is sufficient to allow current to flow from the drain to the source. Prevents the formation of a strong electric field. Therefore, the transistor of cell 1 will not turn on when this voltage is applied to its gate 8. Cell 1 is inactive and thus reads a "1". Of course, "0" and "1" are merely agreements. It is also possible to consider a cell in the off state as a "0" cell and a cell in the on state as a "1" cell.

However, the structure of the conventional ROM cell 2 may be exposed to electrical breakdown of the gate oxide film, which is a phenomenon known as gate oxide breakdown. It is possible that the polysilicon gate region retains charge during plasma etching to define a polycrystalline silicon (polysilicon) gate region 8 on the wafer surface or during ion implantation. Therefore, a voltage is generated between the polysilicon gate region 8 and the underlying substrate. The magnitude of this voltage is a function of oxide thickness. The voltage between the polysilicon gate region and the substrate per unit area of oxide increases as the oxide thickness increases. Conversely, the voltage between the substrate and the polysilicon gate region decreases as the oxide thickness decreases.

FIG. 2 is a schematic sectional view showing the gate region of the cell 2 in the yz plane. For the above-mentioned reason, the gate oxide film breakdown occurs in the ROM cell 2 and the ROM cell 2 does not function properly. The voltage on the gate oxide is given by:

[0007]

[Equation 1]

Q = charge per unit area A = area C = capacitance per unit area G = gate F = field oxide film This equation can be rewritten as the following equation.

[0009]

[Equation 2]

The unit capacitance can be expressed as ε _ox / t, and ε _ox = the dielectric constant of the oxide and t = the thickness of the oxide. Gate oxide breakdown is V / t _g > 10V / 1
Occurs when 00Å. Therefore, from equation (2) above,
When A _f / A _g is large when t _g / t _f is small,
That is, when it is about 1/30, the probability that the breakage will occur is highest. Therefore, in FIG. 2, destruction occurs when the area ratio of the regions 18 and 19 is large and the thickness ratio of the region 19 to the region 18 is small.

In the conventional ROM device, the thickness of the field oxide film is about 6000Å and the gate oxide film thickness is about 800Å, that is, the ratio is 7.5: 1. At this ratio, the voltage difference is such that the gate oxide breakdown is a phenomenon that occurs relatively infrequently. However, due to technological advances in integrated circuit manufacturing technology, the z direction (and also in the x and y directions)
Device density is significantly improved by scaling feature sizes. As a result, the thickness ratio between the field oxide region and the gate oxide region has changed significantly. Newer devices may have a ratio of field oxide thickness to gate oxide thickness of 6000Å to 200Å, or 30: 1. In newer devices, most of the polysilicon geometry is on the field oxide and a small residual area of it is on the gate oxide, and this gate oxide breakdown is conventional. It is much more likely to occur than it would be with a larger device.

[0012]

SUMMARY OF THE INVENTION The present invention is a ROM cell that does not rely on using a gate oxide or field oxide to program the ROM cell under "on" or "off" conditions. A method of manufacturing a structure and a ROM cell structure is provided. The probability of gate oxide breakdown in cells programmed with such a structure is significantly reduced.

In accordance with one embodiment of the present invention, a ROM cell, such as an N-channel device, has a P + conductivity type implant inserted between the N + conductivity type source and its channel. The P + type implant forms a reverse junction diode and prevents ohmic connection to the N channel extending from the drain to the source. ROM cells having this P + type implant are programmed to the inactive or "off" state. ROM cells that are configured to be "on" do not have this P + type implant. In other words, the application of the selected voltage turns on only those ROM cells that do not have P-type implants and not those that do not. Therefore, the resulting ROM device does not require the use of field oxide rather than gate oxide to program the individual cells into the on and off states. A _f / A _g is minimized because the polysilicon row lines have all cells whose gates have a gate oxide and neither cell has a field oxide gate. Further, the present technique allows cells programmed to an off or inactive state to be visually indistinguishable from cells programmed to an on or active state. There is. This feature prohibits discrimination by visual inspection and ROM
It provides security against unauthorized use of program code.

In accordance with another embodiment of the present invention, a typical source / drain P + type implant is used for drain and source N.
It is performed after forming the + type implant but before forming the metal layer on the wafer. A typical P + implant has a concentration of 1 × 10 ¹⁹ atoms / cm ³ and forms a leaky diode at the P + / N + interface. Therefore, the source of the resulting transistor is connected to the body of the device. The resulting ROM array is formed in the "T" layout of these devices.

According to yet another embodiment of the present invention, the RO
It is possible to form M arrays in the form of an "X" layout to improve ROM cell density per unit area beyond that achieved using the "T" layout. Furthermore, in the "X" layout configuration, it is possible to use masks for programming after metallization. The P + / N + diode is not leaky due to the reduced dopant concentration, and the source of the transistor no longer needs to be connected to the body.

[0016]

FIG. 3 is a schematic cross-sectional view of a ROM device 20 formed on a P-conductivity type semiconductor silicon substrate 22 formed according to an embodiment of the present invention. In a commercial embodiment, the ROM device typically has thousands or millions of cells, but the ROM device 2
It should be noted that the device 20 showing the first cell 24 and the second cell 40 is shown for convenience of explanation of FIG.
The first cell 24 has a drain, which may be composed of a more highly doped N + type region 26 and a lightly doped N− region 28. The sources of cell 24 are lightly doped N- region 30 and N +.
It can be composed of A gate insulating layer 34, typically silicon dioxide, is disposed between the polycrystalline silicon gate 36 and the cell substrate. The thickness of this layer does not depend on the information to be stored in the ROM cell.

Oxide layer 34 is sufficiently thin, typically 100 Å to 200 Å thick, so that when a positive voltage is applied to gate 36, a sufficiently large electric field is applied. Once formed, a temporary N-type channel (not shown) is formed and current flows through the transistor. Thus, the transistor of cell 24 is programmed to "on" or active, and in the prior art, when the cell is addressed, the cell is "read" as "0". Is.

FIG. 4 shows a schematic diagram for the ROM cell 24. The resistance of the N + type drain 26 is the gate 36,
Lightly doped portion 30 of source and N + source 32
Are shown in series. The resistance of the lightly doped portion 28 of the drain is not shown in FIG. Because its electrical resistance is negligible and is less than 10% of the lightly doped portion 30.

The ROM device 20 in FIG.
It has 0. Field oxide 42 is used to electrically isolate cell 24 from cell 40,
It also encloses a group of cells that typically share a common source region on the substrate, separating these cells from other nearby cells. Cell 40 is constructed in a similar manner to cell 24 and has a drain composed of an N + type region 44 and a lightly doped region 46 and a lightly doped drain region 48 and N +.
It has a source composed of the mold region 50. The oxide region 52 further includes a polysilicon gate 54 on the substrate 22.
Away from. However, in the cell 40, a P + type dopant is diffused or implanted into the region 48 to form a P + region 56 adjacent the region 50, with the cell operating as described below. Form diode blocking ohmic contacts to prevent. The P + region dopant is 1 μm wide. Therefore, cell 40 is considered to store a "1" when in the "off" or inactive state and when read.

FIG. 5 is a schematic diagram of cell 40, in which P + type implant region 56 includes diodes 58 and 5 between source contact 50 and lightly doped region 48.
9 is formed. Therefore, there is a reverse bias junction for the channel. In operation, when a voltage is applied to the gate 54 of the cell 40, the reverse bias junction generated from the P + implant 56 prevents formation of a channel between regions 44 and 50. Therefore, the cell 40
Transistor remains non-conductive. Therefore, cell 40 is always off and the value of that cell is "1" when addressed.

A comparison of cell 24 programmed to store a "0" with cell 40 programmed to store a "1" shows that the conductivity of the cell transistors is the same as in the conventional device of FIG. It is shown that it is not governed by the thickness of the film. Instead, the conductivity of the cell transistor is determined by the presence of a P + type implant 56 that inhibits the flow of charge between the source and drain. Therefore, the gate oxide of the ROM array can be constructed to a uniform thickness regardless of the desired programmed value of the ROM cell. Therefore, the gate oxide film 34 under the gate 36 of the cell 24 is
Need not be made thinner than the oxide film 52 below the gate 54 of the cell 4. Gate oxide film thickness (2
The ratio of field oxide (6000Å) to 00Å) is on the order of 30, which is typical for conventional field effect transistors. Capable of causing gate oxide breakdown and ROM cell failure caused by polysilicon lines that are mostly on the field oxide and a small percentage (less than 10%) on the thin gate oxide. High voltage polysilicon to substrate voltage differences are avoided. At that time, product yield and reliability are improved.

In the preferred embodiment, the P + implant used to form region 56 is implanted late in the standard CMOS process used to fabricate the ROM device. FIG. 6 illustrates a perspective view of a partially completed ROM device that is useful in explaining the process of manufacturing the ROM device of the present invention. The partially completed ROM of FIG. 6 shows two ROM cells with a common source region. The device has two polysilicon gate regions 60 and 62 formed over gate oxide regions 64 and 66. Oxide regions 64 and 6 as well as polysilicon gate regions 60 and 62
6 and the field oxide film region 68 are formed by a technique known in the art.

Next, as shown in FIG. 7, the structure of FIG. 6 is doped with an N-conductivity type impurity using a known technique,
An N-type region is formed in a portion where this structure is not covered with polysilicon or a field oxide film. As a result, lightly doped N-type regions 72, 74, 76 are formed. These lightly doped regions are about 2 × 1 with phosphorus.
Doped to an impurity concentration of 0 ¹⁷ atoms / cm ³ .

In FIG. 8, oxide spacers 78 are thermally grown and etched back to form an N + select mask, according to known techniques. The structure of FIG. 8 is then doped using techniques known in the art to form N + regions 84, 85, 86, as shown in FIG. The N + type region is 10 ²⁰ atoms / cm ^{3 of} arsenic.
Has a concentration of.

In a typical CMOS fabrication process, then the negative (ie complement) of the N-select mask.
Applied to the structure of FIG. 9 to form a PMOS on the CMOS device.
It defines the P + source / drain regions of the transistor.
In this process, in addition to defining the location of the P + implant in the off-programmed cells of the present invention, by opening the mask in the desired regions of the P + implant, the CMOS process flow is supplemented. It is possible to use the original mask. The resulting structure is as shown in FIG. 10, where the transistor on the right side of the drawing is exposed to P + implant 90, while programming the transistor to the inactive state, In addition, the transistor on the left side of the drawing was masked so that the P + implant was not formed. It should be noted that all ROM transistors have a gap at the source N +, so it is only necessary to use the P + mask to program the array. The N-type implant of the LDD bridges the gap to allow a device without P + to conduct current from the source to the drain. A metal layer is then deposited over the structure to provide the interconnect. Thus, the inventive structure can be achieved without departing from the process used to fabricate CMOS devices. In this process, although boron is used, the approximate concentration of the P + type impurity is 5 × 10 ¹⁹ atoms / cm ³ .

FIG. 11 shows R obtained using the technique of the present invention.
It is a schematic plan view showing an OM cell layout. 11
In, the ROM cells are arranged in orthogonal rows and columns to form a "T" layout. In FIG. 11, two rows 170 and 17 of transistors are shown.
Two and five columns 180-185 are shown, 2 × 5
Forming a matrix. Of course, it is possible to form a matrix having a desired size. In this structure, ROM transistors are arranged compactly. For example, a transistor located in row 170, column 180 may include a drain 190, a polysilicon gate 191, and
It is composed of a source 192. Row 172 column 180
The transistor located at is composed of a source 192, a polysilicon gate 194 and a drain 196. The drain via (through hole) 198 is in contact with the upper metal layer M1 as shown in the drawing. The second metal layer M2 (not shown) is used to contact the source region of the device. Via 200
And 202 provide contacts to the metal layer M2.
Approximate dimensions for the preferred embodiment are shown in microns in FIG. In the unit shown, the device has an areal density of 17.6 μm ² / ROM bits.

Since P + implant is not used, a further examination of FIG. 11 shows that both of the transistors located in column 180 store a "0".
However, the transistor located in row 70 column 83 and the transistor located in row 172 column 182 are configured to store a "1". Both transistors have P + type implants 210, 212 between the gate and source regions of their respective devices, as described above.
have. It should be noted that in the arrangement of the present invention, cells programmed "off" are visually indistinguishable from cells programmed "on". In the typical ROM cell shown in FIG. 1, a distinguishing physical feature of the "on" cell is a thin gate oxide located underneath the polysilicon gate material and thus visually inspected. It is possible. Therefore, the structure of the present invention provides additional security to the ROM program.

Since the P + implantation concentration in the CMOS process is on the order of 5 × 10 ¹⁹ atoms / cm ³ and the N + concentration is 10 ²⁰ atoms / cm ³ , the diode 62 formed at the N + / P + interface (see FIG. 5) causes current to leak under reverse bias conditions when the inventive construction is manufactured using the method described above. The source cannot be at a higher voltage than the P-type body because the P-type implant forms an ohmic contact to the P-type body. This limit limits the number of transistors connected to a single node. Therefore, the "T" layout described above with two transistors connected to a single drain node has been used.

An "X" layout can be used to provide improved areal density per bit. For example, in the case of the embodiment of FIG. 12, a density of 12.5 μm ² / ROM bits has been achieved. 12 is a schematic plan view of a ROM device having four cells in the "X" layout. Each four cells share a common source 250 that is contacted via a contact 252. Each cell has a polysilicon gate 254 and a drain 25
Have six. The drain is contacted to the metal layer using via 251. P + implant 260 is shown for one of the cells, programming that cell to the inactive state. The remaining cells are not programmed or written and are therefore active. Note that each drain contact is shared by four devices, and each source contact is shared by four devices. To decode the memory address for a particular ROM transistor in this structure, the ground voltage is only applied to the odd or even source columns, so there is no requirement for leakage between the source and ground. ..

By modifying the process described above and using an additional masking step for the P implant used to program the ROM, it is possible to create an "X" ROM layout. This additional masking step is an additional step to the typical CMOS process flow, thus allowing the use of lighter dose implants of P-type material than usual. For example, 5 × 10 ¹⁷ boron atoms / cm
It is possible to use an implant with an approximate concentration of ³ . This concentration is sufficient to overcompensate the lightly doped region with a phosphorus concentration of 2 × 10 ¹⁷ atoms / cm ³ . It is possible to use the programming mask after depositing gold on the structure. Figure 13
3 is a flow chart showing the process flow used to manufacture a ROM device incorporating the present invention in an "X" layout and a "T" layout. As will be appreciated, the process flow is similar, except that after the drain and source regions are formed in step 300, the P + region implant and metallization occur in different sequences.

The specific embodiments of the present invention have been described above in detail, but the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. It goes without saying that the above can be modified. For example, ROM devices of opposite polarity can be made by substituting P-type dopants for N-type dopants and vice versa.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a conventional ROM device.

FIG. 2 is a schematic sectional view showing a conventional ROM device in another aspect.

FIG. 3 is an RO configured according to an embodiment of the present invention.
The schematic sectional drawing which showed the M apparatus.

FIG. 4 is a schematic diagram showing a ROM cell programmed to an active state according to an embodiment of the present invention.

FIG. 5 is a schematic diagram showing a ROM cell programmed to an inactive state according to an embodiment of the present invention.

FIG. 6 is a schematic perspective view showing a partially completed ROM according to an embodiment of the present invention.

FIG. 7 is a schematic perspective view showing a partially completed ROM with lightly doped drain and source electrode regions formed according to one embodiment of the present invention.

FIG. 8 is a schematic perspective view showing a partially completed ROM having silicon dioxide spacers grown and etched back according to one embodiment of the present invention.

FIG. 9 is a schematic perspective view showing a partially completed ROM in which an N-type dopant is implanted to form drain and source regions according to an embodiment of the present invention.

FIG. 10 is an RO with a P + implant to program the cell into an inactive state according to one embodiment of the invention.
FIG. 3 is a schematic perspective view showing a partially completed ROM having M cells.

FIG. 11 is a schematic plan view showing a ROM device configured in a “T” configuration according to an embodiment of the present invention.

FIG. 12 is a schematic plan view showing a ROM device configured in an “X” configuration according to an embodiment of the present invention.

FIG. 13 has an “X” or “T” layout and P
FIG. 6 is a flow chart diagram illustrating a process according to one embodiment of the present invention used to manufacture a ROM incorporating a ROM cell with a + implant.

[Explanation of symbols]

 20 ROM Device 22 Silicon Substrate 24 First Cell 26 Highly Doped N + Type Region 28 Lightly Doped N− Region 30 Lightly Doped N− Region 32 N + Type Region 34 Gate Insulating Layer 36 Polysilicon Gate 40 Second Cell 42 Field oxide film 44 N + type region 46 Lightly doped region 48 Lightly doped region 50 N + type region 52 Oxide region 54 Polysilicon gate 56 P + region

Claims (37)

[Claims] 1. An RO formed on a substrate and comprising a plurality of individual storage cells programmed to an active state and a plurality of storage cells programmed to an inactive state.
An M device in the cell structure of the inactivated programmed cell, wherein an insulating layer is provided on the substrate, and a conductive gate electrode is provided on the insulating layer. A first conductivity type drain region is provided on the substrate adjacent to the gate electrode, and the substrate is adjacent to the gate electrode but spaced from the drain region. And a source region of a first conductivity type formed on the substrate adjacent to the implantation region and separated from the gate electrode by the implantation region. A cell structure characterized by being provided. 2. The cell structure according to claim 1, wherein the gate electrode comprises polycrystalline silicon. 3. The method according to claim 1, wherein the first conductivity type is N.
A cell structure having a type and said opposite conductivity type being a P type. 4. The implant region of claim 1, wherein the implant region is about 5.
A cell construction having a dopant concentration between x10 ^{17 and} 5x10 ¹⁹ atoms / cm ³ . 5. A ROM device formed on a substrate,
A plurality of storage cells programmed to an inactive state are provided, and the storage cells programmed to the inactive state include (a) a first source of a first conductivity type, and (b) the first source. An implant of a second conductivity type adjacent to, (c) a first drain formed of the first conductivity type and separated from the implant by a predetermined distance, and (d) located on the surface of the substrate. A first polysilicon gate having a first region adjacent to the first drain and a second region adjacent to the implant, and (e) the first polysilicon gate and the surface of the substrate. A first silicon dioxide layer disposed therebetween, and a plurality of storage cells programmed to an active state are provided, and the storage cells programmed to the active state are (A) a second source of the first conductivity type (B) a second drain formed of the first conductivity type and separated from the second source by a predetermined distance, and (c) located on the surface of the substrate and adjacent to the second drain. A second polysilicon gate having a first region and a second region adjacent to the second source; and (d) a second dioxide disposed between the polysilicon gate and the surface of the substrate. A ROM having a silicon layer. 6. The ROM of claim 5, wherein the storage cells are arranged in a "T" layout. 7. The ROM of claim 5, wherein the plurality of storage cells are arranged in an "X" layout. 8. The method of claim 5, wherein the first and second drains are further formed of a first conductivity type and are located adjacent the first regions of the first and second polysilicon gates, respectively. A ROM having a drain electrode formed therein. 9. The method according to claim 5, wherein the first conductivity type is N.
A ROM having a type substance and the second conductivity type having an N type substance. 10. The R according to claim 5, wherein the first source and the substrate are at substantially the same potential.
OM. 11. The injection portion according to claim 6, wherein the injection portion is approximately 5
A ROM having a dopant concentration of × 10 ¹⁹ atoms / cm ³ . 12. The injection part according to claim 7, wherein
A ROM having a dopant concentration of × 10 ¹⁷ atoms / cm ³ . 13. A plurality of ROM cells, a gate oxide layer, and a polysilicon gate formed on the surface of the gate oxide layer, the polysilicon gate being adjacent to the polysilicon gate, and being of a first conductivity type. In a method of manufacturing a ROM formed on a substrate on which a drain is formed and a source of a first conductivity type is formed at a predetermined distance from each other, selected to be programmed to an inactive state according to a desired programming pattern. The mask is formed on the surface of the substrate except the given region of the ROM cell, and the second conductivity type material is injected into the given region adjacent to the source and the polysilicon gate. A method comprising the steps of forming a second conductivity type implant between a source and a drain in a ROM cell. 14. The method according to claim 13, further comprising the step of forming a drain contact and a source contact, wherein the step of forming the mask and the step of implanting the material form the drain contact and the source contact. The method is performed before the step of performing. 15. The method of claim 14, wherein the step of implanting the material comprises implanting the material of the second conductivity type to a concentration of about 5 × 10 ¹⁹ atoms / cm ³ . 16. The method of claim 14, wherein the ROM is formed in a “T” layout. 17. The method according to claim 13, further comprising the steps of forming a drain contact and a source contact by metallization, wherein the step of forming the mask and the step of implanting the material include the drain contact and the source. A method which is performed after the step of forming the contact. 18. The method of claim 17, wherein the step of injecting the material comprises injecting the material of the second conductivity type to a concentration of about 5 × 10 ¹⁷ atoms / cm ³ . 19. The method of claim 17, wherein the ROM is formed in an "X" layout. 20. The method of claim 13, wherein injecting the second conductivity type material comprises injecting a P-type material. 21. A method of manufacturing a ROM, wherein a plurality of transistors are formed in a common substrate, each transistor having a source region and a drain region of a first conductivity type and being separated from each other by a predetermined distance. Wherein each of the source and drain regions has a highly doped major portion and a lightly doped portion, and the transistor is further located on the surface of the substrate and the lightly doped portion. Having a gate electrode adjacent to the doped portion, masking the selected transistor according to the desired programming code, exposing the plurality of transistors to a second conductivity type implant to lightly dope the source. Forming an implant region of opposite conductivity type at a portion and adjacent to the highly doped major portion of the source. The method of claim 1, wherein the transistor having a step and having the implant is programmed to an inactive state. 22. The method of claim 21, wherein masking the selected transistors is performed before forming drain and source contacts. 23. The method of claim 22, wherein the step of implanting the material comprises implanting the material of the second conductivity type to a concentration of about 5 × 10 ¹⁹ atoms / cm ³ . 24. The method of claim 22, wherein the ROM is formed in a "T" layout. 25. The method of claim 21, wherein masking the selected transistors is performed after forming drain and source contacts. 26. The method of claim 25, wherein the step of injecting the material comprises injecting the second conductivity type material to a concentration of about 5 × 10 ¹⁷ atoms / cm ³ . 27. The method of claim 25, wherein the ROM is formed in an “X” layout. 28. The method of claim 21, wherein injecting the second conductivity type material comprises injecting a P-type material. 29. A ROM having a plurality of individual storage cells formed on a substrate and programmed to an active state and a plurality of cells programmed to an inactive state.
A device, the cell structure of a cell programmed to the inactive state, having a gate electrode disposed on the surface of the substrate, disposed in the substrate, and highly doped. A drain region of a first conductivity type having a main portion of a drain and a lightly doped drain electrode portion, the drain electrode is adjacent to the gate electrode, and the source region of the first conductivity type is provided. Adjacent to the gate electrode and spaced from the drain region and disposed in the substrate, the source region comprises: (a) a highly doped major portion of a first conductivity type and a lightly doped source electrode. And (b) a second conductivity type implant region implanted into the lightly doped source electrode portion, the highly doped major portion being defined by the implant region. ROM, characterized in that it is spaced apart from the gate electrode. 30. The ROM of claim 29, wherein the storage cells are arranged to form a “T” layout. 31. The ROM of claim 29, wherein the plurality of storage cells are arranged to form an "X" layout. 32. The ROM of claim 29, wherein the first conductivity type comprises an N-type material and the second conductivity type comprises a P-type material. 33. The ROM according to claim 29, wherein the first source and the substrate are at substantially the same potential. 34. The ROM of claim 30, wherein the implant has a dopant concentration of about 5 × 10 ¹⁹ atoms / cm ³ . 35. The ROM of claim 31, wherein the implant has a dopant concentration of about 5 × 10 ¹⁷ atoms / cm ³ . 36. The second source of claim 5, wherein the second source further comprises a source electrode formed of the first conductivity type and located adjacent to a second region of the second polysilicon gate. ROM characterized by. 37. The injection portion according to claim 5, wherein the second conductivity type injection portion is formed in a source electrode of the first diode, and a diode is formed between the injection portion and the first source. ROM that is characterized by.