JPH05189078A - System clock selecting circuit - Google Patents

Abstract

PURPOSE:To provide the system clock selecting circuit which enables a backup process such as a saving process for data even if a system clock suddenly stops. CONSTITUTION:A clock stop detection part 5 outputs '0' when a 1st clock 3 is normal or '1' when the 1st clock 3 stops. A multiplexer 2 outputs the 1st clock 3 when the output of the clock stop detection part 5 is '0' or a 2nd clock when '1'. Further, this circuit may be provided with an interruption request generation part which generates an interruption request signal according to a clock stop detection signal 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system, such as a microcomputer, which operates in synchronism with a system clock and is capable of performing a backup process or the like when an abnormality occurs in the system clock. The present invention relates to a clock selection circuit.

[0002]

2. Description of the Related Art Generally, a microcomputer operates in synchronization with a system clock generated by an oscillator circuit. In addition, when processing an instruction, the microcomputer usually generates various timing signals based on the system clock, and fetches and decodes instruction codes, loads data, operates and stores data based on the timing signals. The processing is sequentially executed. Therefore, it is generally necessary that the system clock is always supplied while the circuit is operating.

CMOS (Complementary Metal Ox)
In many cases, a CMOS computer configured by ide Semiconductor) has a mode in which only internal data is backed up (hereinafter referred to as a standby mode). In this standby mode, the system clock is stopped to stop the execution of instructions and reduce current consumption. In this case, the internal system clock is stopped at a specific timing, so the microcomputer should execute the data backup processing correctly, and if the system clock input is restarted, normal instruction processing should be executed thereafter. You can

[0004]

However, in the microcomputer, except when the computer provided with the standby mode described above is in the standby mode, etc.
If the system clock suddenly stops for some reason, the entire system to which the microcomputer is applied will stop operating. Therefore, even if the system clock is restored to a normal state after the data is lost, the operation before the system clock is stopped cannot be continued.

That is, if a dynamic circuit (DRAM) is used inside the microcomputer, data and the like will be lost while the clock is stopped. Even if the dynamic circuit is not used, the temporal width and voltage level of the pulse become unstable immediately before the clock stops, and the clock stops asynchronously. , Even if the clock is supplied again, normal operation cannot be expected.

If only the stop of the system clock is detected, for example, a watchdog timer may be provided outside the microcomputer. That is, in order to prevent the external watchdog timer from overflowing, the microcomputer outputs a signal for clearing the timer within a predetermined period. Then, when the system clock stops, the watchdog timer overflows because the timer clear signal is not output from the microcomputer. Thereby, the stop of the system clock or the runaway of the program of the microcomputer can be detected.

However, in this case, although the stop of the system clock can be detected by providing the watchdog timer outside the microcomputer, the system clock itself is stopped, so that the backup processing for saving the data etc. Can not be executed.

Utilizing the output of the watchdog timer,
If the system clock stops, another clock may be supplied as the system clock and the backup process may be executed by this clock. However, the watchdog timer uses the overflow of the timer to respond to the abnormality detection. The sex is slow. For this reason,
Data and the like will be lost between the time when the system clock is stopped and the time when it is switched to another clock.

Not only the above-mentioned microcomputer but also an LSI (large-scale integrated circuit) which operates in synchronization with the system clock, when the system clock suddenly stops, even if the system clock returns to a normal state,
There is a risk of malfunction.

The present invention has been made in view of the above problems, and provides a system clock selection circuit capable of supplying a clock for performing backup processing or the like when an abnormality occurs in the system clock. The purpose is to

[0011]

A system clock selection circuit according to the present invention receives a clock stop detection unit for generating a stop detection signal when a first clock stops, and inputs the first clock and the second clock. A clock switching circuit that outputs the first clock when the stop detection signal is not output from the clock stop detection unit and outputs the second clock when the stop detection signal is output. Characterize.

[0012]

In the present invention, when the first clock is stopped, the clock stop detector generates the stop detection signal. Further, in the present invention, the clock switching circuit is supplied with the first and second clocks. This clock switching circuit
When the stop detection signal is not output from the clock stop detection unit, the first clock is output. When the stop detection signal is output from the clock stop detection unit, the output is switched from the first clock to the second clock. Therefore, even if the first clock is stopped for some reason, the second clock is supplied to the system. This makes it possible to execute a backup process such as saving data.

In order to perform operations such as saving data when the first clock is stopped, it is preferable to output an interrupt request signal to, for example, a microcomputer and immediately execute saving data by interrupt processing. .. Therefore, it is preferable to include an interrupt request generation unit that generates an interrupt request signal according to the stop detection signal.

[0014]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a system clock selection circuit according to the first embodiment of the present invention.

The clock stop detection unit 5 uses the first clock 3
When the first clock 3 is stopped, "1" is output as the clock stop signal 14, and when the first clock 3 is normal, "0" is output. The multiplexer 2 has a first clock 3 and a second clock 3.
The clock 4 is input, and one of them is output as the system clock 1 based on the output of the clock stop detection unit 5. That is, the multiplexer 2 outputs the first clock 3 when the clock stop detection signal 14 is “0”,
When the clock stop detection signal 14 is "1", the second clock 4 is output.

Further, the one-shot multivibrator 1
No. 5 generates a one-shot pulse when the clock stop detection signal 14 changes from "0" to "1". This one-shot pulse is output as the system reset signal 16 via the OR gate 15a. The reset signal 17 is also supplied as a system reset signal 16 to each circuit in the system via the OR gate 15a.

The clock stop detector 5 includes resistors 6 and 7,
Capacitors 8 and 9 and N-channel transistors 10 and 1
1, an inverter 12, and an OR gate 13. That is, the resistor 6 and the capacitor 8 are connected in series between the power supply and the ground, and the transistor 10 is connected in parallel with the capacitor 8. Then, the first clock 3 is applied to the gate of the transistor 10.
The interconnection point A of the resistor 6, the capacitor 8 and the transistor 10 is connected to one input end of the OR gate 13.

Similarly, the resistor 7 and the capacitor 9 are also connected in series between the power source and the ground, and the transistor 11 is connected in parallel to the capacitor 9. The gate of the transistor 11 has the first clock 3
Are inverted and provided by the inverter 12. The interconnection point B of the resistor 7, capacitor 9 and transistor 11 is connected to the other input terminal of the OR gate 13. The clock stop detection signal 14 is the output of the OR gate 13.

Next, the operation of the clock stop detector 5 will be described.

The capacitor 8 is charged via the resistor 6,
When the voltage at the connection point A exceeds the logic threshold voltage of the OR gate 13, the clock stop detection signal 14 which is the output of the OR gate 13 becomes "1". However, when the first clock 3 is normal, the voltage at the connection point A is OR gate 13
Before the logic threshold voltage of 1 is exceeded, the first clock 3 becomes "1", the N-channel transistor 10 is turned on, the charge of the capacitor 8 is discharged, and the voltage of the connection point A decreases.

Similarly to the circuit formed by the capacitor 9, the resistor 7 and the N-channel transistor 11, when the first clock 3 is normal, the voltage at the connection point B is the logic threshold voltage of the OR gate 13. Before exceeding N, the N-channel transistor 11 is turned on, and the voltage at the connection point B decreases. However, since the first clock 3 is applied to the gate of the N-channel transistor 11 via the inverter 12, the charge of the capacitor 9 is discharged when the first clock 3 is "0".

Therefore, even when the first clock 3 is stopped in either "0" or "1" state, the voltage at either the connection point A or the connection point B becomes the logic threshold voltage of the OR gate 13. And the clock stop detection signal 14 becomes "1".

FIG. 2 is a timing chart showing the operation of the circuit of this embodiment.

At the timing (T1, T3, T5) when the first clock 3 becomes "1", the electric charge of the capacitor 8 is discharged and the voltage at the connection point A becomes 0V. However, when the first clock 3 is stopped (T6), the voltage at the connection point A continues to rise. The voltage at the connection point A is the OR gate 13.
Timing of exceeding the logic threshold voltage of (T7)
Then, the clock stop detection signal 14 becomes "1", and the system clock 1 changes from the first clock 3 to the second clock 4
Switch to.

The system reset signal 16 is output when the clock is switched, but this is the stop of the clock (T
If the time from 6) to clock switching (T7) is long,
This is to prevent the program from running away when an unstable clock is generated before the first clock 3 stops.

In this embodiment, the system clock 1
Even if the first clock 3 is suddenly stopped for some reason, the clock stop detection unit 5 detects this and the multiplexer 2 outputs the second clock 4 as the system clock 1 based on the output, Backup processing and the like can be executed. Further, the clock stop detection signal 14 can be used to notify the occurrence of an abnormality to the outside.

FIG. 3 is a circuit diagram showing a system clock selection circuit according to the second embodiment of the present invention.

The present embodiment is different from the first embodiment in that the configuration of the clock stop detection unit is different, and the other configurations are basically the same as those in the first embodiment. In FIG. 1, the same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The clock stop detector 5a is a D-flip-flop circuit (hereinafter referred to as D-F / F) 18, 19, 2.
0, 21 and OR gates 13a, 22 and 23. The D-F / Fs 18 and 20 are 1-bit counters that count the second clock 4, and when a carry occurs, the Q output of the D-F / Fs 19 and 21 becomes "1".
The clock stop detection signal 14 becomes "1". Also, D-
The F / Fs 18 and 20 are adapted to be cleared by the first clock 3.

Therefore, the second clock 4 is set to DF / F1.
When the first clock 3 is input by the time 8 and 19 count and carry occurs, the clock stop detection signal 14 maintains "0".

If the first clock 3 is stopped at "0", the DF / F18 is not cleared, and if stopped at "1", the DF / F20 is not cleared. Is detected and the clock stop detection signal 14 becomes "1".

FIG. 4 is a timing chart showing the operation of the circuit of this embodiment.

At the timing (T1, T3, T6, T7) when the second clock 4 rises, the 1-bit counter composed of the DF / F 18 counts up. When the first clock 3 is normal, the D-F / F 18 is cleared at the timing (T2, T4) when the first clock 3 rises. However, when the first clock 3 is stopped (timing T5), the DF / F18 is not cleared,
A carry occurs at timing T7 and the clock stop detection signal 14 becomes "1". As a result, the multiplexer 2 outputs the second clock 4 as the system clock 1 as in the first embodiment. At the same time, the system reset signal 16 is output.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 5 is a circuit diagram showing a system clock selection circuit according to the third embodiment of the present invention.

The present embodiment is different from the first embodiment in that the output of the clock stop detector 5 is R as an interrupt request generator.
Since it is also applied to the S-flip-flop circuit (hereinafter referred to as RS-F / F) 33, and the other configuration is basically the same as that of the first embodiment, FIG. The same reference numerals are given to the same components, and detailed description thereof will be omitted.

The clock stop detection signal output from the clock stop detector 5 is applied to the one-shot multivibrator 31, RS-F / F 33 and multiplexer 2.

The multiplexer 2 outputs the first clock 3 as the system clock 1 when the clock stop detection signal 14 is "0", and outputs the second clock 4 when the clock stop detection signal 14 is "1". Output as 1.

The clock stop detection signal 14 is "1".
Then, the RS-F / F 33 is set to "1", and the interrupt request signal 34 is generated and output to the microcomputer. The interrupt request signal 34 is reset to "0" when the interrupt acceptance signal 35 given from the microcomputer becomes "1".

Further, the clock stop detection signal 14 is "1".
Then, the one-shot multivibrator 31 outputs the hardware reset signal 32.

FIG. 6 is a timing chart showing the operation of the circuit of this embodiment.

At the timing (T1, T3, T5) when the first clock 3 becomes "1", the electric charge of the capacitor 8 is discharged and the voltage at the connection point A becomes 0V. However, when the first clock 3 is stopped (T6), the voltage at the connection point A continues to rise. The voltage at the connection point A is the OR gate 13.
Timing of exceeding the logic threshold voltage of (T7)
Then, the clock stop detection signal 14 becomes "1", and the system clock 1 changes from the first clock 3 to the second clock 4
Switch to.

At the same time, RS-F / F33 becomes "1".
And an interrupt request signal 34 is generated,
A hardware reset signal 32 is output from the one-shot multivibrator 31. When the interrupt request signal 34 is input, the microcomputer executes a predetermined interrupt process and saves data, for example. If the clock stop (T6) to the clock switch (T7) is long, or if an unstable clock occurs before the first clock 3 stops, the internal circuit of the microcomputer becomes abnormal. Therefore, the hardware reset signal 32 is used for initializing the circuit because the interrupt processing may not be normally executed.

In this embodiment, the RS-F / F 33 generates an interrupt request signal and outputs the interrupt request signal to the microcomputer. Therefore, processing such as data saving can be immediately executed as interrupt processing.

FIG. 7 is a circuit diagram showing a system clock selection circuit according to the fourth embodiment of the present invention.

The seventh embodiment is different from the third embodiment in that the clock stop detector 5a has a different configuration, and the other configurations are basically the same as those in the third embodiment. In the figure, the same parts as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

The clock stop detection unit 5a has a D-F / F1
It is composed of 8, 19, 20, and 21, an inverter 12, and an OR gate 13a. DF / F18, 2
0 is a 1-bit counter that counts the second clock 4, and when a carry occurs, Q of DF / F 19, 21
The output becomes "1" and the clock stop detection signal 14 becomes "1". The D-F / Fs 18 to 21 are cleared by the first clock 3.

Therefore, the second clock 4 is set to D-F / F1.
If the first clock 3 is input by the time 8 and 20 count and the carry occurs, the clock stop detection signal 14 maintains "0".

When the first clock 3 stops at "0",
If the D-F / F 18 is not cleared and the first clock 3 is stopped at "1", the D-F / F 20 is not cleared. In any case, a carry occurs, the stop of the clock is detected, and the clock is detected. The stop signal 14 becomes "1".

FIG. 8 is a timing chart showing the operation of the circuit of this embodiment.

At the timing (T1, T3, T6, T7) when the second clock 4 rises, the 1-bit counter composed of the DF / F 18 counts up. When the first clock 3 is normal, the D-F / F 18 is cleared at the timing (T2, T4) when the first clock 3 rises. However, at timing T6, the first clock 3
When is stopped, DF / F18 is not cleared, so
A carry occurs at timing T7 and the clock stop signal 14 becomes "1". This allows the system clock 1
Switches from the first clock 3 to the second clock 4.

At the same time, RS-F / F33 becomes "1".
And an interrupt request signal 34 is generated,
A hardware reset signal 34 is output from the one-shot multivibrator 33.

Also in this embodiment, the same effect as that of the third embodiment can be obtained.

[0055]

As described above, according to the present invention, the clock switching circuit outputs the first clock when the first clock is normal, and the clock stop detector detects the abnormality of the first clock. Then, because the second clock is output,
In a system such as a microcomputer, a backup process such as a data saving process can be executed even if an abnormality occurs in the system clock. As a result, it is possible to guarantee the operation when returning to the normal state, and it is possible to improve the reliability of the system.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a system clock selection circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart diagram showing the same operation.

FIG. 3 is a circuit diagram showing a system clock selection circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the same.

FIG. 5 is a circuit diagram showing a system clock selection circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing the same operation.

FIG. 7 is a circuit diagram showing a system clock selection circuit according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart diagram showing the same operation.

[Explanation of symbols]

 2; Multiplexer 5, 5a; Clock stop detecting unit 6, 7; Resistor 8, 9; Capacitor 10, 11; Transistor 12; Inverter 13, 13a, 15a, 22, 23; OR gate 15, 31; One-shot multivibrator 18 ~ 21; D-F / F 33; RS-F / F

Claims (2)

[Claims] 1. A clock stop detection unit that generates a stop detection signal when a first clock stops, and the clock stop detection unit outputs the stop detection signal by inputting the first clock and the second clock. And a clock switching circuit which outputs the first clock when the stop detection signal is output and outputs the second clock when the stop detection signal is output. 2. The system clock selection circuit according to claim 1, further comprising an interrupt request generator that generates an interrupt request signal in response to the stop detection signal.