JPH05189276A - Exclusive control history acquisition method - Google Patents

Abstract

PURPOSE:To correctly acquire execution history while influence given to the execution state of a parallel program is suppressed to a minimum by providing a register to show the presence of the acquisition of history in each CPU, and storing the execution history in a shared memory while keeping still a bus lock state if the register is ON. CONSTITUTION:The register 203 to show whether the execution history of an instruction accompanying bus lock is to be acquired or not is provided in the CPU 200, and if the register is ON, a microprogrammed instruction stores the information of a program counter, etc., or the information of a time stamp, etc., by a global timer in a storing destination address on a memory after setting the bus lock state in addition to original work such as the rewriting of the contents of the memory, etc. On the contrary, if the register 203 is OFF, it executes the original work after setting the bus lock state, and releases a shared bus. Through this method, the execution history can be acquired correctly, and besides, the influence to the execution state of the parallel processing program can be minimized compared with the method by softwave.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive control execution history acquisition method in a tightly coupled parallel processing computer system.

[0002]

2. Description of the Related Art Conventionally, in a tightly coupled parallel processing system configured by using a memory rewriting instruction accompanied by a bus lock, when it is desired to obtain an exclusive processing control execution history realized by using the memory rewriting instruction, Although this is done by software, there is a problem that the history information becomes incorrect because the information cannot be acquired atomically when the instruction occurs, and the execution status of the program changes due to execution of the history acquisition instruction.

[0003]

As described in the prior art, in the execution history acquisition method of the special instruction involving the bus lock by the conventional software, the history cannot be acquired accurately in the tightly coupled parallel processing system. .. This is because even if the execution history is written immediately after the instruction, the CPU other than the CPU that is executing the procedure may secure the shared bus before the writing instruction. The history acquisition by software not only cannot acquire an accurate execution history, but also inserts redundant execution history acquisition instructions to synchronize with each other and to check the execution status of parallel programs executed on multiple CPUs. It will change.

The present invention has been made to solve the above problems, and has as its object the improvement of the efficiency of debugging work in a tightly coupled parallel processing system and the acquisition of history information for performance tuning.

[0005]

SUMMARY OF THE INVENTION In order to perform exclusive control in a tightly coupled parallel processing system, the present invention is directed to another C
For a memory rewrite instruction involving a bus lock that prohibits a bus access of a PU, a register is provided in the CPU to indicate whether or not the execution history of the instruction accompanied by the bus lock is acquired. In addition to the original work such as rewriting the memory contents of the programmed instruction in the bus lock state, for example, information such as a program counter in a general-purpose register and information such as a time stamp by a global timer are stored in the register. It is stored in a storage destination address on the memory, which is stored in advance by software. On the contrary, if the register is OFF, the bus is locked and only the original work is executed to release the shared bus.

The execution history of the instruction accompanied by the bus lock thus obtained is fetched for all CPUs, and the execution history is analyzed by arranging the execution history in time series by the time stamp.

[0007]

According to the present invention, in the tightly coupled parallel processing system, the execution history of the exclusive control instruction with the shared bus lock is acquired accurately and the influence on the execution of the parallel processing program is acquired to the minimum. It becomes possible.

[0008]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a system configuration diagram of a tightly coupled parallel processing system to which the present invention is applied.
N Cs denoted by the numbers 1, 103, 104, and 105
The PU, global timer, and I / O device 107 are connected. All CPUs 2 connected to the shared bus
00 has the configuration shown in FIG. 2, 201 is a memory bus, 202 is a processing unit, and 203 is a register indicating whether or not execution history of a bus lock instruction is acquired.

In the CPU according to the present invention, the bus lock instruction is performed in the procedure shown in FIG. However, the history flag in 301 indicates the register 203, and the register stores the address on the memory of the history information storage destination. The register is set by software, and if the value is 0, it indicates that the execution history acquisition flag is OFF.

If a bus lock command is issued, lock the shared bus with 300, see register 203,
If the history flag is 0 in 301, that is, if history acquisition is not performed, the original instruction execution of 305, for example, rewriting the memory content of the specified address,
The shared bus is released at 6 and the process ends. In 201, 203 is 0
If the memory address value is a value other than, that is, when the history is acquired, the global timer is read at 302, the necessary information is read from the general-purpose register at 303, and the history information indicated by the register 203 is read. The file is stored in the storage destination, the original instruction is executed in 305, the shared bus is released in 306, and the processing is terminated.

[0011]

As described above, according to the present invention, in the tightly coupled parallel processing system, the execution history of bus lock instructions issued for exclusive control between CPUs and the method by software are compared. It is possible to accurately and moreover minimize the influence on the execution state of the parallel processing program.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a tightly coupled parallel processing system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a CPU in FIG.

FIG. 3 is a flowchart illustrating an operation of the embodiment.

[Explanation of symbols]

 101 shared memory 102 shared bus 103-105 CPU 106 global timer 107 I / O device 200 CPU 201 memory bus 202 processing unit 203 history acquisition flag register

Claims (1)

[Claims] 1. An exclusive control characterized in that by providing a register indicating whether history is acquired in each CPU, if the register is ON when a bus lock instruction occurs, the execution history is written out in the bus locked state. History acquisition method.