JPH05190480A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide an excellent semiconductor device having small junction leakage by forming a shallower junction in technique for shallowing a junction depth of the device. CONSTITUTION:After a layer (N-type well) 2 in which impurities are implanted is formed on a semiconductor substrate 1, it is annealed in an N2 atmosphere, the impurities in the vicinity of its surface are externally diffused to reduce its impurity concentration. As a result, an ion implanting amount for forming a junction is reduced, and a shallow junction can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming a MOSFET, a bipolar transistor, or the like on a Si substrate in a semiconductor device to reduce the junction depth.

[0002]

2. Description of the Related Art Conventionally, as a method for obtaining a shallow junction in manufacturing a semiconductor device, for example, the 37th Society of Applied Physics, Proceedings, 30P-ZF-5 (1990).
p. 649 and the like, a shallow junction is formed by forming an amorphous layer in a Si substrate by pre-ion implantation and suppressing channeling associated with subsequent ion implantation (hereinafter referred to as ion implantation). ..

The 37th Biological Society of Japan Proceedings 30P-Z
F-2 (1990) p. As disclosed in 648 and the like, a method of suppressing the junction depth by F implantation by ion implantation is also used.

[0004]

However, according to the above-mentioned method, the S ion is removed by pre-ion implantation or F ion implantation.
There has been a problem that a crystal defect occurs in the i crystal, which causes a junction leak.

In any of the methods, the counter-doped ion implantation for controlling the threshold requires the above-mentioned impurity ion implantation amount in order to cancel the substrate concentration, and as a result, it is formed immediately after the ion implantation. There was a problem that the tail of the impurity profile in the substrate direction becomes longer and the junction becomes deeper.

Further, with the miniaturization, the concentration of the substrate becomes high, so that the amount of ion implantation for forming a junction increases, and as a result, the probability of occurrence of crystal defects increases.

The present invention eliminates the above-mentioned problems of occurrence of crystal defects due to impurity implantation by high-concentration ion implantation and formation of deep junction due to tail of high-concentration impurity distribution in the substrate depth direction. Therefore, the Si substrate containing impurities is annealed under conditions such as N ₂ atmosphere to diffuse the impurities in the substrate in the vicinity of the substrate surface outward to reduce the impurity concentration on the substrate surface, and thus ion implantation for forming a junction is performed. It is an object of the present invention to provide an excellent device which forms a shallow junction with a reduced amount of junction leakage as a result.

[0008]

For the above-mentioned purpose, the present invention anneals a Si substrate containing impurities as described above in an N ₂ atmosphere to diffuse impurities in the vicinity of the surface of the substrate outward, The impurity concentration is reduced.

[0009]

As described above, according to the present invention, the impurity in the vicinity of the substrate surface is diffused outward to reduce the impurity concentration, so that the amount of ion implantation for forming a junction can be reduced. As a result, it is possible to form a shallow junction with little junction leakage.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, a method of forming a buried channel counter doping layer of a buried Pch (P channel) MOSFET is shown in FIG. 1 and will be described below.

First, as shown in FIG. 1A, an NWell 2 having an N-type impurity concentration N _D = 1E17 cm ⁻³ is formed on a P-type silicon substrate 1, and an element isolation region 3 and an active element region 4 are formed by, for example, the LOCOS method. To form. The surface of the active element region 4 is washed with a hydrogen fluoride aqueous solution to remove the silicon dioxide film formed on the surface, and as shown in FIG.
Heat treatment (annealing) for 15 minutes at 900 ° C in N ₂ atmosphere
I do.

FIG. 3C shows the distribution of impurities before and after the above heat treatment. As can be seen from the figure, the NW
The impurities near the surface of ll2 (near the horizontal axis 0) are diffused outward, and the impurity concentration near the surface is lower than that before the heat treatment.

Next, as shown in FIG.
t) Ion implantation for control, for example, ion species ⁴⁹ BF ₂ ⁺ , energy 50 keV, implantation amount 3E
The counter doping layer 5 is formed using 12 [ions / cm ² ].

Next, as shown in FIG. 6E, a gate oxide film 6 having a thickness of about 12 nm is formed, and an n-type polysilicon gate electrode 7 is formed by photolithography / etching technique as shown in FIG. ..

Next, using the gate electrode 7 as a mask, ion implantation for forming a source / drain, for example, ion species ⁴⁹ BF ₂ ⁺ , energy 70 keV, implantation amount 5E15 ions / cm ² is carried out, and thereafter impurity activation is performed. Is heat-treated in an N ₂ atmosphere at 900 ° C. for about 15 minutes to form the source / drain regions 8.

As shown in FIG. 3C, since the impurity concentration near the surface of the NWell 2 is lowered, it is possible to reduce the amount of ion implantation when forming the counter-doping layer 5 to cancel this. it can.

As a result, as shown in (h), the junction depth of the counter-doping layer 5 under the channel is shallower in this embodiment as compared with the prior art, and the structure is strong against the short channel effect. ..

The method described above is of course the NchMOSF
The same can be done when creating an ET, and NchMOSF
Even when the ET is formed, the Vt value can be lowered without lowering the resistance to the short channel effect by lowering the impurity concentration near the substrate surface.

[0019]

As described above, according to the present invention,
Since the impurity in the vicinity of the Si substrate surface is diffused outward and its concentration is reduced, the ion implantation amount for forming a junction can be reduced, and as a result, a shallower junction can be formed as compared with the conventional one. The occurrence of crystal defects is also reduced,
An excellent semiconductor device with little junction leakage can be obtained.

[Brief description of drawings]

FIG. 1 is an example of the present invention.

[Explanation of symbols]

 1 P-type silicon substrate 2 N Well 3 element isolation region 4 active element region 5 counter-doping layer

Claims (1)

[Claims] 1. A semiconductor device characterized in that impurities contained at least near the surface of an active element region formed on a semiconductor substrate are diffused outward by heat treatment to reduce the impurity concentration near the surface. Manufacturing method.