JPH05190657A - Semiconductor substrate and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object of the present invention to provide a SOI structure semiconductor substrate suitable for forming an integrated circuit having a bi-CMOS structure. [Structure] Mesas having different heights are formed on the surface of a silicon wafer, and these mesas are filled with an insulating layer having a flat upper surface, and then the silicon wafer is bonded to another silicon wafer through this insulating layer. .. The back surface of the first silicon wafer is polished until the insulating layer is exposed, and the mesas are separated into islands. These island-shaped semiconductor layers have thicknesses suitable for MOS transistors and bipolar transistors, depending on the height of the initial mesas.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applied to SOI (silicon on insulat)
or) a semiconductor substrate having a structure, and particularly to a semiconductor substrate formed by bonding a silicon substrate to a supporting substrate via an insulating layer.

[0002]

2. Description of the Related Art In order to take advantage of the characteristics of low power consumption of CMOS and high driving ability of bipolar transistor, a so-called bi-CMOS structure in which a CMOS transistor and a bipolar transistor are formed on the same chip is applied to some products. ing. However, in order to take advantage of the characteristics of both types of transistors when forming a bi-CMOS structure on a substrate with an SOI structure, the thickness of the silicon layer should be set between the area where the CMOS transistor is formed and the area where the bipolar transistor is formed. Need to change. For example, in order to suppress the short channel effect of a MOS transistor, the thickness of the silicon layer of the SOI structure must be about 1000Å or less, but the collector part of the bipolar transistor cannot be formed in such a thin silicon layer. Because.

[0003]

As a method of manufacturing a substrate having an SOI structure, a method of recrystallizing a polycrystalline silicon layer deposited on a SiO ₂ layer by irradiation with an energy beam such as a laser, silicon A so-called SIMO, in which oxygen is ion-implanted into a wafer to form a SiO ₂ layer at a predetermined depth
The X method, or a method of polishing one of the two silicon wafers bonded via the SiO ₂ layer to a thickness of 10 μm or less has been proposed. But for now,
The focus is on forming a uniform silicon layer, and there is no practicable method for manufacturing an SOI substrate suitable for forming the above-mentioned bi-CMOS structure.

The present invention is based on the above bonding method,
The purpose is to be able to manufacture an SOI substrate suitable for forming a bi-CMOS structure.

[0005]

The object is to consist of a semiconductor layer formed on one surface of a supporting substrate via an insulating layer, be electrically isolated from each other, and have the same height from the insulating layer. A semiconductor substrate according to the present invention, comprising two islands having different thicknesses, wherein the periphery of each island is filled with an insulating layer having an upper surface having the same height as the upper surface, or A first mask is formed on a surface of a semiconductor substrate having an arbitrary thickness, the first mask covering the first region defined separately, and the semiconductor substrate in the region exposed from the first mask is formed on the surface. To a first depth smaller than the thickness to form a first mesa of a portion of the semiconductor substrate in the first region, the first region being defined by the first region and the etched region. A second mask covering the second region And forming a part of the semiconductor substrate by further etching the semiconductor substrate in a region exposed from the second mask from the etched surface to a second depth smaller than the first depth. And a second mesa separated from the first mesa, and an insulating layer having a thickness larger than a sum of the first depth and the second depth by a predetermined value at least in the semiconductor substrate. The first and second mesas are deposited on the surface, the insulating layer is ground flat until its thickness on the first region reaches the predetermined value, and the insulating layer is ground through the polished insulating layer. A semiconductor substrate according to the present invention, in which the semiconductor substrate is bonded to a supporting substrate, and the semiconductor substrate bonded to the supporting substrate is flatly polished from the back surface with respect to the front surface until the insulating layer is just exposed. Alternatively, the same as above Forming a first mesa and then forming a second mask of an oxidation resistant material and covering the first region and a second region defined in the etched region, The surface of the semiconductor substrate exposed from the second mask is oxidized to form an oxide film having a thickness smaller than the first depth on the surface, and a thickness larger than at least the first depth by a predetermined value. Is deposited on the surface of the semiconductor substrate on which the mesa and the oxide film are formed, and thereafter, in the same manner as above, the thickness of the insulating layer on the first region becomes the predetermined value. To a flat surface, and the semiconductor substrate is bonded to a supporting substrate through the polished insulating layer, and the semiconductor layer bonded to the supporting substrate is exposed from the back surface with respect to the front surface. Including the steps of polishing evenly up to It is accomplished by any of a semiconductor substrate manufacturing method according to the present invention to symptoms.

[0006]

Function: Mesas having different heights are formed on the surface of the semiconductor substrate, and these are filled with an insulating layer having a flat upper surface. After bonding this semiconductor substrate to the supporting substrate via the insulating layer, the back surface thereof is polished to the level of the bottom of the mesa.
In this state, each mesa becomes an island separated by the insulating layer. The thickness of the SOI structure semiconductor layer that forms these islands is equal to the height of the mesa. Therefore, a mesa having a height corresponding to a semiconductor layer having a desired thickness may be formed. It is also possible to form a selective oxide film of a predetermined thickness around the semiconductor layer having a thickness of 1000 Å or less for forming a MOS transistor and control the final thickness by the thickness of this oxide film.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of an essential part for explaining a process of one embodiment of the present invention. Arsenic (As) ions with an energy of 25 KeV and a dose of 1E16 / cm ² are implanted into the surface of the silicon substrate. As a result, a high concentration n-type region (n ⁺ ) is formed over a depth of 0.3 μm from the surface. After depositing a SiO ₂ film with a thickness of about 3000Å on the surface of this silicon substrate, the same figure (a)
As shown in FIG. 3, for example, the SiO ₂ film 2 and the silicon substrate 1 around the first element formation region in which a bipolar transistor is formed are sequentially and selectively etched to form a mesa 1A. The SiO ₂ film 2 is etched by the lithographic technique using a resist mask, and the silicon substrate 1 is etched by the SiO ₂ film 2
Etching is performed by RIE (reactive ion etching) with the mask used as a mask. The height (H ₁ ) of the mesa 1A is about 1 μm.

Then _{, as} shown in FIG. 1 (b), for example, MO
After forming the resist mask 3 covering the surface of the silicon substrate 1 in the second element formation region where the S transistor is formed, the surface of the silicon substrate 1 exposed from the SiO ₂ film 2 and the resist mask 3 is further reduced to a depth of about Anisotropically etch 0.1 μm to form mesa 1B.

The number and arrangement of the mesas 1A and 1B are arbitrary according to the intended semiconductor device. Then, after removing the SiO ₂ film 2 and the resist mask 3, as shown in FIG. 1 (c), an insulating layer 4 of about 2 μm thick made of SiO ₂ is deposited so as to fill the mesas 1A and 1B. To do. As a material for the insulating layer 4, phosphosilicate glass (PS
G), borophosphosilicate glass (BPSG), Si ₃ N ₄ or the like may be used, and it may be formed by an ordinary CVD (chemical vapor deposition) method.

Then, as shown in FIG. 1 (d), the insulating layer 4
The upper surface of the is ground flat. The height difference between the mesas 1A and 1B is 1 μm, and the height of the mesas 1B is 0.1 μm. Therefore, even if the insulating layer 4 with a thickness of about 2 μm is polished flat as described above, An insulating layer 4 of arbitrary thickness of approximately 1 μm or less can be left on it.

Next, as shown in FIG. 2 (e), the flattened insulating layer 4 is superposed on a supporting substrate 6 made of, for example, another silicon wafer, and the insulating substrate 4 is placed in a nitrogen atmosphere at 1000 ° C.
Heat treatment at ℃ for about 30 minutes. As a result, the silicon substrate 1
And the support substrate 6 are bonded. Incidentally, by applying a DC pulse of, for example, 300 V between the silicon substrate 1 and the supporting substrate 6 during this heat treatment, the adhesive strength is improved.

Then, as shown in FIG. 2 (f), the back surface of the silicon substrate 1 adhered to the support substrate 6 is replaced with the mesa 1A and
Polish until the insulating layer 4 around 1B is exposed. This polishing, for example, may be used polishing technique of the silicon wafer to the polishing agent known colloidal silica, silicon and SiO ₂
If the polishing is performed under the condition of selective polishing such that the polishing rate ratio between and is about 6, it is easy to control the end point when the insulating layer 4 is exposed. When polished as above, mesa 1A and
1B is an island buried in the insulating layer 4, the island corresponding to the mesa 1A has a thickness of about 1 μm suitable for forming a bipolar transistor, and the island corresponding to the mesa 1B is suitable for forming a MOS transistor. It has a thickness of about 0.1 μm.

FIG. 3 is a sectional view of an essential part for explaining a process of another embodiment of the present invention. As shown in FIG. 1 (a),
The surface of the silicon substrate 1 around the first element formation region masked by the SiO ₂ film 2 is etched to a height of about 1
After forming the mesa 1A of μm, the SiO ₂ film 2 is removed. Next, according to the well-known LOCOS method, as shown in FIG. 3, an oxidation resistant mask 7 made of, for example, a Si ₃ N ₄ film is formed on the first element formation region and the second element formation region, and then,
The silicon substrate 1 is, for example, 1000 ° C. in a wet oxygen atmosphere.
Heat for about 12 minutes. As a result, the surface of the silicon substrate 1 exposed from the oxidation-resistant mask 7 is thermally oxidized, and the thickness of the surface is reduced.
A 1000 Å SiO ₂ film 8 is formed. It should be noted that the SiO ₂ film 2 may be left as it is when forming the oxidation resistant mask 7.

Then, after the oxidation resistant mask 7 is selectively removed, an insulating layer 4 having a thickness of about 2 μm is deposited on the silicon substrate 1 as in FIG. 1 (c). After that, the silicon substrate 1 is adhered to the supporting substrate according to the same process as in the above embodiment, and then the back surface of the silicon substrate 1 is polished until the SiO ₂ film 8 is exposed. Thus, the thickness of the island formed in the first element formation region is the same as the height of the mesa 1A, and the thickness of the island formed in the second element formation region is the thickness of the SiO ₂ film 8. It is about 1/2 of that, or about 500 Å. in this way
If the LOCOS technology is applied, it is not necessary to etch the periphery of the second element formation region, so the controllability of the thickness is good,
This is advantageous for uniformly forming thin islands of 1000 Å or less on the entire surface of the substrate.

In the above-mentioned embodiment, the case where the semiconductor layer having the island-shaped SOI structure having two kinds of thickness is formed has been described as an example, but according to the present invention, the island having more kinds of thickness is formed. It is also possible to form a semiconductor layer.

[0016]

According to the present invention, it is possible to obtain a semiconductor substrate having an SOI structure having a plurality of island-shaped semiconductor layers having different thicknesses. These island-shaped semiconductor layers can be designed to have an arbitrary thickness and two or more types. Therefore, CMOS transistors and bipolar transistors can be integrated on a single SOI structure substrate, which has the effect of promoting the development of high-density, high-performance semiconductors that take advantage of the low power consumption and high drive capability of these transistors. is there.

[Brief description of drawings]

FIG. 1 is a process explanatory view of an embodiment of the present invention (No. 1)

FIG. 2 is a process explanatory view of an embodiment of the present invention (No. 2)

FIG. 3 is an explanatory view of another embodiment of the present invention.

[Explanation of symbols]

1 Silicon Substrate 1A, 1B Mesa 2 SiO ₂ Film 3 Resist Mask 4 Insulating Layer 6 Support Substrate 7 Oxidation Resistant Mask 8 SiO ₂ Film

Claims (4)

[Claims] 1. Two islands each of which is composed of a semiconductor layer formed on one surface of a supporting substrate via an insulating layer and is electrically separated from each other, and which is equal in height from the insulating layer and different in thickness. A semiconductor substrate characterized by being provided. 2. The semiconductor substrate according to claim 1, wherein the periphery of each of the islands is filled with an insulating layer having an upper surface at the same height as the upper surface. 3. A step of forming a first mask on a surface of a semiconductor substrate having an arbitrary thickness, the first mask covering the first area defined separately from each other, and the area exposed from the first mask. Etching the semiconductor substrate from the surface to a first depth smaller than the thickness to form a first mesa formed of a portion of the semiconductor substrate in the first region; Forming a second mask overlying a second region defined in the etched region; exposing the semiconductor substrate in a region exposed from the second mask from the etched surface to the first region; Further etching to a second depth that is less than the first depth to form a second mesa that is part of the semiconductor substrate and is separated from the first mesa, at least the first depth and the first depth. It ’s the sum of two depths. Depositing an insulating layer having a thickness larger by a predetermined value on the surface of the semiconductor substrate on which the first and second mesas are formed, and the insulating layer has a thickness on the first region A step of flatly polishing to a predetermined value, a step of adhering the semiconductor substrate to a supporting substrate via the polished insulating layer, and a step of adhering the semiconductor substrate adhered to the supporting substrate to the front surface from the back surface. And a step of polishing the insulating layer evenly until the insulating layer is exposed. 4. A step of forming a first mask on a surface of a semiconductor substrate having an arbitrary thickness, the first mask covering the first area defined separately from each other, and the area exposed from the first mask. A step of etching the semiconductor substrate from the surface to a first depth smaller than the thickness to form a mesa formed of a part of the semiconductor substrate in the first region; Forming a second mask covering the first region and a second region defined in the etched region; oxidizing the surface of the semiconductor substrate exposed from the second mask to remove the second mask; A step of forming an oxide film having a thickness smaller than the first depth on a surface, and an insulating layer having a thickness larger than the first depth by a predetermined value is formed on the semiconductor substrate by the mesa and the oxide film. Deposit on the formed surface And a step of flatly polishing the insulating layer until the thickness thereof on the first region reaches the predetermined value, and the semiconductor substrate is bonded to a supporting substrate through the polished insulating layer. And a step of polishing the semiconductor substrate bonded to the support substrate from the back surface with respect to the front surface to a flat surface until the insulating layer is just exposed.