JPH05190846A - Field-effect transistor - Google Patents
Field-effect transistorInfo
- Publication number
- JPH05190846A JPH05190846A JP2055992A JP2055992A JPH05190846A JP H05190846 A JPH05190846 A JP H05190846A JP 2055992 A JP2055992 A JP 2055992A JP 2055992 A JP2055992 A JP 2055992A JP H05190846 A JPH05190846 A JP H05190846A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alsb
- substrate
- effect transistor
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910017115 AlSb Inorganic materials 0.000 claims abstract description 19
- 239000013078 crystal Substances 0.000 claims abstract description 11
- 229910000673 Indium arsenide Inorganic materials 0.000 abstract description 6
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 229910052733 gallium Inorganic materials 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 7
- 229910005542 GaSb Inorganic materials 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 5
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【目的】 ピンチオフ特性に優れ、リーク電流が少な
く、数十ＧＨzの高周波の増幅が可能な電界効果型トラ
ンジスタを得る。
【構成】 基板１上にバッファ層２、チャネル層３、絶
縁層４を順次エピタキシャル成長し、基板１及びバッフ
ァ層２は半絶縁性ＡlＳbからなり、チャネル層３はＴe
ドープ型ＩnＡsＳbとし、特にＡlＳbと格子整合すべく
ＩnＡsＳbのＡsとＳbの原子割合はそれぞれ0.82:0.18、
即ちＩnＡs0.82Ｓb0.18とした。また、チャネル層３の
上に形成する絶縁層４はＡlＧaＳbの混晶から構成し、
Ａl及びＧaの原子割合はそれぞれ0.2:0.8、即ちＡl0.2
Ｇa0.8Ｓbとした。
(57) [Abstract] [Purpose] To obtain a field effect transistor having excellent pinch-off characteristics, a small leakage current, and capable of amplifying a high frequency of several tens GHz. [Structure] A buffer layer 2, a channel layer 3, and an insulating layer 4 are sequentially epitaxially grown on a substrate 1, the substrate 1 and the buffer layer 2 are made of semi-insulating AlSb, and the channel layer 3 is Te.
A doped InAsSb is used, and the atomic ratio of As and Sb of InAsSb is 0.82: 0.18, respectively, in order to make lattice matching with AlSb.
That is, InAs 0.82 Sb 0.18 . The insulating layer 4 formed on the channel layer 3 is made of a mixed crystal of AlGaSb,
The atomic ratio of Al and Ga is 0.2: 0.8, that is, Al 0.2
Ga 0.8 Sb.
Description
【０００１】[0001]
【産業上の利用分野】本発明は化合物半導体を用いた電
界効果型トランジスタ（ＦＥＴ）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) using a compound semiconductor.
【０００２】[0002]
【従来の技術】半導体にソース電極とドレイン電極をオ
ーミック接合し、これら電極間の電流通路の導電率をゲ
ート電極によって変化させ電流を制御する電界効果型ト
ランジスタが知られている。斯かる電界効果型トランジ
スタの半導体材料としては単一元素半導体のＳｉ，Ｓe
や化合物半導体のＧaＡsが一般的である。2. Description of the Related Art A field effect transistor is known in which a source electrode and a drain electrode are ohmic-bonded to a semiconductor, and the conductivity of a current path between these electrodes is changed by a gate electrode to control the current. As a semiconductor material of such a field effect transistor, Si or Se which is a single element semiconductor is used.
Compounds such as GaAs and compound semiconductors are generally used.
【０００３】[0003]
【発明が解決しようとする課題】上記のＳｉやＧaＡs等
よりも電子移動度及び飽和電子速度の高い化合物半導体
として、ＩnＳb、ＩnＡs及びこれらの混晶であるＩnＡs
Ｓbが知られている。因みにＧaＡsの３００Ｋにおける
電子移動度が８，５００ｃｍ2／Ｖ・ｓであるのに対し
ＩnＳbの電子移動度は７８，０００ｃｍ2／Ｖ・ｓ、Ｉn
Ａsの電子移動度は３３，０００ｃｍ2／Ｖ・ｓである。
したがって、これら化合物半導体を電界効果型トランジ
スタの材料として使用することができれば数十ＧＨzの
高周波の増幅が可能になる。As compound semiconductors having higher electron mobility and saturated electron velocity than Si, GaAs, etc., InSb, InAs, and InAs which is a mixed crystal thereof are used.
Sb is known. Incidentally, the electron mobility of GaAs at 300K is 8,500 cm 2 / V · s, whereas the electron mobility of InSb is 78,000 cm 2 / V · s, In.
The electron mobility of As is 33,000 cm 2 / V · s.
Therefore, if these compound semiconductors can be used as a material for a field effect transistor, a high frequency of several tens GHz can be amplified.
【０００４】しかしながら、上記のＩnＳb、ＩnＡs及び
これらの混晶であるＩnＡsＳbは、低抵抗の結晶しか得
られない。具体的にはＩnＳb及びＩnＡsは禁制帯幅が３
００Ｋにおいて０．３６ｅＶ以下と非常に狭いため、電
気抵抗の低い膜や基板しか得られない。このため、これ
らを基板やバッファ層とした電界効果型トランジスタは
ピンチオフ特性が悪くなる。However, the above-mentioned InSb, InAs, and InAsSb, which is a mixed crystal thereof, can obtain only low resistance crystals. Specifically, InSb and InAs have a forbidden band width of 3
Since it is very narrow at 0.36 eV or less at 00K, only a film or substrate having low electric resistance can be obtained. Therefore, the field effect transistor using these as a substrate or a buffer layer has poor pinch-off characteristics.
【０００５】また、ＩnＡsＳbについては適当なＡs組成
を選択することでＧaＳbと格子整合させることができる
ので、ＧaＳbを基板として用いることが考えられるが、
ＧaＳbについても高抵抗の結晶が得られないため、バッ
ファ層や基板として用いるには適さない。Also, since InAsSb can be lattice-matched with GaSb by selecting an appropriate As composition, it is possible to use GaSb as a substrate.
GaSb is not suitable for use as a buffer layer or a substrate, because high-resistance crystals cannot be obtained.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決すべく本
発明は、半絶縁性ＡlＳbからなる基板、若しくは基板上
に形成した半絶縁性ＡlＳbからなるバッファ層上にＡl
Ｓbと格子整合するＩnＡsＳbの混晶からなるチャネル層
を形成した。In order to solve the above-mentioned problems, the present invention provides a substrate made of semi-insulating AlSb or a buffer layer made of semi-insulating AlSb formed on the substrate.
A channel layer made of a mixed crystal of InAsSb that lattice-matches with Sb was formed.
【０００７】[0007]
【作用】基板またはバッファ層として高抵抗のＡlＳbを
用い、このＡlＳbの上にＩnＡsＳbの混晶からなるチャ
ネル層を形成するに当り、Ａsの割合を適切に選定する
ことで、ＡlＳbとＩnＡsＳbとを格子整合させることが
できる。By using AlSb having a high resistance as the substrate or the buffer layer and forming a channel layer made of a mixed crystal of InAsSb on this AlSb, by appropriately selecting the ratio of As, AlSb and InAsSb can be obtained. It can be lattice matched.
【０００８】[0008]
【実施例】以下に本発明の実施例を添付図面に基づいて
説明する。図１は本発明に係る電界効果型トランジスタ
のうちＭＩＳ型電界効果型トランジスタの断面図であ
り、この電界効果型トランジスタは、基板１上に約１μ
ｍ厚のバッファ層２、約１，０００Å厚のチャネル層
３、約１００Å厚の絶縁層４を順次エピタキシャル成長
し、チャネル層３にはソース電極５、ドレイン電極６を
接続し、絶縁層４上にはゲート電極７を設けている。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a MIS field effect transistor of the field effect transistors according to the present invention. This field effect transistor has a thickness of about 1 μm on a substrate 1.
A buffer layer 2 having a thickness of m, a channel layer 3 having a thickness of about 1,000 Å, and an insulating layer 4 having a thickness of about 100 Å are sequentially epitaxially grown. Is provided with a gate electrode 7.
【０００９】基板１及びバッファ層２は半絶縁性ＡlＳb
からなり、チャネル層３はＴeドープ型ＩnＡsＳbとし、
特にＡlＳbと格子整合すべくＩnＡsＳbのＡsとＳbの原
子割合はそれぞれ0.82:0.18、即ちＩnＡs0.82Ｓb0.18と
した。また、チャネル層３の上に形成する絶縁層４はＡ
lＧaＳbの混晶から構成し、Ａl及びＧa原子割合はそれ
ぞれ0.2:0.8、即ちＡl0.2Ｇa0.8Ｓbとした。The substrate 1 and the buffer layer 2 are semi-insulating AlSb.
And the channel layer 3 is Te-doped InAsSb,
In particular, the atomic ratios of As and Sb in InAsSb were 0.82: 0.18, that is, InAs 0.82 Sb 0.18 , so as to be lattice-matched with AlSb. The insulating layer 4 formed on the channel layer 3 is A
composed of a mixed crystal of LGaSb, respectively Al and Ga atomic ratio is 0.2: 0.8, i.e. the Al 0.2 Ga 0.8 Sb.
【００１０】図２は本発明に係る電界効果型トランジス
タのうちＭＯＳ型電界効果型トランジスタの断面図であ
り、この電界効果型トランジスタは、約９００Å厚のチ
ャネル層３の上に前記絶縁層４に代えて約２００Å厚の
ＩnＡsＳb酸化層８を形成している。FIG. 2 is a cross-sectional view of a MOS field effect transistor of the field effect transistors according to the present invention. The field effect transistor is formed on the channel layer 3 having a thickness of about 900 Å and the insulating layer 4 formed thereon. Instead, an InAsSb oxide layer 8 having a thickness of about 200Å is formed.
【００１１】ここで、前記絶縁層４及び酸化層８として
は、ＳｉＮX，ＳiＯ2を形成してもよく、また高抵抗の
ＡlＳbからなるバッファ層２を設ける場合には基板１に
ついては低抵抗であってもある程度の特性は得られるの
で、ＡlＳbと格子定数がほぼ等しいＧaＳbを基板材料と
してもよく、更にＡlＳbからなる基板１が十分に高純度
の場合にはバッファ層２を設けなくてもよい。Here, SiN x , SiO 2 may be formed as the insulating layer 4 and the oxide layer 8. When the buffer layer 2 made of AlSb having a high resistance is provided, the substrate 1 has a low resistance. However, since a certain degree of characteristics can be obtained, GaSb having a lattice constant substantially equal to that of AlSb may be used as the substrate material. Further, when the substrate 1 made of AlSb is sufficiently high in purity, the buffer layer 2 may be omitted. Good.
【００１２】尚、以上においてＡlＳbからなる基板１に
ついては、引上げ法により製造されたアンドープ、比抵
抗１０9Ωcmのもとし、ＧaＳb基板はボート法により製
造されるｎ型で抵抗１Ωcm以下のもとし、ＡlＳb層、Ｉ
nＡsＳb層、ＡlＧaＳb層はいずれも有機金属気相成長法
にて形成した。In the above description, the substrate 1 made of AlSb has an undoped specific resistance of 10 9 Ωcm manufactured by the pulling method, and the GaSb substrate has an n-type resistance of 1 Ωcm or less manufactured by the boat method. , AlSb layer, I
Both the nAsSb layer and the AlGaSb layer were formed by metalorganic vapor phase epitaxy.
【００１３】[0013]
【発明の効果】以下の（表１）は本発明品（Ａは図１に
示したもの、Ｂは図２に示したもの）と従来品のピンチ
オフ特性とリーク電流の関係を示すグラフである。The following (Table 1) is a graph showing the relationship between the pinch-off characteristic and the leakage current of the product of the present invention (A is shown in FIG. 1 and B is shown in FIG. 2) and the conventional product. ..
【００１４】[0014]
【表１】 [Table 1]
【００１５】上記の（表１）からも明らかなように本発
明の電界効果型トランジスタは、基板またはバッファ層
をＡlＳbとし、チャネル層を前記ＡlＳbと格子整合する
ＩnＡsＳbの混晶にて構成したので、ピンチオフ特性に
優れ、リーク電流が少なく、数１０ＧＨzの高周波の増
幅が可能な高性能の電界効果型トランジスタを得ること
ができる。As is clear from the above (Table 1), the field-effect transistor of the present invention comprises AlSb as the substrate or the buffer layer and the InAsSb mixed crystal lattice-matched with the AlSb as the channel layer. It is possible to obtain a high-performance field-effect transistor which has excellent pinch-off characteristics, has a small leak current, and can amplify a high frequency of several tens GHz.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明に係る電界効果型トランジスタの断面図FIG. 1 is a sectional view of a field effect transistor according to the present invention.
【図２】別実施例に係る電界効果型トランジスタの断面
図FIG. 2 is a sectional view of a field effect transistor according to another embodiment.
１…基板、２…バッファ層、３…チャネル層、４…絶縁
層、５…ソース電極、６…ドレイン電極、７…ゲート電
極、８…酸化層。1 ... Substrate, 2 ... Buffer layer, 3 ... Channel layer, 4 ... Insulating layer, 5 ... Source electrode, 6 ... Drain electrode, 7 ... Gate electrode, 8 ... Oxide layer.
Claims (2)
は基板上に形成した半絶縁性ＡlＳbからなるバッファ層
上にＡlＳbと格子整合するＩnＡsＳbの混晶からなるチ
ャネル層を形成したことを特徴とする電界効果型トラン
ジスタ。1. A channel layer made of a mixed crystal of InAsSb lattice-matched with AlSb is formed on a substrate made of semi-insulating AlSb or on a buffer layer made of semi-insulating AlSb formed on the substrate. Field effect transistor.
晶からなるチャネル層上に絶縁層または酸化層を形成
し、この絶縁層または酸化層の上にゲート電極を設けた
ＭＩＳ型またはＭＯＳ型の電界効果型トランジスタ。2. The MIS-type or MOS-type device according to claim 1, wherein an insulating layer or an oxide layer is formed on the channel layer made of the mixed crystal of InAsSb, and a gate electrode is provided on the insulating layer or the oxide layer. Field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2055992A JPH05190846A (en) | 1992-01-09 | 1992-01-09 | Field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2055992A JPH05190846A (en) | 1992-01-09 | 1992-01-09 | Field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05190846A true JPH05190846A (en) | 1993-07-30 |
Family
ID=12030520
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2055992A Withdrawn JPH05190846A (en) | 1992-01-09 | 1992-01-09 | Field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05190846A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100345516B1 (en) * | 2000-09-05 | 2002-07-24 | 아남반도체 주식회사 | Radio frequency integrated circuit device and manufacturing method thereof |
| US20100264459A1 (en) * | 2003-09-09 | 2010-10-21 | Asahi Kasei Kabushiki Kaisha | Infrared sensor IC, and infrared sensor and manufacturing method thereof |
-
1992
- 1992-01-09 JP JP2055992A patent/JPH05190846A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100345516B1 (en) * | 2000-09-05 | 2002-07-24 | 아남반도체 주식회사 | Radio frequency integrated circuit device and manufacturing method thereof |
| US20100264459A1 (en) * | 2003-09-09 | 2010-10-21 | Asahi Kasei Kabushiki Kaisha | Infrared sensor IC, and infrared sensor and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990408 |