JPH05190896A - Led array and manufacture thereof - Google Patents

Led array and manufacture thereof

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Publication number
JPH05190896A
JPH05190896A JP655892A JP655892A JPH05190896A JP H05190896 A JPH05190896 A JP H05190896A JP 655892 A JP655892 A JP 655892A JP 655892 A JP655892 A JP 655892A JP H05190896 A JPH05190896 A JP H05190896A
Authority
JP
Japan
Prior art keywords
led
directions
cleavage
array
led chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP655892A
Other languages
Japanese (ja)
Inventor
Munekazu Tsujikawa
宗和 辻川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP655892A priority Critical patent/JPH05190896A/en
Publication of JPH05190896A publication Critical patent/JPH05190896A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide a LED array with less generation of a faulty LED chip due to crack and chipping at the time of cutting and less damage to a LED element at the time of cutting and a method for manufacturing the LED array. CONSTITUTION:A LED array is constituted by providing LED elements C1-C64 (or C128) which are aligned in <010> and <0-10> directions in a crystal face (100) and at the same time aligning a LED chip 1 with cut cleavage planes (010), (00-1), (0-10), and (001) in a row in <010> and <0-10> directions.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、プリンタ、プロッタ、
ファクシミリ、ＬＥＤプリントヘッド、光学的文字書き
込み装置等に搭載されるＬＥＤヘッド用のＬＥＤアレ
イ、並びにその製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a printer, plotter,
The present invention relates to an LED array for an LED head mounted on a facsimile, an LED print head, an optical character writing device, etc., and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】一般にＬＥＤヘッドは、ＬＥＤチップを
アレイ状に配したＬＥＤアレイを備え、更にＬＥＤチッ
プは一列に配置した多数のＬＥＤ素子を有する。通常、
ＬＥＤチップは、結晶面（１００）にＬＥＤ素子を集積
したウエハからダイシングやスクライビング等により切
断される。分離されたＬＥＤチップを図５に示す。図５
からも分かるように、ＬＥＤチップ１０には、所定のド
ット数に応じて、通常は６４（又は１２８）個のＬＥＤ
素子Ｃ1 〜Ｃ64が一列に配置され、このようなＬＥＤチ
ップ１０を更に基板上に一列に配することでＬＥＤアレ
イが構成される。2. Description of the Related Art Generally, an LED head has an LED array in which LED chips are arranged in an array, and the LED chips each have a large number of LED elements arranged in a line. Normal,
The LED chip is cut from the wafer in which the LED elements are integrated on the crystal plane (100) by dicing, scribing, or the like. The separated LED chip is shown in FIG. Figure 5
As can be seen from the figure, the LED chip 10 usually has 64 (or 128) LEDs depending on the predetermined number of dots.
The elements C 1 to C 64 are arranged in a row, and the LED chip 10 is further arranged in a row on the substrate to form an LED array.

【０００３】ところで、図５に示すように、ＬＥＤ素子
列の両端に在るＬＥＤ素子Ｃ1 、Ｃ 64は切断面に最も近
い部分に位置するため、その切断面がチッピングの少な
い劈開面（０）、（０１１）となるように、その劈
開面に垂直な方向である劈開方向＜０１１＞及び＜０
＞にＬＥＤ素子を配列することが試みられている（実
開昭６３−１００８６０号公報参照）。By the way, as shown in FIG.
LED elements C on both ends of the row1, C 64Is closest to the cut surface
Since it is located in a large area, its cut surface has less chipping.
The cleavage planes (0) and (011)
Cleavage direction <011> and <0 which is a direction perpendicular to the open surface
It has been attempted to arrange LED elements in
(See Japanese Laid-Open Patent Publication No. 63-100860).

【０００４】[0004]

【発明が解決しようとする課題】このようにＬＥＤ素子
を集積したＬＥＤチップ１０は、図６に示すように、フ
ァセットを劈開面（０１）とし、上面を結晶面（１０
０）とするウエハ２０に作製された後、＜０１＞及び
＜０１＞方向に平行に、且つ＜０１１＞及び＜０
＞方向に平行に切断され、ウエハ２０から切り離され
る。分離されたＬＥＤチップ１０の切断面は（０１
）、（０１１）、（０１）、（０）となる。In the LED chip 10 in which the LED elements are integrated in this way, as shown in FIG. 6, the facet is the cleavage plane (01) and the upper surface is the crystal plane (10).
0) is formed on the wafer 20 and then parallel to the <01> and <01> directions and <011> and <0.
It is cut in parallel with the> direction and separated from the wafer 20. The cut surface of the separated LED chip 10 is (01
), (011), (01), and (0).

【０００５】しかしながら、（０１１）、（０）に
垂直な面（０１）、（０１）はチッピングが発生し
易い性質を持つため、切断時にこれらの面（０１）、
（０１）からＬＥＤ素子Ｃ1 〜Ｃ64やその他の機能部
分に欠損、チッピングが達して、不良ＬＥＤチップとな
る可能性が高い。更には、切断時にＬＥＤ素子Ｃ1 〜Ｃ
64にダメージを与えることが多い。However, since the planes (01) and (01) perpendicular to (011) and (0) have a property that chipping is likely to occur, these planes (01) and (01) are easily cut.
There is a high possibility that the LED elements C 1 to C 64 and other functional portions will be defective or chipped from (01), resulting in a defective LED chip. Furthermore, at the time of disconnection, the LED elements C 1 to C
Often damages 64 .

【０００６】従って、本発明の目的は、切断時に起こる
欠損やチッピングによる不良ＬＥＤチップの発生、及び
切断時におけるＬＥＤ素子へのダメージが少ないＬＥＤ
アレイ、並びにそのＬＥＤアレイを製造する方法を提供
することにある。Therefore, an object of the present invention is to produce a defective LED chip due to chipping or chipping that occurs during cutting, and to reduce damage to the LED element during cutting.
It is to provide an array and a method of manufacturing the LED array.

【０００７】[0007]

【課題を解決するための手段】前記目的を達成するため
に、本発明のＬＥＤアレイは、結晶面（１００）におい
て＜０１０＞及び＜００＞方向又は＜００１＞及び＜
００＞方向に平行に配列されたＬＥＤ素子を有すると
共に、切断劈開面（０１０）、（００）、（０
０）、（００１）を持つＬＥＤチップを、＜０１０＞及
び＜００＞方向又は＜００１＞及び＜００＞方向に
一列に配してなることを特徴とする。In order to achieve the above object, the LED array of the present invention has a <010> and <00> directions or <001> and <001> in a crystal plane (100).
In addition to having the LED elements arranged parallel to the 00> direction, the cleavage planes (010), (00), (0
The LED chips having 0) and (001) are arranged in a line in the <010> and <00> directions or in the <001> and <00> directions.

【０００８】本発明のＬＥＤアレイにおけるＬＥＤチッ
プは、切断による劈開面が（０１０）、（００）、
（００）、（００１）であり、これらの劈開面はいず
れもチッピングが生じ難い性質を持つため、ダイシング
やスクライビング等による切断時に欠損やチッピングが
起こり難く、不良ＬＥＤチップの発生が減少すると共
に、切断時におけるＬＥＤ素子へのダメージも低減す
る。The LED chips in the LED array of the present invention have cleavage planes (010), (00),
(00) and (001), and all of these cleavage planes have a property that chipping is unlikely to occur, so that chipping or chipping is unlikely to occur during cutting by dicing or scribing, and the number of defective LED chips is reduced. Damage to the LED element during cutting is also reduced.

【０００９】又、本発明のＬＥＤアレイの製造方法は、
ウエハの結晶面（１００）にＬＥＤ素子を＜０１０＞及
び＜００＞方向又は＜００１＞及び＜００＞方向に
平行に配列し、このＬＥＤ素子列を＜０１０＞及び＜０
０＞方向に平行に、且つ＜００１＞及び＜００＞方
向に平行に切断して、ウエハからＬＥＤチップを分離
し、このＬＥＤチップを＜０１０＞及び＜００＞方向
又は＜００１＞及び＜００＞方向に一列に配すること
を特徴とする。この製造方法により、前記不良ＬＥＤチ
ップの発生、及びＬＥＤ素子へのダメージが少ないＬＥ
Ｄアレイが得られる。The LED array manufacturing method of the present invention is
LED elements are arranged parallel to the <010> and <00> directions or <001> and <00> directions on the crystal plane (100) of the wafer, and the LED element rows are arranged in <010> and <0>.
The LED chip is separated from the wafer by cutting in parallel with the 0> direction and parallel with the <001> and <00> directions, and the LED chip is cut in the <010> and <00> directions or <001> and <00. It is characterized in that they are arranged in a line in the> direction. With this manufacturing method, LE with less occurrence of the defective LED chip and less damage to the LED element
A D array is obtained.

【００１０】[0010]

【実施例】以下、本発明のＬＥＤアレイ及びその製造方
法を実施例に基づいて説明する。図１は一実施例のＬＥ
ＤアレイにおけるＬＥＤチップを示す。このＬＥＤチッ
プ１は、結晶面（１００）において＜０１０＞及び＜０
０＞方向に平行に配列されたＬＥＤ素子Ｃ1 〜Ｃ
64（又はＣ128 ）を有し、切断劈開面（０１０）、（０
０）、（００）、（００１）を持つものである。図
１から分かるように、劈開方向＜００１＞に垂直な面が
劈開面（０１０）、同様に劈開方向＜００＞に垂直な
面が劈開面（００）、劈開方向＜００＞に垂直な面
が劈開面（００）、劈開方向＜０１０＞に垂直な面が
劈開面（００１）になっている。EXAMPLES The LED array of the present invention and the method for manufacturing the same will be described below with reference to examples. FIG. 1 shows an LE according to an embodiment.
2 shows an LED chip in a D array. This LED chip 1 has <010> and <0> in the crystal plane (100).
LED elements C 1 to C arranged parallel to the 0> direction
64 (or C 128 ) and the cleavage planes (010), (0
It has 0), (00), and (001). As can be seen from FIG. 1, a plane perpendicular to the cleavage direction <001> is a cleavage plane (010), a plane perpendicular to the cleavage direction <00> is also a cleavage plane (00), and a plane perpendicular to the cleavage direction <00>. Is the cleavage plane (00), and the plane perpendicular to the cleavage direction <010> is the cleavage plane (001).

【００１１】これらの劈開面は、前述の従来例における
劈開面（０１１）、（０）と同様に、全てチッピン
グが起き難い性質を有する面であるため、劈開面（００
）、（００１）に近接するＬＥＤ素子Ｃ1 、Ｃ64に
は、欠けやチッピングが殆ど生じない。又、劈開方向＜
０１０＞及び＜００＞と劈開方向＜００１＞及び＜０
０＞に平行に切断するため、切断時にＬＥＤ素子に与
えるダメージは極少である。Like the cleavage planes (011) and (0) in the above-mentioned conventional example, all of these cleavage planes have the property that chipping hardly occurs, so that the cleavage plane (00
) And (001), the LED elements C 1 and C 64 are hardly chipped or chipped. Also, the cleavage direction <
010> and <00> and cleavage directions <001> and <0
Since the cutting is performed in parallel with 0>, the damage given to the LED element at the time of cutting is minimal.

【００１２】上記ＬＥＤチップ１を製造するには、図２
において、まず、上面を結晶面（１００）とし、ファセ
ットを劈開面（０１）とするウエハ２の結晶面（１０
０）に対して、常套手段にて選択拡散、素子分離及び電
極形成を行い、結晶面（１００）上に＜０１０＞及び＜
００＞方向に平行に配されたＬＥＤ素子を作製する。
図２には特に示していないが、ＬＥＤ素子は実際にはウ
エハ２上に等ピッチで集積される。To manufacture the LED chip 1 described above, the process shown in FIG.
First, the crystal plane (10) of the wafer 2 whose upper surface is the crystal plane (100) and whose facet is the cleavage plane (01).
0) is subjected to selective diffusion, element isolation and electrode formation by conventional means, and <010> and <<> are formed on the crystal plane (100).
The LED elements arranged parallel to the 00> direction are manufactured.
Although not specifically shown in FIG. 2, the LED elements are actually integrated on the wafer 2 at an equal pitch.

【００１３】ここで、ＬＥＤ素子の配列方向となる＜０
１０＞及び＜００＞方向は、図６に示す従来の製造方
法における配列方向＜０１１＞及び＜０＞に対して
４５°の角度をなす。次に、このＬＥＤ素子列を所定ド
ット数に応じて６４個（又は１２８個）分だけ一まとめ
にして切断するために、ダイシングやスクライビング等
によって、ＬＥＤ素子の配列方向＜０１０＞及び＜０
０＞と、この方向に垂直な方向＜００１＞及び＜００
＞とに平行に切断する。図２にはこの時の状態を模式的
に示してあり、切断によりＬＥＤチップ１がウエハ２か
ら分離される。実際には、このようなＬＥＤチップ１が
ウエハ２から多数切り離される。切断の結果、ＬＥＤチ
ップ１の切断劈開面は（０１０）、（００）、（０
０）、（００１）となる。Here, <0, which is the arrangement direction of the LED elements.
The 10> and <00> directions form an angle of 45 ° with the arrangement directions <011> and <0> in the conventional manufacturing method shown in FIG. Next, in order to collectively cut this LED element row by 64 (or 128) according to the predetermined number of dots, the LED element array directions <010> and <0> are set by dicing or scribing.
0> and directions <001> and <00 perpendicular to this direction.
Cut parallel to> and. FIG. 2 schematically shows the state at this time, and the LED chip 1 is separated from the wafer 2 by cutting. In reality, a large number of such LED chips 1 are separated from the wafer 2. As a result of cutting, the cleavage planes of the LED chip 1 are (010), (00), (0
0) and (001).

【００１４】その後、得られたＬＥＤチップの劈開面
（００１）と、別のチップの劈開面（００）とが当接
するように、各ＬＥＤチップ１を所定の基板上にダイボ
ンディングすることにより、各ＬＥＤチップ１のＬＥＤ
素子Ｃ1 〜Ｃ64が＜０１０＞及び＜００＞方向に一列
に並んだＬＥＤアレイが完成する。図３に別実施例のＬ
ＥＤアレイにおけるＬＥＤチップを示す。このＬＥＤチ
ップ３は、ＬＥＤ素子Ｃ1 〜Ｃ64（又はＣ128 ）が劈開
方向＜００＞及び＜０１０＞に垂直な方向の劈開方向
＜００１＞及び＜００＞に平行に配されたものであ
る。４つの劈開面は、上記実施例と同様に（００）、
（００）、（００１）、（０１０）であり、劈開面
（００）にＬＥＤ素子Ｃ1 が、劈開面（０１０）にＬ
ＥＤ素子Ｃ64が近接する。このＬＥＤチップ３でも、劈
開面が上記実施例と同じであり、前記と同等の効果が得
られる。After that, each LED chip 1 is die-bonded onto a predetermined substrate so that the cleavage surface (001) of the obtained LED chip and the cleavage surface (00) of another chip contact each other. LED of each LED chip 1
An LED array in which the elements C 1 to C 64 are aligned in the <010> and <00> directions is completed. FIG. 3 shows another embodiment of L
2 shows an LED chip in an ED array. In this LED chip 3, LED elements C 1 to C 64 (or C 128 ) are arranged in parallel with the cleavage directions <001> and <00> perpendicular to the cleavage directions <00> and <010>. is there. The four cleavage planes are (00), as in the above embodiment.
(00), (001), and (010), and the LED element C 1 is on the cleavage plane (00) and L is on the cleavage plane (010).
The ED element C 64 approaches. Also in this LED chip 3, the cleavage plane is the same as that of the above-mentioned embodiment, and the same effect as the above can be obtained.

【００１５】ＬＥＤチップ３の製造方法では、図４に示
すように、まず、ウエハ４の結晶面（１００）にＬＥＤ
素子を＜００１＞及び＜００＞方向に平行に作製す
る。＜００１＞及び＜００＞方向は、先の実施例にお
けるＬＥＤ素子の配列方向＜００＞及び＜０１０＞に
垂直であり、且つ図６に示す従来の製造方法における配
列方向＜０１１＞及び＜０＞とは４５°の角度をな
す。In the method of manufacturing the LED chip 3, as shown in FIG. 4, first, the LED is formed on the crystal plane (100) of the wafer 4.
The device is manufactured parallel to the <001> and <00> directions. The <001> and <00> directions are perpendicular to the LED element array directions <00> and <010> in the previous embodiment, and the array directions <011> and <0 in the conventional manufacturing method shown in FIG. > Forms an angle of 45 °.

【００１６】次いで、ダイシングやスクライビング等に
よって、ＬＥＤ素子の配列方向＜００１＞及び＜００
＞と、この方向に垂直な方向＜００＞及び＜０１０＞
とに平行に切断し、ＬＥＤチップ３を得る。その後、分
離されたＬＥＤチップ３を、劈開面（０１０）と（０
０）が当接するように、基板上にダイボンディングし、
ＬＥＤアレイを作製する。Then, by dicing, scribing, or the like, the LED element array directions <001> and <00> are formed.
>, And directions <00> and <010> perpendicular to this direction.
The LED chip 3 is obtained by cutting in parallel with and. Then, the separated LED chips 3 are separated from the cleavage planes (010) and (0
Die bonding on the substrate so that
Create an LED array.

【００１７】[0017]

【発明の効果】本発明のＬＥＤアレイ及びその製造方法
は、以上説明したように構成されるため、下記の効果を
奏する。 （１）ウエハからＬＥＤチップを切断する時に欠損やチ
ッピングが起こり難く、不良ＬＥＤチップの発生が減少
する。 （２）切断時にＬＥＤ素子に与えるダメージが少なく、
ＬＥＤ素子の性能劣化が防止される。 （３）設計上、ＬＥＤ素子の配列方向の幅を狭くしたＬ
ＥＤチップを得ることができ、結果的にＬＥＤアレイの
小型化が可能となる。 （４）不良ＬＥＤチップが少なくなるため、より歩留り
の高い生産を行うことができ、ＬＥＤヘッドの構成部品
中で最も高価なＬＥＤアレイのコストが削減される。The LED array and the method for manufacturing the same according to the present invention are configured as described above, and therefore have the following effects. (1) When the LED chips are cut from the wafer, chipping or chipping is less likely to occur, and the number of defective LED chips is reduced. (2) Less damage to the LED element when cutting,
Performance deterioration of the LED element is prevented. (3) By design, the width of the LED elements in the array direction is narrowed to L
An ED chip can be obtained, and as a result, the LED array can be downsized. (4) Since the number of defective LED chips is reduced, production with a higher yield can be performed, and the cost of the most expensive LED array among the components of the LED head is reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例のＬＥＤアレイにおけるＬＥ
Ｄチップの概略斜視図である。FIG. 1 is an LE in an LED array according to an embodiment of the present invention.
It is a schematic perspective view of a D chip.

【図２】図１に示すＬＥＤチップを得るための製造方法
を示すウエハの概略斜視図である。2 is a schematic perspective view of a wafer showing a manufacturing method for obtaining the LED chip shown in FIG. 1. FIG.

【図３】本発明の別実施例のＬＥＤアレイにおけるＬＥ
Ｄチップの概略斜視図である。FIG. 3 is an LE in an LED array according to another embodiment of the present invention.
It is a schematic perspective view of a D chip.

【図４】図３に示すＬＥＤチップを得るための製造方法
を示すウエハの概略斜視図である。FIG. 4 is a schematic perspective view of a wafer showing a manufacturing method for obtaining the LED chip shown in FIG.

【図５】従来例のＬＥＤアレイにおけるＬＥＤチップの
概略斜視図である。FIG. 5 is a schematic perspective view of an LED chip in a conventional LED array.

【図６】図５に示すＬＥＤチップを得るための製造方法
を示すウエハの概略斜視図である。6 is a schematic perspective view of a wafer showing a manufacturing method for obtaining the LED chip shown in FIG.

【符号の説明】[Explanation of symbols]

１、３ ＬＥＤチップ ２、４ ウエハ （０１０）、（００） 劈開面 （００）、（００１） 劈開面 ＜００１＞、＜００＞ 劈開方向 ＜００＞、＜０１０＞ 劈開方向 （１００） 結晶面 （０１） ファセット 1, 3 LED chips 2, 4 Wafer (010), (00) Cleavage plane (00), (001) Cleavage plane <001>, <00> Cleavage direction <00>, <010> Cleavage direction (100) Crystal plane (01) Facet

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】結晶面（１００）において＜０１０＞及び
＜００＞方向又は＜００１＞及び＜００＞方向に平
行に配列されたＬＥＤ素子を有すると共に、切断劈開面
（０１０）、（００）、（００）、（００１）を持
つＬＥＤチップを、＜０１０＞及び＜００＞方向又は
＜００１＞及び＜００＞方向に一列に配してなること
を特徴とするＬＥＤアレイ。1. A crystal plane (100) has LED elements arranged in parallel with <010> and <00> directions or <001> and <00> directions, and has cleavage planes (010), (00). , (00), (001) are arranged in a line in the <010> and <00> directions or the <001> and <00> directions. 【請求項２】ウエハの結晶面（１００）にＬＥＤ素子を
＜０１０＞及び＜００＞方向又は＜００１＞及び＜０
０＞方向に平行に配列し、このＬＥＤ素子列を＜０１
０＞及び＜００＞方向に平行に、且つ＜００１＞及び
＜００＞方向に平行に切断して、ウエハからＬＥＤチ
ップを分離し、このＬＥＤチップを＜０１０＞及び＜０
０＞方向又は＜００１＞及び＜００＞方向に一列に
配することを特徴とするＬＥＤアレイの製造方法。2. LED elements are provided on a crystal plane (100) of a wafer in <010> and <00> directions or <001> and <0.
They are arranged parallel to the 0> direction, and this LED element row is
The LED chips are separated from the wafer by cutting in parallel with the <0> and <00> directions and parallel with the <001> and <00> directions, and the LED chips are <010> and <0>.
A method for manufacturing an LED array, wherein the LED arrays are arranged in a line in the 0> direction or the <001> and <00> directions.
JP655892A 1992-01-17 1992-01-17 Led array and manufacture thereof Pending JPH05190896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP655892A JPH05190896A (en) 1992-01-17 1992-01-17 Led array and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP655892A JPH05190896A (en) 1992-01-17 1992-01-17 Led array and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05190896A true JPH05190896A (en) 1993-07-30

Family

ID=11641664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP655892A Pending JPH05190896A (en) 1992-01-17 1992-01-17 Led array and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05190896A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7579205B2 (en) 2004-04-27 2009-08-25 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
US7663151B2 (en) 2004-04-27 2010-02-16 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
CN102157651A (en) * 2010-01-11 2011-08-17 Lg伊诺特有限公司 Light emitting device, method of manufacturing light emitting device, light emitting device package, and lighting system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7579205B2 (en) 2004-04-27 2009-08-25 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
US7663151B2 (en) 2004-04-27 2010-02-16 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
CN102157651A (en) * 2010-01-11 2011-08-17 Lg伊诺特有限公司 Light emitting device, method of manufacturing light emitting device, light emitting device package, and lighting system
US8008685B2 (en) 2010-01-11 2011-08-30 Lg Innotek Co., Ltd. Light emitting device, method of manufacturing light emitting device, light emitting device package, and lighting system

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