JPH05191802A - Integrated circuit and picture transmisson method using it - Google Patents

Abstract

(57) [Abstract] [Object] The present invention provides an integrated circuit for downsizing and efficient transmission of a still image transmission device. [Structure] A processor for compressing and expanding still image data, an interface for communicating with an externally connected processor, and an external device for connecting a memory for storing a program such as compression and expansion of still image data. Bus interface, built-in ROM for storing basic control program of processor, built-in high-speed RAM for storing program and data, image memory interface for external connection, image memory interface for controlling AD converter and DA converter, synchronization It is composed of a synchronization unit that synchronizes with the signal. With the integrated circuit according to the present invention, it is possible to reduce the size of the image transmission device and increase the transmission efficiency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image transmission apparatus, which is useful for controlling an image memory, an AD converter, a DA converter, image processing such as compression / expansion of still image data, and generation of a display control signal. Regarding the circuit.

[0002]

2. Description of the Related Art A conventional still image transmission apparatus requires a high performance processor for compression / expansion processing of a large amount of data and control of the entire apparatus. Alternatively, it has a dedicated circuit or dedicated integrated circuit for data compression / decompression. Also,
The control of the image memory, the AD converter and the DA converter and the generation of the display control signal are mainly constituted by a standard integrated circuit. The device having such a configuration has a complicated circuit, a large number of parts, and a large housing.

In the conventional still image apparatus, it was not possible to divide n still images into the image memory and to form one still image. Therefore, in order to form an n-divided screen, there is only means for transmitting a still image n times to another still image transmission device and reproducing the data sent as an n-divided screen on the receiving side.

[0004]

Conventionally, a high-performance processor or a dedicated integrated circuit is required to perform compression / expansion processing of still image data, and control or display of an image memory, an AD converter or a DA converter is required. Since the control signal is mainly generated by a standard integrated circuit, the circuit configuration of the still image device is complicated and the device cannot be downsized. Further, since the reduction image cannot be captured when capturing the still image, the n-th
There is a problem that the efficiency of still image transmission is low in the reproduction of the split screen.

Therefore, according to the present invention, image processing such as compression / expansion processing of still image data, image memory, AD converter, D
By providing an integrated circuit for controlling the A converter, synchronizing with a synchronizing signal, and generating a display control signal, the number of parts is reduced and the load on the processor for controlling the entire still image transmission apparatus is reduced to simplify the circuit configuration. It is an object to contribute to downsizing of a still image device and efficient still image transmission.

[0006]

The present invention achieves the above-mentioned object, and a circuit for taking in the image data obtained by AD-converting an image signal as a still image in an image memory and transmitting it by a subscriber telephone line or receiving this signal. In an integrated circuit that constitutes a circuit for reproducing a still image, a processor for performing compression / expansion processing of still image data, an external processor interface for exchanging data with a processor external to the integrated circuit, and the compression / expansion processing An external bus interface with an external memory for storing programs and data, a RAM and a ROM for storing image data, programs and data, and an image memory interface for controlling external image memories, AD converters and DA converters , And a synchronous circuit section to form an integrated circuit.

[0007]

As shown in FIG. 1, an integrated circuit 1 for a still image transmission apparatus according to the present invention includes an external memory 3, an AD converter 5, a DA converter 6, an image memory 4, an external processor 2, a sync separation circuit and a display control circuit. Connect 7. The processor 11 executes programs stored in the external memory 3, the built-in ROM 15, and the built-in high-speed RAM 14, communicates with the external processor 2 via the external processor interface 12, controls the image memory interface 16 and compresses and expands image data. Image processing and image memory 4 and built-in high-speed RAM 14
And data transfer between the external memory 3 and the external processor 2. The processor 11 refers to data or programs on the external memory 3 via the external bus interface 13 or stores data in the external memory 3.

The image memory interface 16 controls the flow of image data under the control of the processor 11. By this control, the image data from the AD converter 5 is output to the DA converter (display of the input image) and the image data from the AD converter 5 is written into the image memory 4 (capture of still image). The still image data is output to the DA converter (still image display). Further, the image memory interface 16 is the image memory 4 of the processor 11.
Access to and mediation of image memory refresh. The synchronization section 17 controls the image memory interface 16 in synchronization with the synchronization signal from the synchronization separation circuit 7 and generates a display control signal. When the synchronizing signal is not input, this is generated inside the synchronizing unit 17.

[0009]

[Table 1]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a processor 11 accepts commands shown in Table 1 from an external processor 2.
Programs of the processor 11 for these commands are stored in the built-in ROM 15 or the external memory 3.
To execute image processing at high speed, the processor 11 operates at a clock that is considerably faster than the access time of the external memory 3. However, when the processor 11 directly executes a program in the external memory 3, the processing is external. The memory access time is rate-determining and high-speed processing cannot be realized. If all programs and data are stored in the built-in ROM 15, high-speed processing can be realized because the access time is short, but a huge ROM is required inside the integrated circuit, which increases the size of the integrated circuit. There is a drawback that it is not possible.

Therefore, the program is stored in the built-in ROM 1 based on the contents of processing performed by the processor, the required processing speed, the changeability of the program, and the program size.
5 or the external memory 3. In addition, built-in ROM
An instruction code transfer program is arranged on 15. When the command issued by the external processor 2 is in the built-in ROM 15, the processor 11 directly executes the program. When the external processor 2 issues a command in which the program exists in the external memory 3, the processor 11 executes the instruction code transfer program as shown in FIG. 3 and stores the program in the external memory corresponding to the command at a high speed. After the transfer, the processor 11 executes the program on the built-in high-speed RAM.
As described above, it is possible to prevent the processing speed from being lowered due to the access to the external memory 3, realize the ease of changing the program, and suppress the increase in the area of the integrated circuit.

When the processor 11 executes the "CMP" command in Table 1, the processing is performed in the following order. a Obtain data of the screen area from the external processor interface 12. b Built-in corresponding program from external memory 3 High speed R
Transfer to AM14. c Read the data in the specified area from the image memory 4. The data read at d c is compressed. e When the compressed data is complete, set the compressed data in the external processor interface. If there is not enough data, return to c. f Wait until the external processor 2 receives data from the external processor interface 12. g If the transfer of data in the specified area is not completed, c
Return to. h Command end.

When the processor 11 executes the "EXP" command, the sequence is as follows. a Obtain the screen area data from the external processor interface 12. b Built-in corresponding program from external memory 3 High speed R
Transfer to AM14. c If data is set in the external processor interface 12, the data is read. Wait if there is no data. The data read at d c is expanded. e If the expansion of the designated area is not completed, the procedure returns to c. f Interpolation processing of image data is performed as necessary, and the image data is written in the image memory 4. g command end

There are two methods for transmitting a still image between still image transmitting apparatuses using this integrated circuit and displaying a screen of n divisions on the receiving side. The method performed by the conventional device shown in FIG. 4 and the method made possible by the present integrated circuit shown in FIG. In the method of FIG. 4, the transmitting side sequentially transmits n still images. On the receiving side, the still image is reduced and reproduced to form an n-divided image. In the method of FIG. 5, the transmitting side performs the reduced capture of the still image shown in FIG. 2 n times to form an n-divided screen and transmits it. On the other hand, the receiving side simply reproduces the sent image data. The method of FIG. 5 is longer than the method of FIG. 4 in transmission time (telephone line occupation time)
The advantage is that the screen can be shortened and the screen configured on the sending side can be confirmed.

[0014]

As described above, according to the present invention, the functions of compressing / decompressing image data necessary for the still image transmission device and controlling the image memory, AD converter and DA converter are realized by the present integrated circuit. Therefore, the still image transmission device can be downsized. In particular, processing the compression / decompression processing of image data by a processor incorporated in an integrated circuit reduces the load on the processor controlling the entire apparatus and greatly simplifies the circuit associated with the program. Being able to arrange the program outside the integrated circuit without degrading the processing capability facilitates adapting to various image data processing including program modification and image data compression / expansion processing. Further, the still image reduction transmission according to the present invention enables more efficient still image transmission than ever before.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an integrated circuit of the present invention.

FIG. 2 is a diagram showing an execution procedure of image processing.

FIG. 3 is a diagram showing still image division and capture.

FIG. 4 is a diagram showing divisional reproduction of a still image by a conventional device.

FIG. 5 is a diagram showing still image division transfer according to the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/08 B 9070-5C

Claims (3)

[Claims] 1. A still image in an integrated circuit which constitutes a circuit for taking in the image data obtained by AD converting an image signal as a still image into an image memory and transmitting it through a subscriber telephone line or a circuit for receiving this signal and reproducing the still image. A processor for performing data compression / expansion processing, an external processor interface for exchanging data with a processor external to the integrated circuit, an external bus interface with an external memory for storing the compression / expansion processing program and data, and an image. RAM and ROM for storing data, programs and data, external image memory,
An integrated circuit having an image memory interface for controlling an AD converter and a DA converter, and a synchronizing circuit section. 2. The integrated circuit according to claim 1, wherein the compression / expansion program is executed by transferring the compression / expansion processing program stored in the external memory to the RAM of the integrated circuit and then reading the RAM. 3. An image transmission method, wherein the integrated circuit according to claim 1 or 2 captures still image data from an AD converter into an image memory as a partial screen at an arbitrary position.