JPH0520129A - Microprocessor monitoring system - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object of the present invention to provide a microprocessor monitoring method for monitoring the normality of a microprocessor, which is highly reliable when detecting an abnormal state. A monitoring unit 4 having a first flag 2 and a second flag 3 is provided for a microprocessor 1. The monitoring unit 4 sets the first flag 2 to 1 at a constant cycle, and the microprocessor 1 reads the first flag 2 at a proper time, and when it is 1, sets the second flag 3 to 1. The first flag 2 to 0 and the first flag 2
Is 0, the second flag 3 is set to 0.
By resetting the microprocessor 1 when the monitoring unit 4 detects that the time when the first flag 2 or the second flag 3 is 1 exceeds the predetermined time,
It is configured by monitoring the normality of the microprocessor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for monitoring the normality of a microprocessor, and more particularly to a microprocessor monitoring system having high reliability in detecting an abnormal state of the microprocessor.

When performing various kinds of control and the like, a system has been widely used in which a microprocessor is used to perform a required operation by software. In such a system, it is important that the microprocessor always operates normally without causing a runaway or the like. Therefore, it is essential to monitor the normality of the microprocessor.

It is demanded that such a microprocessor monitoring system be capable of detecting an abnormal state of the microprocessor with high reliability.

[0004]

2. Description of the Related Art FIG. 4 shows a conventional microprocessor monitoring system which uses a so-called watchdog timer. In FIG. 4, 11 indicates a monitored microprocessor (MPU), and 12 is a watchdog timer.

The watchdog timer 12 has a timer circuit internally using a resistor (R) and a capacitor (C), and utilizes a transient phenomenon in this circuit to make a time constant RC.
This timer circuit is cleared by the MPU 11 accessing a specific point of the watchdog timer 12 within a fixed time determined by. As a result, the watchdog timer 12 determines that the MPU 11 is not operating abnormally and does not generate a reset signal for the MPU 11.

On the other hand, within the time determined by the time constant RC, M
When the PU 11 does not access a specific point of the watchdog timer 12, the timer circuit times out, so the watchdog timer 12 is set to the MPU 11
Is determined to be in an abnormal state, a reset signal is generated to reset the MPU 11.

As described above, in the case of the conventional watchdog timer, the only condition for judging the normality of the MPU is that the point of the watchdog timer is accessed from the microprocessor within a certain period of time, which is extremely simple. Moreover, it is possible to monitor the abnormal state of the microprocessor.

[0008]

However, there are cases where the point of the watchdog timer is continuously accessed regardless of the abnormal state of the microprocessor. In such a case, there is a problem that the watchdog timer cannot judge that the microprocessor is in an abnormal state and cannot generate a reset signal to the microprocessor.

The present invention is intended to solve such a problem of the prior art, and even in the above case, it is possible to judge that the microprocessor is in an abnormal state and output a reset signal. Therefore, it is an object of the present invention to provide a microprocessor monitoring method that can obtain higher reliability than the watchdog timer in determining the normality of the microprocessor.

[0010]

According to the microprocessor monitoring system of the present invention, the microprocessor
The monitoring unit 4 having the flag 2 and the second flag 3 is provided. The monitoring unit 4 sets 1 to the first flag 2 at a constant cycle, and when the microprocessor 1 reads the first flag 2 at a proper time and is 1, the second flag 3 is set to 1
Is set to set the first flag 2 to 0, and when the first flag 2 is 0, the second flag 3 is set to 0. The monitoring unit 4 resets the microprocessor 1 when it detects that the time when the first flag 2 or the second flag 3 is 1 exceeds a predetermined time, thereby monitoring the normality of the microprocessor 1. It is characterized by doing.

Further, the microprocessor monitoring system of the present invention has a read register 24 which is set in the microprocessor 11 at regular intervals, and a read register 24.
The first timer counter 26 which counts the set time of the above and times out when a predetermined time elapses, the write register 25 which is set and reset according to the output of the microprocessor 11, and the set time of the write register 25 is counted and the predetermined time A second timer counter 27 that times out when a lapse of time is provided. When the read register 24 of the microprocessor 11 is in the set state, the write register 25
Is set to reset the read register 24 and clear the first timer counter 26. Further, the microprocessor 11 uses the read register 24
Is reset, the write register 25 is reset to clear the second timer counter 27. Then, the normality of the microprocessor 11 is monitored by resetting the microprocessor 11 by the timeout of the first timer counter 26 or the second timer counter 27.

[0012]

The first flag 2 is set to 1 at a constant cycle. The microprocessor 1 reads the first flag 2 at a proper time, and when the value is 1, the second flag 3 is set to 1 to set 0 to the first flag 2. In addition, the microprocessor 1 uses the first flag 2
Is 0, the second flag 3 is set to 0. Then, the first flag 2 or the second flag 3 is 1
Then, the microprocessor 1 is reset by generating a reset signal when a predetermined time is exceeded. When the microprocessor 1 is abnormal, the second flag 3 cannot be set to a predetermined state in accordance with the state of the first flag 2, so the first flag 2 or the second flag 3 cannot be set.
The flag 3 of 1 is longer than a predetermined time. Therefore, by detecting this, the microprocessor 1 can be reset, and the normality of the microprocessor 1 can be monitored by this.

The read register 24 is set at regular intervals. The first timer counter 26 counts the set time of the read register 24 and times out when a predetermined time has elapsed. The write register 25 is set and reset according to the output of the microprocessor 11. The second timer counter 27 counts the set time of the write register 25 and times out when a predetermined time has elapsed. The microprocessor 11 sets the write register 25 when the read register 24 is in the set state, whereby the read register 24 is reset and the first timer counter 26 is cleared. Further, the microprocessor 11 resets the write register 25 when the read register 24 is in the reset state, so that the second timer counter 27 is cleared. When the microprocessor 1 is abnormal, the write register 25 cannot be set to a predetermined state according to the state of the read register 24, so the first timer counter 26 or the second timer counter 27 times out. Therefore, the microprocessor 11 can be reset by detecting this, and the normality of the microprocessor 11 can be monitored by this.

[0014]

FIG. 2 shows the structure of an embodiment of the present invention, in which the same parts as those in FIG. 4 are designated by the same reference numerals, and 13 is a monitoring unit for monitoring the normality of the microprocessor. is there. In the monitoring unit 13, 21 is an oscillator that generates a pulse of a constant cycle, 22 is a counter that divides the pulse from the oscillator 21, 23 is a flip-flop (FF) that holds the output state of the monitoring unit, and 24 is the MPU 11 monitors Read register (RRE that reads the status of the part 13
G), 25 is a write register (WREG) in which the MPU 11 writes a response to the monitoring unit 13, 26 is a timer counter (CNT1) for measuring the time when the read register 24 is in the "H" state, and 27 is in the write register 25 " A timer counter (C
NT2), 28 and 29 are AND circuits, and 30 is an OR circuit.

FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG. Hereinafter, based on FIGS. 2 and 3, the operation of each unit when the MPU 22 is normal will be described by dividing it into states A to D shown in FIG.

(State A) The counter 22 divides the output of the oscillator 21 to generate an output that alternately changes between "H" and "L" at a constant cycle T. FF23 is
Set to "H" at the rising edge of the output of the counter 22,
The read register 24 reads the state of the FF 23 and its output becomes "H". At the same time, the timer counter 26 starts counting by being supplied with a clock from the counter 22 via the AND circuit 28.

(State B) The MPU 11 reads the state of the read register 24, and outputs "H" because it is "H", and "H" is written in the write register 25 by this. When the state of the write register 25 becomes "H", the FF 23 is cleared and becomes "L", whereby the timer counter 26
Is cleared. Almost at the same time, the timer counter 2
7 starts counting by being supplied with a clock from the counter 22 through the AND circuit 29.

(State C) The MPU 11 reads the state of the read register 24 again, and when it is "L", the output of "L" is generated, whereby "L" is written in the write register 25. Write register 25
The timer counter 27 is cleared by the state of "1" becoming "L".

After (state D), the MPU 11 periodically reads the output of the read register 24, and when it is "L", the output of "L" is generated, and thereby "L" is written in the write register 25. Keep going. This state continues until the FF 23 becomes "H" after T time and the same operation is repeated again.

When the MPU 11 is normal, the above operation is repeated. Each of the timer counters 26 and 27 has a predetermined time-out time and is cleared before the time-out, so that no output is generated.

When the MPU 11 does not output a normal response corresponding to the state of the read register 24 to the write register 25 for some reason, the timer counters 26 and 27 time out and generate an output via the OR circuit 30. Then, the MPU 11 is reset by this output.

As described above, when the MPU 11 does not make a predetermined response according to the state of the monitoring unit 13, the MPU 11 is judged to be abnormal and the MPU 11 is reset, so that the normality of the MPU 11 is monitored. Can be done. Further, an alarm for notifying the abnormality of the MPU 11 can be generated to the outside by the reset signal to the MPU 11.

[0023]

As described above, according to the present invention, M
Since the PU periodically reads the status of the monitoring unit and makes a predetermined response, the monitoring unit determines the normality of the MPU, so that the MPU can be monitored with higher reliability than the conventional watchdog timer. Can be done.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a time chart explaining the operation of the embodiment shown in FIG.

FIG. 4 is a diagram showing a conventional microprocessor monitoring system.

[Explanation of symbols]

1,11 microprocessor A few flags 4 Monitor 24 read register 25 write register 26,27 timer counter

Claims (2)

[Claims] 1. A microprocessor monitoring system for monitoring the normality of a microprocessor (1), comprising a monitoring section (4) having a first flag (2) and a second flag (3), and monitoring section. (4) sets 1 to the first flag (2) at a constant cycle, and when the microprocessor (1) reads the first flag (2) at the appropriate time and is 1, the second flag (3 ) Is set to 1 and the first flag (2)
Is set to 0, and when it is 0, the second flag (3) is set to 0, and the monitoring unit (4) sets the first flag (2) or the second flag (3) to 1. A microprocessor monitoring method characterized in that the microprocessor (1) is reset when it is detected that the time exceeds a predetermined time. 2. In a microprocessor monitoring system for monitoring the normality of a microprocessor (11), a read register (24) to be set at a constant cycle and a set time of the read register (24) are counted and a predetermined time has elapsed. First timer counter that times out (26)
A write register (25) that is set and reset according to the output of the microprocessor (11); and a second timer counter (27) that counts the set time of the write register (25) and times out when a predetermined time elapses. The read register (24) is reset and the first timer counter (26) is cleared by the microprocessor (11) setting the write register (25) when the read register (24) is in the set state. , The microprocessor (11) writes the write register (2 when the read register (24) is in the reset state.
By resetting 5), the second timer counter (27) is cleared and the first timer counter (26)
Alternatively, the microprocessor (11) is reset by the time-out of the second timer counter (27).