JPH05206464A - Thin film semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To improve the property of a thin film transistor and lower the temperature in process. CONSTITUTION:In a thin film semiconductor device, which constitutes a MIS field effect transistor, the semiconductor thin film in a channel region is constituted of a section which has at least two kinds of thin films. Accordingly, enough on/off ratio is secured by other thin part. And, since a source region 2S and a drain region 2D are thickened, enough activation at low temperature becomes possible. Moreover, a gate electrode is provided to cover both the thick part and the thin part of a semiconductor film 2, and with this as a mask, ion implantation to form the source region 2S and the drain region 2D is performed, so a channel region 2C is made in the semiconductor film 2 with two thicknesses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device constituting a MIS type field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art A thin film transistor (TFT) used for an active matrix type liquid crystal display device is basically constructed as shown in FIG. That is, a semiconductor thin film 2 such as polysilicon is formed and patterned on a substrate 1 such as glass or ceramics, and the upper surface is S
It is covered with a gate insulating film 3 such as iO ₂ . A gate electrode 4 made of tantalum, polysilicon, or the like is formed on the gate insulating film 3 in the channel region 2C of the thin film transistor, and the semiconductor thin film 2 is doped with impurities in a self-aligned manner to form a source region 2S and a drain region 2D. To be done.
Further, an interlayer insulating film 5 such as SiO ₂ is formed, and the source region 2S and the drain region 2 are formed through the contact holes.
A source electrode 6S and a drain electrode 6D connected to D are provided.

When a thin film transistor having such a structure is formed by a low temperature process having a maximum process temperature of about 600 ° C., the semiconductor thin film 2 usually requires a film thickness of 1000 Å or more to activate the source / drain regions. To be done. FIG. 8 shows the relationship between the thickness of the channel region 2C of the semiconductor thin film 2 and the on / off ratio. The thin film is 50 nm (5
If it exceeds 00 angstrom), the off current increases sharply, and the on / off ratio is greatly deteriorated.

On the other hand, when a thin film transistor having a conventional structure is formed by a high temperature process, the source / drain regions can be activated at a high temperature of about 1000 ° C., so that the thickness of the semiconductor film 2 is reduced to about 500 Å. And a relatively high on / off ratio can be ensured.

[0005]

However, the conventional techniques have the following problems. First, when a thin film transistor having a conventional structure is adopted, the maximum process temperature is 100
Since a self-aligned thin film semiconductor device can be manufactured only in a high temperature process of 0 ° C. or higher, use of an expensive fused silica substrate is obligatory and there is a problem that the product price rises. In addition, because of the high temperature process, deformation such as warpage and distortion of the substrate occurs, and only a small quartz substrate can be used, and it is difficult to increase the size. Even when manufactured on a small-sized substrate in a high temperature process, the semiconductor thin film 2 is often peeled from the substrate when the contact holes are formed for forming the source / drain electrodes, and the contact resistance becomes large even after the electrodes are formed. Stable mass production has been difficult because it causes a decrease in productivity such as a substantial reduction in characteristics.

On the other hand, when a thin film transistor having a conventional structure is formed in a low temperature process, it is difficult to thin the semiconductor film as described above, so that a thin film transistor having a high off current and consequently a small on / off ratio can be manufactured. No, it has not been put to practical use.

The present invention is intended to solve the above problems, and an object of the present invention is to provide a thin film semiconductor device having a structure capable of stably manufacturing a good thin film transistor having a high on / off ratio and a manufacturing method thereof. And to provide.

[0008]

According to the present invention, at least one surface of a substrate whose surface is an insulating material has a source region and a drain region containing an impurity serving as a donor or an acceptor, the source region and the drain region. M including a semiconductor film that forms a channel region connecting to each other, a gate insulating film formed so as to cover at least the channel region, and a gate electrode provided on the gate insulating film.
In the thin film semiconductor device forming the IS field effect transistor, the semiconductor film in the channel region is formed by at least two kinds of portions having different film thicknesses.

Further, according to the present invention, the first semiconductor film is deposited on at least the surface of the substrate made of an insulating material, and then the first region is formed only in the source region, the drain region and the channel region having a large film thickness. The first step of patterning so that the semiconductor film remains, the second semiconductor film is deposited, and then the second step is performed only on the remaining first semiconductor film and only at a portion where a thin channel region is to be formed later. Second step of patterning so that the remaining semiconductor film remains, a third step of forming a gate insulating film, and a channel having a large film thickness after a part of the remaining first and second semiconductor films. A fourth step of forming a gate electrode on the gate insulating film so as to cover a portion to be a region and a portion of the remaining second semiconductor film to be a channel region having a thin film thickness later. Use the gate electrode as a mask The impurity serving as a donor or acceptor is added to the first and the second semiconductor film which is not covered with the gate electrode, characterized in that it comprises a fifth step of forming a source region and a drain region.

Further, according to the present invention, after depositing a first semiconductor film on a substrate having at least a surface made of an insulating material, the first semiconductor film is removed from a portion which will later become a thin thin film channel region and its vicinity. First step, depositing a second semiconductor film, and then removing the second semiconductor film and the first semiconductor film from the other parts except the part which becomes the source region, the drain region and the channel region later. The second step, the third step of forming the gate insulating film, and the part of the remaining first and second semiconductor films that will later become a thick channel region remain. A fourth step of forming a gate electrode on the gate insulating film so as to cover a part of the second semiconductor film which will later become a thin channel region, and a donor or acceptor using the gate electrode as a mask. That an impurity is added to the first and second semiconductor film not covered with the gate electrode, characterized in that it comprises a fifth step of forming a source region and a drain region.

[0011]

In the thin film transistor according to the present invention, a part of the semiconductor thin film in the channel region is thickened, and therefore, another thin part ensures a sufficient on / off ratio. By thickening the source region and the drain region, it becomes possible to sufficiently activate the added impurities at a low temperature.

[0012]

Embodiments of the present invention will now be described with reference to the accompanying drawings, but the same elements will be denoted by the same reference symbols and redundant description will be omitted.

FIG. 1 is a sectional view showing the basic structure of a thin film transistor according to the embodiment. As shown in the figure, a semiconductor thin film 2 is patterned on the substrate 1. This semiconductor thin film 2 is thin in the central portion of the channel region 2C, and the source region 2S and the drain region 2D and both side portions of the channel region 2C in the vicinity thereof. Thickened in. Then, in alignment with the gate electrode 4, the semiconductor thin film 2 such as polysilicon is doped with impurities serving as donors or acceptors.

In this structure, when the thickness of the central portion of the channel region 2C is 500 angstroms or less, a sufficient on / off ratio is secured. Since the ion implantation is performed only on the thick semiconductor thin film 2, 600 ° C.
The following low temperature activation can be performed. Further, since the semiconductor thin film 2 is thickened at the contact portions of the source electrode 6S and the drain electrode 6D, it is possible to avoid the problem that the semiconductor thin film peels off when the contact hole is opened, and the contact between the source and drain electrodes can be improved.

Next, the manufacturing method of the first embodiment will be described with reference to FIGS. 2 (a) to (d)
FIG. 4 is a cross-sectional view of FIGS. First, glass
Insulating film 1 with good film quality on plate material 11 such as ceramics
2 is formed and is used as the substrate 1. Next, the lower semiconductor thin film 21 is formed of polysilicon and patterned (see FIGS. 2 and 3 (a)). Here, the deposition is performed at a temperature of 600 ° C. using a low pressure CVD method, and the flow rate of SiH ₄ is 11 [SCC.
M], silane partial pressure is 5.7 mtorr, thickness is 1500
Angstrom.

Next, the upper semiconductor thin film 22 is formed under the same conditions as the lower semiconductor thin film 21. However, the thickness is 250
The semiconductor thin film 2 forming a thin film transistor is formed by patterning with an angstrom (FIGS. 2 and 3 (b)).
reference).

Next, SiO ₂ is deposited by the ECR-CVD method to form the gate insulating film 3. At this time, the substrate 1
The temperature is 100 ° C. and the thickness is 1500 Å.

Next, phosphorus (P) -doped polysilicon is deposited at a temperature of 600 ° C. to a thickness of 3000 angstroms by a low pressure CVD method, and then Si is formed by an atmospheric pressure CVD method.
O ₂ is deposited at a temperature of 300 ° C. to a thickness of 1500 Å and patterned to form a two-layer structure of the gate electrode 4 and the cap insulating film 41 in the channel region 2C of the thin film transistor.
Form on top. Then, using this two-layer structure as a mask,
Using an ion implanter with a mass spectrometer, phosphorus ( ³¹ P
By implanting ⁺ ) ions, an n-type drain region 2D and a source region 2S are formed (see FIGS. 2 and 3 (c)). In this example, ³¹ P ⁺ is 3 × 10 ¹⁵ at 110 KeV.
/ Cm ^{2 was} hit.

Then, in an atmosphere of N ₂ gas, 600
Annealing is performed at 2 ° C. for 2 hours to activate the impurity-doped portion. In this embodiment, since the thick semiconductor thin film 2 is doped with impurities only, the activation is easy, and the sheet resistance of the source region 2S and the drain region 2D is about 2,424 ohms.

Next, the Si is formed at 300 ° C. by the atmospheric pressure CVD method.
O ₂ is deposited to 5000 Å to form an interlayer insulating film 5.
To form. Then, dope H ₂ (hydrogen) to 95
KeV is performed at a concentration of 2 × 10 ¹⁶ / cm ² to terminate dangling bonds of silicon with hydrogen. Then, heat treatment is performed at 350 ° C. for 2 hours to form a contact hole and form a source electrode 6S and a drain electrode 6D by a vapor deposition method or a sputtering method (shown in FIGS. 2 and 3 (d)).

At this time, since the film thickness of the source region and the drain region is about 1750 angstroms, the problems such as the peeling of the silicon film and the poor contact with the electrode can be solved without any problems.

The self-aligned thin film transistor thus manufactured is as follows.

Length; L = 5 + 10 + 5 μm Width; W = 10 μm Mobility; μ _O = 3.8 cm ² / V · sec On-current; I _ON = 6.54 × 10 ⁻⁸ A Off-current; I _OFF = 1. 91 x 10 ^-13 A (V _gS =-
0.5 V) Here, the film thickness of the channel portion is 1750 on the source region side.
Angstrom, 250 Angstrom in the center,
The drain region side is 1750 angstroms. The respective lengths are 5 μm, 10 μm and 5 μm, and the total channel length over the entire channel portion is 20 μm. The on-current I _ON is the source-drain current when the transistor is turned on at the source-drain voltage V _dS = 4V and the gate voltage V _gS = 10V. Further, the off-current is defined as the minimum value of the source / drain current when the source / drain voltage V _dS = 4V. In this example, the off state was obtained at the gate voltage V _gS = _-0.5V .

As shown in this embodiment, the source / drain regions were successfully activated in the low temperature process without performing uncontrollable laser irradiation which was the cause of the variation only in the present invention. Since the film thickness near the center was thinned to 250 angstroms, it was possible to suppress the leak current when the transistor was off sufficiently low. As a result, even in the low temperature process, the gate voltage 10
It has been possible to realize a self-aligned thin film transistor having an on / off ratio of 5.5 digits for modulation of about V. Also,
The planar shape of the upper semiconductor thin film 22 may be as shown in FIG. 4 instead of FIG. 4 (a)-(d)
Corresponds to FIGS. 2A to 2D.

Further, it may be as shown in FIGS. Here, the cross sections of FIGS. 5A to 5E are shown in FIG.
It is sectional drawing in the centerline of (a)-(e). First, an insulating film 12 having a good film quality is formed on a plate material 11 such as glass or ceramics, and this is used as a substrate 1. Next, the semiconductor thin film 21 is formed of polysilicon, and subsequently, patterning is performed so as to remove the semiconductor thin film from a portion to be a channel region having a thin film thickness later and the vicinity thereof, thereby forming the lower semiconductor thin film 21. ..

(See FIGS. 5 and 6 (a)). Here, the deposition is performed by using a low pressure CVD method at a temperature of 600 ° C., the flow rate of SiH ₄ is 11 [SCCM], the silane partial pressure is 5.7 mtorr, and the thickness is 1500 angstrom.

Next, the upper semiconductor thin film 22 is formed under the same conditions as the lower semiconductor thin film 21. (See FIGS. 5 and 6 (b))
However, the thickness thereof is set to 250 Å, and the semiconductor thin film 2 forming the source / drain and channel regions of the thin film transistor is formed by patterning to remove the lower semiconductor thin film 21 and the upper semiconductor thin film 22 other than the transistor region (FIG. 5, FIG. 6 (c)).

Next, SiO ₂ is deposited by the ECR-CVD method to form the gate insulating film 3. At this time, the substrate 1
The temperature is 100 ° C. and the thickness is 1500 Å.

Next, polysilicon doped with phosphorus (P) as an impurity by the low pressure CVD method is heated at 600 ° C. for 30 times.
Deposited to a thickness of 00 Å, then atmospheric CVD
Method is used to deposit SiO ₂ at a temperature of 300 ° C. to a thickness of 1500 Å and pattern it to form a two-layer structure of the gate electrode 4 and the cap insulating film 41 on the channel region 2C of the thin film transistor. Then, using this two-layer structure as a mask, phosphorus ( ³¹ P ⁺ ) ions are implanted using an ion implanter equipped with a mass spectrometer to form an n-type drain region 2D and a source region 2S (see FIG. 5,
6 (d)). In this embodiment, ³¹ P ⁺ was implanted at 110 KeV and 3 × 10 ¹⁵ / cm ² .

Then, in an atmosphere of N ₂ gas, 600
Annealing is performed at 2 ° C. for 2 hours to activate the impurity-doped portion. In this embodiment, since the thick semiconductor thin film 2 is doped with impurities only, the activation is easy, and the sheet resistance of the source region 2S and the drain region 2D is about 2,424 ohms.

Next, Si is formed at 300 ° C. by an atmospheric pressure CVD method.
O ₂ is deposited to 5000 Å to form an interlayer insulating film 5.
To form. Then, dope H ₂ (hydrogen) to 95
KeV is performed at a concentration of 2 × 10 ¹⁶ / cm ² to terminate dangling bonds of silicon with hydrogen. Then, heat treatment is performed at 350 ° C. for 2 hours to form a contact hole and form a source electrode 6S and a drain electrode 6D by vapor deposition or sputtering (illustrated in FIGS. 5 and 6E).

According to the first embodiment described above, an n-channel self-aligned thin film transistor having excellent characteristics (low off current and high on current) can be obtained only by a low temperature process using a glass substrate. Further, by adopting the structure of the present invention, it is possible to improve the yield even in the high temperature process and stably manufacture many thin film transistors. In this embodiment, the thickness of the lower semiconductor thin film 21 is set to 150.
The thickness is 0 angstrom, so the on / off ratio is 5.
Although it has only about 5 digits, the characteristics can be further improved by thinning the lower semiconductor film to about 300 Å. This will be shown in another embodiment later. Generally, if the film thickness of the source / drain region is about 500 angstroms or less, problems such as peeling of the silicon film and contact failure occur, while the film thickness of the channel region is 5
Since the off current increases and the on / off ratio decreases when the thickness is about 100 Å or more (FIG. 8), it is preferable that the film thicknesses of the lower semiconductor film and the upper semiconductor film are each about 250 Å, and as a result, the source It is best that the film thickness of the drain region and the channel region of the thick film portion is about 500 Å, and the film thickness of the channel region of the thin film portion is about 250 Å.

Next, the manufacturing process of the second embodiment will be described.
First, the temperature is 620 ° C. and the silane partial pressure is 7.53 mtor.
SiH ₄ of 17 [SCCM] is supplied under the condition of r
A lower semiconductor thin film 21 of 1500 angstroms of polysilicon is formed on the substrate 1 by the VD method and patterned (see FIGS. 2, 3, 4 (a)). Then, an upper semiconductor thin film 22 of 250 Å is formed and patterned under the same conditions. As a result, the semiconductor thin film 2 for thin film transistor is formed (FIGS. 2, 3, 4 (b)).
reference).

Next, ECR-CVD is performed at a substrate temperature of 100 ° C.
The gate insulating film 3 of SiO ₂ is formed to a thickness of 1500 angstroms by the method. After that, SiH ₄ was added to the source gas.
The PH ₃ with a, formed at 600 ° C. 3000 Angstroms doped polysilicon in the low pressure CVD method, then a condition of 300 ° C. at atmospheric pressure CVD, a SiO ₂ 0.99
Deposit 0 Å. Then, by patterning, the gate electrode 4 shown in FIGS.
A double structure of the cap insulating film 41 is obtained.

Then, phosphorus ions were implanted by using a mass non-separation type ion implanter without a mass spectrometer to form source / drain regions. In this embodiment, 5% concentration of phosphine (P
H ₃ ) and acceleration voltage of 110 KV at 3 × 10 ¹⁵ / cm
Phosphorus was added at a concentration of ² . Next, heat treatment was performed at 300 ° C. for 2 hours in a reducing atmosphere containing 3% of hydrogen. At this time, the sheet resistance of the source region 2S and the drain region 2D was 3888Ω / □. Conventionally, heat treatment at about 600 ° C. or higher was required to activate the additive impurity element.
By implanting phosphine diluted with hydrogen with a mass non-separation type ion implanter, hydrogen ions were simultaneously added when phosphorus was added, and the hydrogen ions terminated dangling bonds in silicon. Therefore, scattering of electrons in the n-type silicon due to dangling bonds is suppressed, and the resistance can be lowered. In addition, the release of hydrogen from the gate SiO ₂ can be reduced, and the hydrogenation treatment such as hydrogen doping afterwards can be reduced or omitted. In general, hydrogenation treatment is a major cause of transistor variation and lot-to-lot variation. Therefore, reduction or omission of hydrogenation treatment according to this embodiment is a technological advance that is essential for stable mass production. ..

Next, by atmospheric pressure CVD method at 300 ° C. for 50 minutes.
Interlayer insulating film 5 of 00 angstrom is formed and
Hydrogen is injected at a lower concentration of eV and 1.2 × 10 ¹⁶ / cm ² at a lower voltage, and heat treatment is performed at 350 ° C. for 2 hours. Then, a contact hole is provided to form the source electrode 6S.
And the drain electrode 6D is formed (FIGS. 2, 3 and 4).
(See (d)).

The thin film transistor thus formed has μ _O = 4.82 cm ² / V · sec and I _ON = 1.4.
9 × 10 ⁻⁷ A, I _OFF = 1.56 × 10 ⁻¹³ A (V _gS =
It was 1.0 V). In this embodiment, the source region 2S
Since hydrogen is also injected at the same time as the impurity is injected into the drain region 2D, a lower temperature process can be performed. Further, the hydrogenation conditions for terminating the dangling bonds of silicon can be relaxed.

Also in the process of the second embodiment, the structure of the thin film transistor can be as shown in FIGS.

Next, the manufacturing method of the third embodiment will be described.
In this case, the lower semiconductor thin film 21 is formed by the low pressure CVD method.
The upper semiconductor thin film 22 is formed to a thickness of 1500 angstroms under the conditions of 00 ° C., the flow rate of SiH ₄ is 13 [SCCM] and the partial pressure thereof is 6.3 mtorr, and the upper semiconductor thin film 22 is formed to 250 angstroms under the above conditions. The following process is the same as that of the second embodiment.

In this case, the sheet resistance of the source region 2S and the drain region 2D is 2904 ohms, and μ _O = 5.05 cm ² / Vsec of the thin film transistor,
I _ON = 3.41 × 10 ⁻⁷ A, I _OFF = 1.04 × 10
^{It was -12} A (at the time of V _dS = 1.5 V). Compared with the second embodiment, since the silane partial pressure during the semiconductor thin film deposition is lowered, the on-current is improved even though the process maximum temperature is as low as 600 ° C.

Next, the manufacturing method of the fourth embodiment will be described.
In this case, as in the second embodiment, the lower semiconductor thin film 2
1, the upper semiconductor thin film 22 and the gate insulating film 3 are formed. The gate electrode 4 is made of 2000 angstrom chromium (C) by a sputtering method at 100 to 200 ° C.
r) film, and the cap insulating film 41 is SiO _{2 at} 300 ° C. and 3000 angstrom by atmospheric pressure CVD method. Further, the doping of phosphorus and hydrogen with PH ₃ and the subsequent heat treatment are also performed in the same manner as in the second embodiment, and then the atmospheric pressure CV is applied.
5000 Å Si at 300 ° C by D method
An interlayer insulating film 5 made of O ₂ is formed. Then, the source electrode 6S and the drain electrode 6D are formed.

In the thin film transistor thus obtained, the sheet resistance of the source region 2S and the drain region 2D is 2300 ohms, and μ _O = 5.43 cm ² / V · se.
c, I _ON = 1.73 × 10 ⁻⁷ A, I _OFF = 1.46 × 1
It was 0 ^-13 A (at the time of V _gS = -3.2 V). In this embodiment, the gate electrode is made of chromium by the sputtering method,
Furthermore, the formation of the source / drain regions according to the present invention is performed 300 times.
Since the activation is performed at a low temperature of ℃, the maximum temperature of the thermal process after forming the gate insulating film could be kept as low as 300 ℃. For this reason, the hydrogenation process, which is the main cause of variations and fluctuations, was eliminated and the transistor characteristics were improved.

Next, the manufacturing method of the fifth embodiment will be described.
The temperature of the lower semiconductor thin film 21 is set to 570 ° C. by the low pressure CVD method, SiH ₄ is set to 100 [SCCM], the silane partial pressure is set to 0.8 mtorr, and the thickness is set to 250 angstrom. Next, the upper semiconductor thin film 22 has a thickness of 250 angstroms under the same conditions, and the gate insulating film 3 is the same as that of the second embodiment. After depositing 2000 angstrom ITO by the sputtering method, the cap insulating film 41 is exposed to 300 ° C. by the atmospheric pressure CVD method.
To 3500 angstroms of SiO ₂ . Then, the doping of phosphorus and hydrogen with PH ₃ is performed at 110 ke
V and 6 × 10 ¹⁵ / cm ² and heat treatment at 350 ° C. for 2 hours. The sheet resistance of the source region 2S and the drain region 2D by such low temperature treatment was 4964 ohms. Then, as in the second embodiment, the interlayer insulating film 5 is formed.
A source electrode 6S and a drain electrode 6D are formed.
In the thin film transistor thus obtained, W = 30 μm, and the transistor length L is 5 μm in the thick channel portions of the thin film on the source side and the drain side, and 5 μm in the thin portion in the center.
m for a total of 15 μm, μ ₀ = 13.6 cm ² / V
Sec, I _ON = 1.68 × 10 ⁻⁶ A, I _OFF = 2.6
By modulating 6 × 10 ⁻¹³ A (V _gS = OV) and a gate voltage of 10 V, an extremely good thin film transistor having an on / off ratio of about 7 digits was produced. As described above, the thickness of the lower semiconductor film and the thickness of the upper semiconductor film are as thin as 250 angstroms, respectively.
This is because it has a film thickness of 00 angstrom and the film thickness of the channel portion can be made extremely thin to 250 angstrom. This is also because the hydride of the added ion species was diluted with hydrogen and implanted by using the non-mass separation type ion implantation device, so that low temperature activation was possible and an extra heat step could be eliminated.

[0044]

As described above in detail, in the thin film transistor according to the present invention, a part of the semiconductor thin film in the channel region is made thicker, and therefore another thin film (for example, 5).
00 angstroms or less) is enough to turn on /
The off ratio is secured. Then, by thickening the source region and the drain region, it becomes possible to perform sufficient activation at a low temperature and to improve the contact.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a basic structure of a thin film transistor according to an example.

FIG. 2 is a cross-sectional view showing the method of manufacturing the thin film transistor according to the example.

FIG. 3 is a plan view corresponding to FIG.

FIG. 4 is a plan view corresponding to FIG.

FIG. 5 is a cross-sectional view showing the method of manufacturing the thin film transistor according to the example.

FIG. 6 is a plan view corresponding to FIG.

FIG. 7 is a cross-sectional view of a conventional thin film transistor.

FIG. 8 is a diagram showing a relationship between a film thickness of polysilicon and an on / off ratio of a thin film transistor.

[Explanation of symbols]

1 ... Substrate, 2 ... Semiconductor thin film, 2C ... Channel region, 2S
... Source region, 2D ... Drain region, 21 ... Lower semiconductor thin film, 22 ... Upper semiconductor thin film, 3 ... Gate insulating film, 4 ...
Gate electrode, 41 ... Cap insulating film, 5 ... Interlayer insulating film,
6S ... Source electrode, 6D ... Drain electrode.

Claims (9)

[Claims] 1. A source region and a drain region containing an impurity serving as a donor or an acceptor, and a channel region connecting the source region and the drain region are formed on at least one surface of a substrate whose surface is an insulating material. A thin film semiconductor device forming a MIS field effect transistor comprising a semiconductor film, a gate insulating film formed so as to cover at least the channel region, and a gate electrode provided on the gate insulating film, A thin film semiconductor device, wherein the semiconductor film in the channel region is formed by at least two kinds of portions having different film thicknesses. 2. The film thickness of the semiconductor film forming the source region and the drain region is the same as or thicker than the film thickness of a thick portion of the semiconductor film forming a part of the channel region. The thin film semiconductor device according to claim 1. 3. The thin film semiconductor device according to claim 1, wherein the thin film thickness of the semiconductor film forming a part of the channel region is 500 angstroms or less. 4. After depositing a first semiconductor film on a substrate having at least a surface made of an insulating material, the first semiconductor film remains only on the source region, the drain region, and the portions which become thick channel regions. First to pattern to
And the step of depositing a second semiconductor film and then leaving the remaining first semiconductor film.
A second step of patterning so that the second semiconductor film remains only on a portion of the semiconductor film that is to be turned into a thin channel region later, and a third step of forming a gate insulating film. A part of the first and second semiconductor films which later become a thick channel region, and a part of the remaining second semiconductor film which later becomes a thin channel region. A fourth step of forming a gate electrode on the gate insulating film so as to cover the gate insulating film, and the first and second semiconductors in which the gate electrode is not covered with impurities serving as donors or acceptors using the gate electrode as a mask. A fifth step of forming a source region and a drain region by adding to the film, and a method of manufacturing a thin film semiconductor device. 5. The method of manufacturing a thin film semiconductor device according to claim 4, wherein the source region and the drain region are formed by implanting an impurity serving as a donor or an acceptor using an ion implantation device. 6. A source region and a drain region are formed by implanting an impurity serving as a donor or an acceptor using a mixture of a hydride of the impurity element and hydrogen as a source gas and using a mass non-separation type ion implantation device. 5. The method for manufacturing a thin film semiconductor device according to claim 4, wherein. 7. A first semiconductor film is deposited on a substrate, at least the surface of which is made of an insulating material, and thereafter, the first semiconductor film is removed from a portion to be a channel region having a thin film thickness and its vicinity. A second step of depositing the second semiconductor film, and then removing the second semiconductor film and the first semiconductor film from other portions except the portions which will later become the source region, the drain region and the channel region. A step of forming a gate insulating film, a part of the remaining first and second semiconductor films to be a channel region with a large film thickness later, and the remaining part of the first and second semiconductor films. A second step of forming a gate electrode on the gate insulating film so as to cover a part of the second semiconductor film which will later become a thin channel region, and the gate electrode serves as a mask to serve as a donor or an acceptor. The impurities not covered with the gate electrode and the first
And a fifth step of forming a source region and a drain region by adding it to the second semiconductor film, the method for manufacturing a thin film semiconductor device. 8. The method of manufacturing a thin film semiconductor device according to claim 7, wherein the source region and the drain region are formed by implanting impurities serving as donors or acceptors by using an ion implantation device. 9. A source region and a drain region are formed by implanting an impurity serving as a donor or an acceptor, using a mixture of a hydride of the impurity element and hydrogen as a source gas and using a mass non-separation type ion implantation device. The method for manufacturing a thin film semiconductor device according to claim 7, wherein