JPH05210512A - Processor - Google Patents

Abstract

(57) [Abstract] [Object] The present invention provides a processor capable of multiple interrupts and achieving high-speed responsiveness to interrupt processing without being restricted by the registers that can be used in interrupt processing. To aim. The present invention relates to a dedicated register (6, 7, 8) for holding specific information related to program execution, a general-purpose register (3) for holding unspecified information related to program execution, and a currently used register. A first register (4) holding information indicating a bank inside, a second register (5) holding information indicating a return bank, held in the second register, the dedicated register and a general-purpose register. Each piece of information is composed of a bank memory (2) having a plurality of banks to be transferred without passing through an external bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor having a bank structure, and more particularly to a processor capable of handling multiple interrupts.

[0002]

2. Description of the Related Art Generally, the number of general purpose registers in a CPU (central processing unit) of a microprocessor is limited by the number of semiconductor chips used. for that reason,
There is a microprocessor having a structure called a bank structure.

A bank is a group of general-purpose registers (mainly used for calculation in a program). Generally, when storing a general-purpose register, an area of a RAM (random access memory) is stored in a space (called a bank RAM) divided by a predetermined size. By switching the bank, one bank RAM can be selected from among several bank RAMs to store and read general-purpose registers.

Among conventional microprocessors, those having a bank structure are equivalent to having a large number of general-purpose registers by switching banks. For example, as shown in FIG. 9, the microprocessor
If the general-purpose register 101 in one bank is set to 4 registers and has 256 banks, 4 × 256 = 1024
It is equivalent to having registers.

When there are a plurality of banks, there is a register called a bank pointer which indicates the number of the bank. By changing the value of that register, the contents stored in another bank can be treated as a general-purpose register that can be used now.

In a conventional microprocessor system having a bank structure, 1) stack memory and 2) general-purpose register are considered as save destinations of bank numbers used when an interrupt occurs. .. Even if the bank is switched in the interrupt routine, both of them read the bank number before the interrupt from each save destination after the interrupt routine ends, so you can return to the original bank by looking at the bank number. You can

[0007]

Among the microprocessor systems having the bank structure, the one that saves the bank number used when the interrupt occurs in the stack memory is connected to the external bus of the microprocessor. Moreover, it is necessary to perform writing to the low-speed stack memory (when an interrupt occurs) and reading (when returning from the interrupt processing), which takes time.

On the other hand, among microprocessor systems having a bank structure, when a bank is switched due to an interrupt, the bank number of the bank being used is saved in a general-purpose register after the bank is switched. As compared with the case of saving in the stack memory described above, since there is no slow access to the external bus, reading and writing of the bank number which is the return information is faster.

However, when the interrupt processing is performed using the general-purpose register after the bank switching, the general-purpose register containing the return information cannot be used and the general-purpose register that can be used in the interrupt processing can be limited. If you want to use that general-purpose register, you have to save the bank number by returning to a stack memory or the like. Therefore, it is slower than the method of saving to the stack memory from the beginning.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to enable multiple interrupts without being restricted by the registers that can be used in interrupt processing and to achieve high-speed interrupt processing. It is to provide a processor that can achieve high responsiveness.

[0011]

In order to achieve the above object, the present invention provides a dedicated register for holding specific information related to program execution and a general-purpose register for holding unspecified information related to program execution. A bank memory having a plurality of banks to which the information indicating the currently used bank, the information indicating the return bank, and the information held in the dedicated register and the general-purpose register are transferred without passing through an external bus. Composed of and.

[0012]

In the above structure, according to the present invention, the dedicated register and general-purpose register used in the processing and the position of the bank corresponding to the unfinished processing executed before the processing are provided for each processing. The indicated information is transferred to and held in the corresponding bank without passing through the external bus.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a main configuration of a processor according to an embodiment of the first feature of the present invention.

FIG. 1 is an enlarged view of a portion of a bank memory 2 of a CPU core 1 according to the present invention in the entire semiconductor chip. Originally, the semiconductor chip has a built-in ROM through the system bus in addition to the CPU 1 and the bank memory 2.
(Not shown), a timer (not shown), a bus controller (not shown), etc. are mounted. Data is exchanged between these elements via the system bus. Data is exchanged with the outside of the chip via the bus controller. The built-in ROM stores the command words of the program created by the user. Built-in R
The OM may also be implemented on a separate chip, in which case
CPU via system bus via bus controller
Data is exchanged with 1. In this specification, this system bus is used to mean an external bus, that is, external to the CPU. On the other hand, the feature of the present invention is that the contents of the general-purpose register 3 are transferred to the bank memory 2 when the bank is switched.
Since saving / restoring is performed via a dedicated bus connecting 1 and the bank memory 2, normal data transfer can be performed at high speed.

In FIG. 1, the processor includes a CPU 1 and a bank memory 2. The CPU 1 includes a general-purpose register group 3 including general-purpose registers RW0 to RW15 each having a 16-bit length, a current bank pointer (CBP) 4, a preliminary bank pointer (PBP) 5, a program counter (PC) 6, and a user stack pointer (USP). 7,
Processor status word (PSW) 8 and interrupt stack pointer (ISP), special stack pointer (ESP), condition code (C
A dedicated register group such as C) is provided.

The current bank pointer (CBP) 4 is
This is a register showing the position of the bank currently in use. The pre-deposited bank pointer (PBP) 5 is a register indicating the position of the return bank, which is the bank to be returned from the bank currently in use after the process executed using the bank currently in use is completed. However, if the value of PBP5 is "0", it indicates that there is information on the position of the bank to be returned to the stack memory. The program counter (PC) 6 is a register indicating an address of a memory area in which a command word of the program is stored, and its value changes when the program is operating.

The interrupt stack pointer (ISP) is PC6, PSW8, PBP5, U when returning from the interrupt.
It is a register indicating the address of the memory area in which the value of SP7 is stored. User stack pointer (USP)
Is a register indicating the address of the memory area in which the values of PC6, PSW8, and PBP5 are stored when returning from the subroutine of the user program. The special stack pointer (ESP) is a register indicating the address of the memory area in which the values of PC6, PSW8, PBP5, and USP when returning from the system call are stored. The condition code (CC) is a register that stores a flag indicating the state of the operation result. The processor status word (PSW) 8 is a register indicating the status of the microprocessor.

As shown in FIG. 2, the condition code CC is a carry flag C21 (1 when a carry occurs from the most significant bit or a borrow occurs as a result of the operation.
Is set), an overflow flag V22 (1 is set when an overflow occurs as a result of the operation), a zero flag Z23 (1 is set when the result of the operation is zero), a sign flag S24 (the operation result) The value of the most significant bit of is copied).

As shown in FIG. 3, the PSW 8 has a task mode TM31 (designation of stack pointer), a bank size (BS) 32 (size of bank currently in use),
Delayed interrupt designation (DI) 33, privileged mode designation (R)
G) 34, designation of single step operation (SS) 35,
Interrupt enable (EI) 36, interrupt mask (IM) 37,
Information such as the contents of the condition codes (CC) 21 to 24 is stored. Returning to FIG. 1, the bank memory 2
Are provided in the RAM built in the processor. The bank memory 2 includes, for example, banks 1 to 256.
, The bank i (i = 1 to 256) is composed of four unit banks and has a size of 4 words. In such a bank memory 2, for example, the general-purpose register group 3 is allocated to consecutive banks, and PC6, PBP5, PS
The dedicated register consisting of W8 and USP7 is assigned to one bank. Further, in the embodiment described below, as shown in FIG. 4, the general-purpose register 3 is allocated to the register groups R0 to R15 of four consecutive banks each consisting of four registers, and the PC6 and PBP5 are allocated. , PSW
8, dedicated registers consisting of USP7 are allocated to four continuous unit banks of one bank. The banks allocated in this way, the dedicated register group and the general-purpose register group 3 are connected so that data can be transferred at a high bandwidth without using an external bus.

In such a structure, a bank was used at an arbitrary time, but when an interrupt occurred, the bank was switched to an interrupt routine (a program for processing an interrupt). At that time, if it goes to the interrupt routine as it is, it is not known which bank to return to, so the position of the bank to be used when the processing in the interrupt routine is completed by preparing PBP5 (hereinafter referred to as the return bank number). ).

At the same time, prepare CBP4,
The position of the bank currently in use can be known, and the contents of CBP4 can be changed to PBP when bank switching occurs.
Save the return bank number by loading into 5.
When returning the bank, the value of PBP5 is loaded into CBP4.

Registers used during program execution are general-purpose registers, PC6, ISP, USP7, ES
There are P, CBP4, PBP5, CC, PSW8.

An area (bank area) for saving the general-purpose register group 3, PC6, USP7, PSW8 and PBP5 shown in FIG. 4 is secured in the bank RAM, and the sizes assigned to the banks are equal to each other. Are separated. PBP5, PC6, USP7, PSW
1 bank for saving 8 and general-purpose registers (4, 8, 1) used in processing using these dedicated registers
1 to 4 banks corresponding to the respective numbers of registers are required in order to save 2 or 16 registers depending on the processing contents).

On the other hand, when switching to the subroutine,
The switched routines are PBP5, PC6, USP
7. The PSW 8 is saved in a stack memory (last-in first-out storage device) (not shown).

Switching between banks is mainly divided into interrupt processing, subroutine call, and system call.

When switching banks by interrupt processing, first, when an interrupt condition is satisfied and an interrupt occurs, an interrupt request signal is output to the interrupt control circuit. The control circuit outputs to the processor the interrupt having the highest priority among the interrupts received at the same time. The processor receives the interrupt and outputs a permission signal to the interrupt control circuit if the generated interrupt has a higher priority than the processing currently being performed and the interrupt is permitted.

However, the non-maskable interrupt from the outside of the chip accepts the interrupt and outputs the enable signal regardless of whether the interrupt is enabled or disabled if the priority is higher than that of the process currently being performed.

The interrupt control circuit receives the enable signal, generates a vector corresponding to the interrupt request source, the microprocessor calculates the start address of the interrupt process from the vector, and writes the value in the PC6.

At the start of interrupt processing, one word written in the start address is read and referred to. Information indicating whether to switch the bank and a bank number to be switched are set in the 1 word by the program. The one word is called an interrupt mode word.

When switching banks, the contents of the current bank (general register group 3, PC6, PSW8, USP7,
PBP5) is saved in the bank RAM, the contents of CBP4 are loaded into PBP5, and the bank number used in interrupt processing is stored in CBP4. A general-purpose register is loaded from the bank RAM designated by this bank number, the bank is switched, and interrupt processing is started.

Next, when the bank is switched by a subroutine call, CAL is set in the user program.
The subroutine is called by the L instruction. USP7
PC of the bank currently used for the stack memory indicated by
6. Since PBP5 has been saved and saved in the stack memory, PBP is set to "0" and CBP4 remains unchanged. Next, the address designated by the CALL instruction is written in the PC 6, and the processing of the subroutine is started.

Since the bank is not switched in the subroutine, the CHG of the program must be switched when the bank is switched.
The BK instruction (bank switching instruction) is used. Then, only the general-purpose register is saved in the bank RAM, and a new bank number is written in CBP4. I changed the bank, but PBP5
Does not operate. When switching the banks, if the banks are shifted from 1 to 3, parameters can be passed and results can be received. On the other hand, if it is shifted by 4 or more, the banks will be switched without any overlap.

Next, when the bank is switched by the system call, the system call (software interrupt) is a non-maskable interrupt, so that the interrupt is accepted regardless of whether the interrupt is enabled or disabled. Generate a vector corresponding to the interrupt processing by the interrupt control circuit,
The start address of interrupt processing is calculated from that vector. At the same time, P used in the interrupted process
Since C6, PBP5, and PSW8 are written in the stack memory and written in the stack memory, "0" is written in PBP.
Set.

Next, the calculated start address is sent to the PC.
Write to 6. In system calls, banks are not automatically switched as in normal interrupt processing, so banks are switched by a program. Bank switching is performed by the CHGBK instruction (bank switching instruction).

First, only the general-purpose register is saved in the bank RAM, and a new bank number is written in CBP4. PB
Do not operate P5. Then, the system call is processed. Further, like the subroutine call, if the banks are shifted from 1 to 3, it becomes possible to pass parameters and receive results.

Next, when recovering from bank switching due to an interrupt, interrupt processing is completed, and the original bank is recovered by a RETI instruction (return instruction from interrupt). Load the contents of PBP5 into CBP4 and
From the bank RAM indicated by P4 to the general-purpose register 3, PC6,
Load PBP5, PSW8, USP7. As a result, the original bank can be restored.

However, if it is necessary to save the contents of the general-purpose registers used in the interrupt processing such as when the continuation is executed when the same interrupt is input next time, the contents are stored in the bank RAM before returning. Write back instructions in a program.

Next, when recovering from the bank switching by the subroutine call, the processing of the subroutine call is finished, and the program is returned to the original bank in the subroutine by the CHGBK instruction (bank switching instruction). The value of CBP4 before being switched by the program is written in CBP4, and only the general purpose register 3 is loaded from the bank RAM indicated by CBP4. As a result, the original bank can be restored.

Next, the original routine is restored by the RET instruction (return instruction from the subroutine). Since PBP5 is "0", the stack memory indicated by USP7
6. Load PBP5. At that time, if the bank overlap is set to 1 to 3, the results can be passed.

Next, when recovering from the bank switching by the system call, the processing of the system call is completed, and the original bank is recovered by the CHGBK instruction (bank return instruction). The value of CBP4 before switching by the program is written to CBP4, and the bank RA indicated by CBP4 is written.
Only general register 3 is loaded from M. This allows
You can recover to the original bank. The RETI (return instruction from interrupt routine) instruction restores the original routine.
Since PBP5 is "0", PC6, PBP5 and PSW8 are loaded from the stack memory indicated by USP7. Then, the original routine can be returned to.

As described above, when a bank is switched by a subroutine call or a system call, parameters can be transferred to the switched register bank. When register banks are overlapped and bank numbers are set when switching banks, parameters stored in general-purpose registers can be passed.

That is, parameters can be passed between the portions where the general-purpose registers overlap each other. For this reason, the time can be shortened because the process can be performed directly without using a stack memory or the like. However, in the delivery, the register number of the original register bank and the register number of the new bank differ.

Next, an embodiment of bank switching will be described with reference to FIGS.

FIG. 5 is a diagram showing an example of use of a bank,
FIG. 6 is a diagram showing the flow of processing at the time of bank switching.

Here, the system call 1 does not switch the bank, and the subroutine 2 is the system call 2. When PBP5 in use is "0", PC6, PBP
5 indicates that the PSW 8 is saved in the stack.

First, the main routine is executed. At this time, the CBP 4 has the bank number 15 being used, and the PBP 5 has been initialized to "0". Banks 15 for storing the PC 6, PBP 5, USP 7, and PSW 8 are used for the bank, and banks 16 to 19 are used for the bank RAM for storing the general-purpose register 3.

Next, when subroutine 1 is called,
The PC6 and PBP5 of the bank that has been used up to now are saved in the stack memory and saved in the stack memory.
Set "0" to P. The program address designated by the subroutine call instruction is set in the PC 6.
The bank used by the program is switched from 15 to 12. The contents of the used general-purpose register 3 are saved in the banks 16 to 19. Set CBP4 to 12,
The general registers are loaded with the values of banks 13-16. R of bank 16 used in the previous main routine
Registers 0 to R3 are stored in R12 of subroutine 1
Parameters can be directly passed from R15 to R15.

Next, when the interrupt routine 1 is generated, at the start of the routine 1, one word at the start address preset by the program is read and the interrupt routine 1 is read.
Read the bank number and size used in. At the same time, the general-purpose registers of subroutine 1 are stored in banks 13 to 1
6, PC6, PSW8, USP7, PBP5 is bank 1
Save to 2 and load 12 of the contents of CBP4 into PBP5.

The start address corresponding to the interrupt routine 1 is written in the PC 6, the bank number 1 used in the interrupt routine 1 is entered in the CBP 4, and the bank is switched. General purpose registers are loaded from bank 2 and bank 3 for use.

Next, when the interrupt routine 2 is generated, as in the case of the interrupt routine 1, at the beginning of the routine, one word at the start address preset by the program is read and the bank number used in the interrupt routine 2 is read. And read the size. At the same time, the general-purpose registers of interrupt routine 1 are banks 2 to 3, PC6, PSW8, and U.
SP7 and PBP5 are saved in bank 1 and the content 1 of CBP4 is loaded into PBP5.

The start address corresponding to the interrupt routine 2 is written in the PC 6, the bank number 8 used in the interrupt routine 2 is entered in the CBP 4, and the bank is switched. General purpose registers are loaded from bank 9 and used.

Next, when the processing of the interrupt routine 2 is completed, a return instruction from the interrupt routine 2 is generated, and C
Load BP4 with the value 1 of PBP5. Load PC6, PBP = 12, PSW8, USP7 from bank 1, load general registers from bank 2 and bank 3,
Restores the original bank. Then, the processing of the interrupt routine 1 is continued.

Next, when the processing of the interrupt routine 1 is completed, a return instruction from the interrupt routine 1 is generated, and the CBP 4 is processed in the same manner as the processing of the interrupt routine 2 is completed.
Load the value 12 of PBP5 to. Bank 12 to P
C6, PBP = 0, PSW8, USP7 are loaded, banks 13 to 16 are loaded into general-purpose registers, and the original bank 12 is restored. Then, the processing of subroutine 1 is continued.

Next, when a system call 2 is generated in the middle of the processing of the subroutine 1 and is accepted, the PC 6, PSW 8 and PBP used in the subroutine 1 =
0 is saved in the stack memory. Next, the start address corresponding to the software interrupt routine is set to PC6.
Write in.

Since the software interrupt does not automatically switch banks, the value of CBP4 remains at 12. Since it is saved in the stack memory, "0" is set in PBP. Programmatically switch banks, CBP = 1
Set to 0. General purpose registers are loaded from banks 11 and 12 and used.

Next, during the processing of the system call 2,
When the interrupt routine 3 occurs, as in the case of the interrupt routine 2, one word at the start address preset by the program is read at the beginning of the routine, and the bank number and size used in the interrupt routine 3 are read.
At the same time, the general-purpose registers of system call 2 are banks 11 to 12, PC6, PSW8, USP7, PBP.
= 0 saves to bank 10 and writes 10 of CBP4 contents to P
Load it into BP5.

The start address corresponding to the interrupt routine is written in PC6, and the interrupt routine 3 is written in CBP.
Insert the bank number 4 used in step 2 to switch the bank. Banks 5 to 7 are loaded and used as general-purpose registers.

Next, when the system call 1 is generated during the processing of the interrupt routine 3 and is accepted, PC6, PSW8, PBP = 1 used in the interrupt routine 3 are used.
0 is saved in the stack memory. Next, the start address corresponding to the software interrupt routine is set to PC6.
Write in.

The value of CBP4 does not change because the software interrupt does not automatically switch banks. Since it is saved in the stack memory, PBP is set to "0".
System call 1 does not switch banks, so C
BP remains 4, and general-purpose registers use banks 5 to 7 as they are.

Next, when the processing of the system call 1 is completed, it returns to the interrupt routine 3 by the return instruction from the interrupt. Since PBP is "0", PC6, PSW8, PBP used in interrupt routine 3 from the stack memory
= 10 is loaded. Since the banks have not been switched,
The value of CBP4 remains unchanged at 4, and the general purpose registers use banks 5 to 7 as they are, and the processing of the interrupt routine 3 is restarted.

Next, when the processing of the interrupt routine 3 is completed, a return instruction from the interrupt routine 3 is generated and C
Load BP4 with the value of 10 for PBP5. Bank 10
To PC6, PBP = 0, PSW8, and USP7 are loaded, general registers are loaded from banks 11 and 12, and the original bank 10 is restored. Then, the system call 2 is continued.

Next, when the processing of the system call 2 is completed, 12 is loaded into the CBP by the bank switching instruction of the program, and the bank 12 is restored. PBP =
Since it is 0, PC6, PBP = 0, P from the stack memory
Load SW8. Banks 13 to 16 are loaded into the general-purpose registers, and the processing of subroutine 1 is performed again.

Next, when the processing of the subroutine 1 is completed, the program loads 15 into the CBP 4 and returns the bank. Since PBP = 0, P from the stack memory
Load C6, PBP = 0. Banks 16 to 19 are loaded into the general-purpose registers, and the continuation of the main routine is restarted.

A register for holding both the value indicated by CBP and the value indicated by PBP may be provided.
As described above, according to the present invention, when accessing the return bank number, it is not necessary to access the stack memory via the low-speed external bus, so that it is possible to have a high-speed responsiveness to an interrupt.

Further, it is possible to cope with multiple interrupts without providing a plurality of sets of dedicated registers such as PCs and PSWs, and high-speed interrupt response / recovery is possible. In addition, the location of the return bank number can be selected by the value of the register holding the return bank number, so the return bank number for interrupts that do not require a fast response should be placed in the external stack memory. Can also
The RAM of the internal bank can be used efficiently. For example, if interrupt 2 that uses the same general-purpose register occurs while interrupt 1 is responding, interrupt 2
Since the PC and PSW used in step 1 are written in the bank, the PC and PSW used in interrupt 1 can be saved in the stack memory, and the bank memory can be saved by placing them in the stack memory. ..

Next, an embodiment according to the second feature of the present invention will be described. The feature of this embodiment is that the PB of the above-mentioned embodiment is used.
Instead of having P, it consists in using one bank to store the return bank number.

Here, one bank is composed of four registers as shown in FIG. 4, and consecutive one to four banks are used as general-purpose registers. PC6, PSW8, USP
1 bank is used to save 7.

Although a bank was used at an arbitrary time, when an interrupt occurred, an interrupt routine (a program for processing an interrupt) was visited to switch the bank. At that time, if it goes to the interrupt routine as it is, it is not known which bank to return to, so the bank number is stored in the bank RAM so that the bank number can be known.

At the same time, prepare CBP4,
Make sure you know the location of the bank currently in use. Further, when bank switching occurs, CBP4 is loaded into the bank RAM that stores the return bank number of the switching destination, and the position of the bank to be returned after the end is saved. Conversely, the bank can be returned by loading it into CBP4.

On the other hand, when switching to the subroutine,
The switched routines are PC6, USP7, PSW8
Are saved in the stack memory (last-in first-out storage device). Switching between banks is mainly divided into interrupt processing, subroutine call, and system call.

When switching banks by interrupt processing, first, when an interrupt condition is satisfied and an interrupt occurs, an interrupt request signal is output to the interrupt control circuit. The control circuit outputs to the processor the interrupt having the highest priority among the interrupts received at the same time. The processor receives the interrupt and outputs a permission signal to the interrupt control circuit if the generated interrupt has a higher priority than the processing currently being performed and the interrupt is permitted.

However, the non-maskable interrupt from the outside of the chip accepts the interrupt and outputs the enable signal regardless of whether the interrupt is permitted or not, if the priority is higher than that of the routine which is currently being performed.

The interrupt control circuit receives the enable signal, generates a vector corresponding to the interrupt request source, the microprocessor calculates the start address of the interrupt routine from the vector, and writes the value in the PC6.

At the beginning of the process, one word written in the start address is read to select whether to switch the bank. This one word is set by the program.

When switching the bank, the contents of the current bank (general-purpose register 3, PC6, PSW8, USP7) are saved in the bank RAM, and the contents of CBP4 are loaded as the return bank number into the bank used in the interrupt routine. The bank number used in the interrupt routine is put in CBP4. The general-purpose register 3 is loaded from the bank RAM designated by this bank number, the bank is switched, and interrupt processing is started.

Next, when the bank is switched by a subroutine call, CAL is set in the user program.
The subroutine is called by the L instruction. USP7
PC of the bank currently used for the stack memory indicated by
Since 6 has been saved and saved in the stack memory, the return bank number in the bank is set to "0" and CBP4 remains unchanged. Next, set the address specified by the CALL instruction to P
Write to C6 and start the processing of the subroutine.

When switching banks by program,
The CHGBK instruction (bank switching instruction) is used. Only the general-purpose register is saved in the bank RAM, and a new bank number is written in CBP4. I changed the bank, but PBP5
Does not operate. Then, routine processing is performed. At that time, if the banks are shifted from 1 to 3, the parameters can be passed and the results can be received. On the other hand, if it is shifted by 4 or more, the banks will be switched without any overlap.

Next, when the bank is switched by the system call, the system call (software interrupt) is a non-maskable interrupt, and therefore the interrupt is accepted regardless of whether the interrupt is enabled or disabled. The interrupt control circuit generates a vector corresponding to the interrupt routine, and calculates the start address of the interrupt routine from the vector. At the same time, the PC6 and PSW8 used in the interrupted routine are written in the stack memory, and the return bank number is set to 0 because they were written in the stack memory.

Next, the calculated start address is set to the PC
Write to 6. Since the system call does not automatically switch banks as in the normal interrupt routine, the bank is switched by the program. Bank switching is performed by the CHGBK instruction (bank switching instruction). First, save only the general-purpose registers in the bank RAM,
Write a new bank number to CBP4. Do not operate PBP5. Then, routine processing is performed. Also, like the subroutine call, if you shift the bank from 1 to 3,
Parameters can be passed and results can be received.

Next, when recovering from bank switching due to an interrupt, when the interrupt processing is completed, RETI
An instruction (return instruction from interrupt) restores the original bank. The contents of the return bank number in the bank are loaded into CBP4, and the general-purpose register 3, PC6, PSW8, and USP7 are loaded from the bank RAM indicated by CBP4. As a result, the original bank can be restored.

However, when it is necessary to retain the contents of the general-purpose registers used in the interrupt routine, for example, when the same interrupt is input next time and the continuation is to be executed,
The program issues an instruction to write the contents back to the bank RAM before returning.

Next, in the case of recovering from bank switching by a subroutine call, when the processing of the subroutine call is completed, the program is returned to the original bank in the subroutine by the CHGBK instruction (bank switching instruction). CBP4 before switching to CBP4 by program
Value is written and only the general-purpose register is loaded from the bank RAM indicated by CBP4. As a result, the original bank can be restored.

Next, the original routine is restored by the RET instruction (return instruction from the subroutine). Since the return bank number is "0", PC6 is loaded from the stack memory indicated by USP7. At that time, the bank overlap is 1
If it is set from 3 to 3, the result can be passed.

Next, when recovering from bank switching by a system call, when the system call processing is completed, the original bank is recovered by a CHGBK instruction (bank return instruction). The value of CBP4 before being switched by the program is written in CBP4, and only the general-purpose register is loaded from the bank RAM indicated by CBP4. As a result, the original bank can be restored. The RETI (return instruction from interrupt routine) instruction restores the original routine. Since the return bank number is "0", PC6 and PSW8 are loaded from the stack memory indicated by USP7. Then, the original routine can be returned to.

Next, an embodiment in which the position of the bank in which the CBP 4 stores the value indicating the position of the bank to be used after the processing is completed will be described with reference to FIGS. 7 and 8. FIG. 7 is an example of using one bank, and FIG. 8 is a diagram showing a flow of processing when switching banks.

Here, the system call 1 does not switch the bank, and the subroutine 2 is the system call 2. Also, the bank number is stored in the bank indicated by the value obtained by subtracting 1 from CBP4. When the return bank number is "0", it indicates that the PC6 and PSW8 are saved in the stack memory.

First, the main routine is executed. At this time, the number 15 of the bank being used is in the CBP 4, and the return bank number in the bank 14 is initialized to "0". PC6, USP7, P
The bank for storing SW8 is bank 15, general-purpose register 3
Banks 16 to 19 are used as the bank RAM for storing

Next, when subroutine 1 is called,
The return bank numbers in the banks PC6 and 14 of the bank that have been used up to now are saved in the stack memory, and since they have been saved in the stack memory, "0" is set to the return bank number in the bank 14. The program address designated by the subroutine call instruction is set in the PC 6. The bank used by the program is switched from 15 to 13. The contents of the used general-purpose register are saved in the banks 16 to 19. The return bank number “0” that was in the bank 14 is loaded into the bank 12. CBP is set to 13 and general registers are loaded with the values of banks 14-16.

Registers R0 to R3 of bank 16 used in the above main routine are stored in subroutine 1
Parameters can be passed directly from R8 to R11.

Next, when the interrupt routine 1 occurs, at the beginning of the routine 1, one word at the start address preset by the program is read, and the bank number and size used in the interrupt routine 1 are read. At the same time, the general-purpose registers of subroutine 1 are stored in banks 14 to 1
6, PC6, PSW8, USP7 are saved to bank 13 and 13 of the contents of CBP4 is loaded into the return bank number in bank 1.

The start address corresponding to the interrupt routine is written in PC6, and the interrupt routine 1 is written in CBP4.
Insert the bank number 2 used in step 2 to switch the bank. A general purpose register is loaded from bank 3 and used.

Next, when the interrupt routine 2 is generated, as in the case of the interrupt routine 1, at the beginning of the routine, one word at the start address preset by the program is read and the bank used in the interrupt routine 2 is read. Read the number and size. At the same time, interrupt routine 1
General-purpose registers are bank 3, PC6, PSW8, USP
7 is saved in bank 2, and 2 of the contents of CBP4 is saved in bank 8
Load the return bank number in.

The start address corresponding to the interrupt routine is written in PC6, and the interrupt routine 2 is written in CBP4.
Insert the bank number 9 used in step 1 to switch the bank. General purpose registers are loaded from bank 10 and used.

Next, when the processing of the interrupt routine 2 is completed, a return instruction from the interrupt routine 2 is generated and C
Load BP4 with the value 2 of the return bank number in bank 8. PC6, PSW8, USP7 are loaded from bank 2, general-purpose registers are loaded from bank 3, and the original bank is restored. The return bank number in bank 1 is 13
Is included. Then, the processing of the interrupt routine 1 is continued.

Next, when the processing of the interrupt routine 1 is completed, a return instruction from the interrupt routine 1 is generated, and the CBP 4 is generated in the same manner as the processing of the interrupt routine 1 is completed.
The value 13 of the return bank number in bank 1 is loaded into. PC6, PSW8, and USP7 are loaded from bank 13, banks 14 to 16 are loaded into general-purpose registers, and the original bank 13 is restored. The return bank number in bank 12 contains "0". Then, the processing of subroutine 1 is continued.

Next, when a system call 2 is generated during the processing of the subroutine 1, and this is accepted, the PC 6, PSW 8 and bank 1 used in the subroutine 1 are accepted.
The value "0" of the return bank number in 2 is saved in the stack memory. Then, the start address corresponding to the software interrupt routine is written in the PC 6.

Since the software interrupt does not automatically switch banks, the value of CBP4 remains unchanged at 13. Since it has been saved in the stack memory, the return bank number in bank 12 is set to "0". Programmatically switch banks to change CBP4 from 13 to 12. Bank 1
The return bank number “0” that was in 2 is loaded into the bank 11. The general purpose register is loaded from the bank 13 and used.

Next, during the processing of the system call 2,
When the interrupt routine 3 occurs, as in the case of the interrupt routine 2, one word at the start address preset by the program is read at the beginning of the routine, and the bank number and size used in the interrupt routine 3 are read.
At the same time, the general-purpose register of the system call 2 is saved in the bank 13, PC6, PSW8, and USP7 in the bank 12, and 12 of the contents of the CBP4 is loaded into the return bank number in the bank 4.

The start address corresponding to the interrupt routine is written in PC6, the bank number 5 used in interrupt routine 3 is entered in CBP4, and the bank is switched. General purpose registers are used by loading banks 6 to 7.

Next, when the system call 1 is generated during the processing of the interrupt routine 3 and is accepted, the return bank number 12 in the PC 6, PSW 8 and bank 4 used in the interrupt routine 3 is stored in the stack memory. Evacuate to. Then, the start address corresponding to the software interrupt routine is written in the PC 6.

The value of CBP4 does not change at 5 because the software interrupt does not automatically switch banks. Since it is saved in the stack memory, the return bank number in bank 4 is set to "0". The general purpose registers use banks 6 to 7 as they are.

Next, when the processing of the system call 1 is completed, it returns to the interrupt routine 3 by the return instruction from the interrupt. Since the return bank number in bank 4 is "0",
P used in interrupt routine 3 from stack memory
C6 and PSW8 are loaded, the bank 4 is returned, and the bank number 12 is loaded. Since the banks have not been switched,
The value of CBP4 remains unchanged at 5, the general purpose registers use banks 6 to 7 as they are, and the processing of the interrupt routine 3 is restarted.

Next, when the processing of the interrupt routine 3 is completed, a return instruction from the interrupt routine 3 is generated and C
Load BP4 with the value 12 of the return bank number in bank 4. Bank 12 to PC6, PSW8, USP7
Load general registers from bank 13,
Restores the original bank 12. The return bank number in bank 11 contains "0". Then, the system call 2 is continued.

Then, when the processing of the system call 2 is completed, the CBP is changed from 12 to 13 by the bank switching instruction of the program and is returned to the bank 13. Bank 11
Load the return number “0” in the bank 12 into the bank 12. Since the return bank number in bank 12 is "0", PC6, PSW8, and the return number "0" in bank 12 are loaded from the stack memory into bank 12. Banks 14 to 16 are loaded into the general-purpose registers, and the processing of subroutine 1 is performed again.

Next, when the processing of the subroutine 1 is completed, the CBP 4 is changed from 13 to 15 by the program and is returned to the bank 15. The return number “0” in the bank 12 is loaded in the bank 14. The return bank number in bank 14 is "0",
6. The return bank number "0" in the bank 14 is loaded into the bank 14. Banks 16 to 19 are loaded into the general-purpose registers, and the continuation of the main routine is restarted.

As described above, even if the PBP is not provided and the contents to be stored in the PBP are calculated and directly transferred to the bank memory, the same effect as that of the above-described embodiment can be obtained. Further, the register of the PBP5 is unnecessary, and the configuration can be simplified.

Further, normally, data is passed through the system bus, but according to the present invention, the CPU
The core and the bank memory 2 are connected by a dedicated bus other than the system bus. Therefore, when switching banks,
Since the contents of the general-purpose register 3 and the dedicated register are saved / restored in the bank memory 2 via the dedicated bus, high-speed data transfer can be realized. Further, by widening the width of the dedicated bus (64 bits, 128 bits), faster bank switching becomes possible.

In order to operate the second embodiment more efficiently, the third to fifth embodiments will be described below with reference to FIGS.
Shown in.

Compared with the first and second embodiments, the third to fifth embodiments
The embodiment is characterized by having a pointer that points to a dedicated register such as the PC 6 and the PSW 8 and a pointer that points to a general-purpose register separately.

FIG. 10A shows the structure of a processor according to the third embodiment of the present invention. In the third embodiment, SB is newly designated as a bank for saving the PC 6 and PSW 8.
A P (special bank pointer) 10 is provided. The operation will be described with reference to FIGS. 10 and 10C. CB
P4 and SBP10 are rewritten by instructions and interrupts. When rewriting by command, CBP4 and SBP10
Dedicated instructions that can be rewritten simultaneously are required. This is named CCBP (Change Current Bank Pointer) instruction. Two CBP4 and SBP10 are required as operands of the CCBP instruction. CBP4 and SBP1
0 can be rewritten separately by LOAD command etc.,
In that case, since the interrupt must be prohibited until both CBP4 and SBP10 are rewritten, the efficiency becomes poor. On the other hand, when rewriting with an interrupt, new values of CBP4 and SBP10 are described in the interrupt mode word in the interrupt table.

Next, the operation when an interrupt occurs while using a register exceeding the number of general-purpose registers 3 in this embodiment will be described by using 10C.

Initialization of the CBP4 and the SBP10 is performed by the interrupt mode word at the time of interruption and by the CCBP instruction at the time of task change by an instruction.
If more work registers than the number of general-purpose registers 3 are required for interrupt processing or in the task, C is issued by the LOAD instruction.
The contents of the general-purpose register 3 are updated by rewriting the BP4.
Furthermore, when a new interrupt occurs here, the contents of the general-purpose register 3 are first saved in the bank designated by CBP4, and the PC6C and PSW8 are set to SBP10.
Save to the bank specified by.

FIG. 11 shows the structure of a processor according to the fourth embodiment of the present invention.

In the fourth embodiment, a BBP (base bank pointer) 12 pointing to the bank at the base position of the work area of the register, and the PC 6 and PSW when an interrupt occurs.
It is characterized in that it has a DSR (distant to special register) 14 for holding a relative value which is a distance between the bank memory for saving 8 and the BBP 12. The operation of the fourth embodiment will be described with reference to FIGS. 11B and 11C. The CBP4, BBP12 and DSR14 are rewritten by an instruction and an interrupt. When rewriting with an instruction,
The CBP4, BBP12, and DSR14 require dedicated instructions that are simultaneously rewritten. This is called a CBBP (change base bank pointer) instruction. C
BBP12 and DSR1 as operands of BBP instruction
4 is specified, and the same value as BBP12 is loaded into CBP4. On the other hand, when rewriting by an interrupt, a new B is written in the interrupt mode word of the interrupt table.
The values of BP12 and DSR are described.

Next, with reference to FIG. 11C, the operation when an interrupt occurs while using a register exceeding the number of general-purpose registers 3 in this embodiment will be described.

The initial setting of BBP12, CBP4 and DSR14 depends on the interrupt mode at the time of interrupt, and
When the task is changed by a command, the CBBP command is used. At the time of an interrupt or in a task, if more registers than the number of general-purpose registers 3 are needed, the LOAD instruction will be issued
The contents of the general-purpose register 3 are updated by rewriting the BP4.
Furthermore, when a new interrupt occurs here, the contents of the general-purpose register 3 are first saved in the bank pointed to by CBP4, and the PC6 and PSW8 are saved in the bank pointed by BBP12 and DSR14. As a result, the fourth embodiment has an advantage that the length of the operand can be shortened as compared with the third embodiment. On the other hand, the number of registers is larger in the fourth embodiment, and when saving / restoring the PC 6 and the PSW 8, it takes extra time for the calculation by combining the information from the BBP 12 and the DSR 14.

In the fifth embodiment shown in FIG. 12, instead of the CBP4 in the fourth embodiment, a DCR (distant toe C) which holds information on the distance from the BBP to the CBP4 is used.
BP register) is provided. With such a structure, the length of the operand can be further shortened in the fifth embodiment than in the third and fourth embodiments. Further, the number of registers in the fifth embodiment can be reduced as compared with the fourth embodiment.

[0119]

As described above, according to the present invention, when the bank is switched, the information indicating the position of the return bank and the information of the dedicated register and the general-purpose register are transferred and saved without passing through the external bus. Since a plurality of sets are provided in the bank memory, the response / recovery of the interrupt processing can be performed at high speed without being restricted by the general-purpose register that can be used in the interrupt processing and the like.

By providing a plurality of sets of save areas, it is possible to deal with multiple interrupts.

Further, since the area for saving the contents of the dedicated register is selected, the bank memory can be efficiently used.

Furthermore, a bank for saving the contents of a dedicated register such as PC or PSW can be designated for each task, and pointers pointing to the dedicated register and the general-purpose register are prepared separately, so that the general-purpose register is updated by a bank change. Can be executed at high speed, and the bank can be shared within a task or between tasks, so that the bank memory can be used more efficiently.

[Brief description of drawings]

FIG. 1 is a diagram showing a main configuration of a processor according to an embodiment of a first feature of the present invention.

FIG. 2 is a diagram showing a configuration example of a condition code.

FIG. 3 is a diagram showing a configuration example of a processor status word.

FIG. 4 is a diagram showing a configuration of a register group stored in a bank RAM.

FIG. 5 is a diagram showing an example of use of a bank of an embodiment according to the first feature of the present invention.

FIG. 6 is a diagram showing a flow of processing at the time of bank switching in the usage example of the bank shown in FIG. 5;

FIG. 7 is a diagram showing a usage example of a bank of an embodiment according to the second feature of the present invention.

8 is a diagram showing a flow of processing at the time of bank switching in the usage example of the bank shown in FIG.

FIG. 9 is a diagram showing a configuration of a bank group in a conventional processor.

FIG. 10 is a diagram showing a usage example and an operation of the bank of the embodiment according to the third feature of the present invention.

FIG. 11 is a diagram showing a usage example and an operation of the bank of the embodiment according to the fourth feature of the present invention.

FIG. 12 is a diagram showing a usage example and an operation of the bank of the embodiment according to the fifth feature of the present invention.

[Explanation of Codes] 1 CPU 2 Bank memory 3 General-purpose register group 4 Current bank pointer (CBP) 5 Previous bank pointer (PBP) 6 Program counter (PC) 7 User stack pointer (USP) 8 Processor status word (PSW) 10 Special bank pointer (SBP) 12 Base bank pointer (BBP) 14 Distant to special register (DSR) 16 Distant to CBP register (DCR)

Front Page Continuation (72) Inventor Kanuma Akira 580-1 Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Semiconductor System Technology Center (72) Inventor Toshiyuki Yaguchi 580, Horikawa-cho, Kawasaki-shi, Kanagawa No. 1 Stock Company Toshiba Semiconductor System Technology Center

Claims (11)

[Claims] 1. A dedicated register for holding specific information related to program execution, a general-purpose register for holding unspecified information related to program execution, information indicating a bank currently in use, and a return bank. A processor comprising: information and a bank memory having a plurality of banks to which information held in the dedicated register and the general-purpose register is transferred without passing through an external bus. 2. A dedicated register for holding specific information related to program execution, a general-purpose register for holding unspecified information related to program execution, and a first register for holding information indicating a bank currently in use. A register, a second register that holds information indicating a return bank, and a plurality of banks to which the respective information held in the second register, the dedicated register, and the general-purpose register are transferred without passing through an external bus. A processor having a bank memory provided with a set. 3. A dedicated register for holding specific information related to program execution, a general-purpose register for holding unspecified information related to program execution, and a first register for holding information indicating a bank currently in use. A register, a first bank in which information indicating a return bank is transferred without passing through an external bus, and a second bank in which information held in a dedicated register and a general-purpose register is transferred without passing through an external bus And a calculating means for calculating information indicating the first bank based on the information held in the first register. 4. A dedicated register for holding specific information related to program execution, a general-purpose register for holding unspecified information related to program execution, and a first register for holding information indicating a bank currently in use. The register and information indicating the bank currently in use held in the first register is transferred when the process currently being executed is not finished and another process is started, and this information is returned to the bank. It is retained as the information indicating, and when the other processing is finished,
The second register to which the held information is transferred to the first register, and the second register, the dedicated register, and the general-purpose register when the currently executed process is not finished and another process is started. The information held in the register is transferred and held without passing through the external bus, and when the other processing is completed, the held information is transferred to the second register, the dedicated register and the general-purpose register by the external bus. A bank memory having a plurality of sets of banks that are transferred without passing through the processor. 5. A dedicated register for holding specific information related to program execution, a general-purpose register for holding unspecified information related to program execution, and a first register for holding information indicating a bank currently in use. The register and information indicating the bank currently in use held in the first register is transferred when the process currently being executed is not finished and another process is started, and this information is returned to the bank. It is retained as the information indicating, and when the other processing is finished,
The first bank to which the held information is transferred to the first register, and the first bank to be held in the dedicated register and the general-purpose register when the currently executed process is not finished and another process is started. A second bank in which stored information is transferred and held without passing through an external bus, and when the other processing is completed, the held information is transferred to the dedicated register and general-purpose register without passing through an external bus. And a calculating means for calculating information indicating the first bank based on the information held in the first register. 6. The processor according to claim 1, wherein when the information indicating the return bank has a specific value, the information indicating the return bank and the information of the dedicated register are transferred to a stack memory. . 7. When the information held in the second register has a specific value, the information held in the second register and the information in the dedicated register are transferred to a stack memory. The processor according to claim 2 or 4, characterized in that: 8. When the information held in the first bank has a specific value, the information held in the first bank and the information in the dedicated register are transferred to a stack memory. 6. A processor according to claim 3 or 5, characterized in that 9. The bank instructing means stores a first register for holding information indicating a bank currently in use, and a third register for indicating an address of a memory area containing an instruction word of a program.
A register and a fourth register indicating the state of the processor,
4. The processor according to claim 1, further comprising a first pointer that points to the contents of the third register and the fourth register. 10. The bank instructing means stores a first register for holding information indicating a bank currently in use, a third register for indicating an address of a memory area in which an instruction word of a program is stored, and a state of the processor. A fourth register, a second pointer that points to an address of the base bank, and a fifth register that holds distance information between the third pointer and the bank in which the contents of the third register and the fourth register are saved. Claim 1 and Claim 3 characterized by having.
Processor described in. 11. The bank instructing means includes a third register indicating an address of a memory area containing an instruction word of a program, a fourth register indicating a state of a processor, and a second pointer indicating an address of a base bank. 4. The processor according to claim 1, further comprising means for holding distance information between the second pointer and the first register.