JPH05211233A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05211233A JPH05211233A JP720092A JP720092A JPH05211233A JP H05211233 A JPH05211233 A JP H05211233A JP 720092 A JP720092 A JP 720092A JP 720092 A JP720092 A JP 720092A JP H05211233 A JPH05211233 A JP H05211233A
- Authority
- JP
- Japan
- Prior art keywords
- film
- element isolation
- oxide film
- silicon nitride
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000002955 isolation Methods 0.000 claims abstract description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- -1 boron ions Chemical class 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 210000003323 beak Anatomy 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000010408 film Substances 0.000 description 64
- 241000293849 Cordylanthus Species 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000013039 cover film Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に選択酸化法による素子分離酸化膜の形成法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation oxide film by a selective oxidation method.
【０００２】[0002]
【従来の技術】従来の半導体装置の製造工程における素
子分離酸化膜の形成方法を図４を用いて説明する。2. Description of the Related Art A conventional method for forming an element isolation oxide film in a semiconductor device manufacturing process will be described with reference to FIG.
【０００３】まず図４（ａ）に示すように、シリコン基
板１上にパッド酸化膜（ＳｉＯ2 ）２Ａと窒化シリコン
膜（Ｓｉ3 Ｎ4 ）３Ａを形成した後、窒化シリコン膜を
パターニングし素子分離領域に開口部を設ける。次でこ
の窒化シリコン膜３Ａをマスクとして熱酸化し素子分離
酸化膜７Ｂを形成する。First, as shown in FIG. 4A, after a pad oxide film (SiO 2 ) 2A and a silicon nitride film (Si 3 N 4 ) 3A are formed on a silicon substrate 1, the silicon nitride film is patterned to form an element. An opening is provided in the separation area. Then, the silicon nitride film 3A is used as a mask to perform thermal oxidation to form an element isolation oxide film 7B.
【０００４】次に図４（ｂ）に示すように、素子分離領
域以外の窒化シリコン膜３Ａ及びパッド酸化膜２Ａを除
去する。Next, as shown in FIG. 4B, the silicon nitride film 3A and the pad oxide film 2A other than the element isolation region are removed.
【０００５】[0005]
【発明が解決しようとする課題】デバイスの高集積化が
進むにつれ素子分離領域の縮小化、つまり選択酸化法に
よる素子分離酸化膜７Ｂの横方向の広がり（バーズビー
ク）の縮小化が要求されてきている。そのため、従来の
選択酸化による素子分離酸化膜の形成方法では、バーズ
ビークを縮小にするため窒化シリコン膜を厚くし、パッ
ド酸化膜を薄くする必要がある。パッド酸化膜の薄膜化
及び窒化シリコン膜を厚くすることにより、バーズビー
クの縮小は認められるものの、窒化シリコン膜のもたら
す応力がパッド酸化膜で緩和することができないため、
シリコン基板に欠陥を発生させデバイス特性を劣下させ
るという欠点がある。As device integration becomes higher, it is required to reduce the element isolation region, that is, the lateral expansion (bird's beak) of the element isolation oxide film 7B by the selective oxidation method. There is. Therefore, in the conventional method of forming an element isolation oxide film by selective oxidation, it is necessary to thicken the silicon nitride film and thin the pad oxide film in order to reduce the bird's beak. By reducing the pad oxide film and thickening the silicon nitride film, the bird's beak can be reduced, but the stress caused by the silicon nitride film cannot be relaxed by the pad oxide film.
There is a drawback that defects are generated in the silicon substrate and the device characteristics deteriorate.
【０００６】また、チャンネルストッパーとして所望の
不純物をイオン注入する場合、パッド酸化膜を介してシ
リコン基板に注入し欠陥の発生を抑制していたが、パッ
ド酸化膜が薄くなると、窒化シリコン膜除去の際、パッ
ド酸化膜が同時に除去されベアー注入となり、基板に欠
陥が多量に発生するという欠点がある。Further, when a desired impurity is ion-implanted as a channel stopper, the generation of defects is suppressed by implanting it into the silicon substrate through the pad oxide film. However, when the pad oxide film becomes thin, the silicon nitride film is removed. At this time, the pad oxide film is removed at the same time and bare injection is performed, which causes a large number of defects on the substrate.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、シリコン基板上に薄い酸化シリコン膜と窒化
シリコン膜を順次形成したのち素子分離領域の少くとも
前記窒化シリコン膜を選択的に除去する工程と、前記窒
化シリコン膜の側壁に絶縁膜からなるサイドウォールを
形成した後全面にポリシリコン膜を形成する工程と、前
記ポリシリコン膜上よりチャンネルストッパーとして所
望の不純物をイオン注入した後前記素子分離領域を選択
的に酸化し素子分離酸化膜を形成する工程とを含むもの
である。According to a method of manufacturing a semiconductor device of the present invention, a thin silicon oxide film and a silicon nitride film are sequentially formed on a silicon substrate, and then at least the silicon nitride film in an element isolation region is selectively formed. A step of removing, a step of forming a side wall made of an insulating film on the side wall of the silicon nitride film, a step of forming a polysilicon film over the entire surface, and a step of ion-implanting desired impurities as a channel stopper from above the polysilicon film. And a step of selectively oxidizing the element isolation region to form an element isolation oxide film.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ），（ｂ）は本発明の第１の実施例を説明
するための半導体チップの断面図である。The present invention will be described below with reference to the drawings. 1A and 1B are cross-sectional views of a semiconductor chip for explaining the first embodiment of the present invention.
【０００９】まず図１（ａ）に示すように、低濃度Ｐ型
の面方位（１００）を有するシリコン基板１上に、パッ
ド酸化膜２を４５ｎｍ，窒化シリコン膜３を３００ｎｍ
の厚さに形成する。次で素子分離領域上の窒化シリコン
膜３をパターニングし開口部を設けた後、この窒化シリ
コン膜３の側壁にサイドウォール４として窒化シリコン
膜を形成する。このサイドウォール４が横方向の酸化過
程を抑制し、素子分離領域の横方向広がりを小さくす
る。更に実際のマスク設計寸法より小さい素子分離領域
が形成されるわけである。その後、サイドウォール４上
にカバー膜およびイオン注入保護膜として、ポリシリコ
ン膜５を約１００ｎｍの厚さに形成する。その後チャン
ネルストッパーとしてボロンイオン６を５０ｋｅｖ，ド
ーズ量１．５×１０13ｃｍ-2の条件でポリシリコン膜５
を介してシリコン基板１に注入する。その際、ポリシリ
コン膜５は注入損傷を緩和させる保護膜となる。First, as shown in FIG. 1A, a pad oxide film 2 of 45 nm and a silicon nitride film 3 of 300 nm are formed on a silicon substrate 1 having a low-concentration P-type plane orientation (100).
To the thickness of. Next, after the silicon nitride film 3 on the element isolation region is patterned to form an opening, a silicon nitride film is formed as a sidewall 4 on the side wall of this silicon nitride film 3. The sidewall 4 suppresses the lateral oxidation process and reduces the lateral expansion of the element isolation region. Furthermore, an element isolation region smaller than the actual mask design size is formed. Then, a polysilicon film 5 having a thickness of about 100 nm is formed on the sidewall 4 as a cover film and an ion implantation protection film. Then, the polysilicon film 5 is used as a channel stopper under the conditions of 50 keV of boron ion 6 and a dose of 1.5 × 10 13 cm -2.
It is injected into the silicon substrate 1 through. At this time, the polysilicon film 5 serves as a protective film that relieves the implantation damage.
【００１０】次に図１（ｂ）に示すように、１０００
℃、２時間、ウエット酸化を行ない、素子分離酸化膜７
を形成する。以下図１（ｃ）に示すように、ウエットエ
ッチング法等により窒化シリコン膜３等を除去し、酸化
膜７からなる素子分離領域を完成させる。Next, as shown in FIG.
Wet oxidation is performed at ℃ for 2 hours, and the element isolation oxide film 7
To form. As shown in FIG. 1C, the silicon nitride film 3 and the like are removed by a wet etching method or the like to complete the element isolation region made of the oxide film 7.
【００１１】従来の技術と比較するため図３に素子分離
領域の横方向広がりの素子分離酸化膜厚依存性を示す。
従来技術による素子分離領域の横方向の広がりに比べ、
本実施例では、素子分離酸化膜７のバーズビークが抑制
されるため素子分離領域の横方向広がりは小さく、本実
施例の優位性が認められる。For comparison with the prior art, FIG. 3 shows the dependence of the lateral expansion of the element isolation region on the element isolation oxide film thickness.
Compared to the lateral expansion of the element isolation region according to the conventional technology,
In this embodiment, since bird's beak of the element isolation oxide film 7 is suppressed, the lateral extension of the element isolation region is small, and the superiority of this embodiment is recognized.
【００１２】図２（ａ）〜（ｃ）は本発明の第２の実施
例を説明するための半導体チップの断面図である。FIGS. 2A to 2C are sectional views of a semiconductor chip for explaining the second embodiment of the present invention.
【００１３】まず図２（ａ）に示すように、低濃度Ｐ型
の面方位（１００）を有するシリコン基板１上に、パッ
ド酸化膜２を２０ｎｍ，窒化シリコン膜３を３００ｎｍ
の厚さに形成する。次で素子分離領域上の窒化シリコン
膜３をパターニングした後、その側壁にサイドウォール
４として窒化シリコン膜を形成する。その後、これら窒
化シリコン膜３，４をマスクとしてシリコン基板１に溝
１０を１００ｎｍの深さで形成する。その際、ドライエ
ッニングの異方性を弱め、溝１０の側壁が傾くようにす
る。その後、カバー膜およびイオン注入保護膜として、
ポリシリコン膜５Ａを１００ｎｍの厚さに堆積させる。
その後、ボロンイオン６をポリシリコン膜５Ａを介して
シリコン基板１に注入する。First, as shown in FIG. 2A, a pad oxide film 2 of 20 nm and a silicon nitride film 3 of 300 nm are formed on a silicon substrate 1 having a low-concentration P-type plane orientation (100).
To the thickness of. Next, after patterning the silicon nitride film 3 on the element isolation region, a silicon nitride film is formed as a sidewall 4 on the side wall thereof. Then, using the silicon nitride films 3 and 4 as a mask, the groove 10 is formed in the silicon substrate 1 to a depth of 100 nm. At that time, the anisotropy of dry etching is weakened so that the sidewall of the groove 10 is inclined. After that, as a cover film and an ion implantation protection film,
A polysilicon film 5A is deposited to a thickness of 100 nm.
Then, boron ions 6 are implanted into the silicon substrate 1 via the polysilicon film 5A.
【００１４】次に図２（ｂ）に示すように、ウエット酸
化により素子分離酸化膜７Ａを形成したのち、図２
（ｃ）に示すように、窒化シリコン膜３等をウエットエ
ッチング法で除去する。Next, as shown in FIG. 2B, an element isolation oxide film 7A is formed by wet oxidation, and then, as shown in FIG.
As shown in (c), the silicon nitride film 3 and the like are removed by a wet etching method.
【００１５】このように第２の実施例によれば、溝１０
の形成により素子分離酸化膜７Ａが深く形成されるた
め、第１の実施例に比べバーズビークを更に小さくでき
る利点がある。As described above, according to the second embodiment, the groove 10
Since the element isolation oxide film 7A is deeply formed by the formation of the above, there is an advantage that the bird's beak can be further reduced as compared with the first embodiment.
【００１６】[0016]
【発明の効果】以上説明したように本発明は、シリコン
基板上の絶縁膜の側壁にサイドウォールを形成し、その
上にカバー膜およびイオン注入保護膜として、ポリシリ
コン膜を形成した後、チャンネルストッパーとして所望
の不純物をイオン注入した後、素子分離領域を酸化させ
ることにより、酸化膜からなる素子分離領域の横方向広
がりを少くできるという効果がある。更にイオン注入よ
る欠陥の発生を抑制できるという効果もある。As described above, according to the present invention, a sidewall is formed on the side wall of an insulating film on a silicon substrate, a polysilicon film is formed thereon as a cover film and an ion implantation protection film, and then a channel is formed. After the desired impurities are ion-implanted as a stopper, the element isolation region is oxidized, so that the lateral spread of the element isolation region made of an oxide film can be reduced. Further, there is an effect that the generation of defects due to ion implantation can be suppressed.
【図１】本発明の第１の実施例を説明するための半導体
チップの断面図。FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための半導体
チップの断面図。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.
【図３】実施例の効果を説明するための素子分離領域の
横方向広がりの酸化膜厚依存性を示す図。FIG. 3 is a diagram showing the oxide film thickness dependence of the lateral expansion of the element isolation region for explaining the effect of the embodiment.
【図４】従来例を説明するための半導体チップの断面
図。FIG. 4 is a cross-sectional view of a semiconductor chip for explaining a conventional example.
１ シリコン基板 ２，２Ａ パッド酸化膜 ３，３Ａ 窒化シリコン膜 ４ サイドウォール ５，５Ａ ポリシリコン膜 ６ ボロンイオン ７，７Ａ，７Ｂ 素子分離酸化膜 １０ 溝 1 Silicon Substrate 2, 2A Pad Oxide Film 3, 3A Silicon Nitride Film 4 Sidewall 5, 5A Polysilicon Film 6 Boron Ion 7, 7A, 7B Element Isolation Oxide Film 10 Groove
Claims (2)
窒化シリコン膜を順次形成したのち素子分離領域の少く
とも前記窒化シリコン膜を選択的に除去する工程と、前
記窒化シリコン膜の側壁に絶縁膜からなるサイドウォー
ルを形成した後全面にポリシリコン膜を形成する工程
と、前記ポリシリコン膜上よりチャンネルストッパーと
して所望の不純物をイオン注入した後前記素子分離領域
を選択的に酸化し素子分離酸化膜を形成する工程とを含
むことを特徴とする半導体装置の製造方法。1. A step of sequentially forming a thin silicon oxide film and a silicon nitride film on a silicon substrate, and then selectively removing at least the silicon nitride film in an element isolation region, and an insulating film on a sidewall of the silicon nitride film. A step of forming a polysilicon film over the entire surface after forming a sidewall made of, and ion-implanting desired impurities as a channel stopper from above the polysilicon film, and then selectively oxidizing the element isolation region to form an element isolation oxide film. And a step of forming a semiconductor device.
溝を形成した後ポリシリコン膜を形成する請求項１記載
の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein a polysilicon film is formed after forming a shallow groove in the silicon substrate between the sidewalls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP720092A JP2707901B2 (en) | 1992-01-20 | 1992-01-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP720092A JP2707901B2 (en) | 1992-01-20 | 1992-01-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05211233A true JPH05211233A (en) | 1993-08-20 |
| JP2707901B2 JP2707901B2 (en) | 1998-02-04 |
Family
ID=11659390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP720092A Expired - Lifetime JP2707901B2 (en) | 1992-01-20 | 1992-01-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2707901B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403770A (en) * | 1993-04-22 | 1995-04-04 | Hyundai Electronics Industries Co., Ltd. | Method for forming a field oxide film in a semiconductor device |
| JPH0851104A (en) * | 1993-12-27 | 1996-02-20 | Natl Science Council Of Roc | Improved method for growing oxide layer in zoned silicon oxidation method |
-
1992
- 1992-01-20 JP JP720092A patent/JP2707901B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5403770A (en) * | 1993-04-22 | 1995-04-04 | Hyundai Electronics Industries Co., Ltd. | Method for forming a field oxide film in a semiconductor device |
| JPH0851104A (en) * | 1993-12-27 | 1996-02-20 | Natl Science Council Of Roc | Improved method for growing oxide layer in zoned silicon oxidation method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2707901B2 (en) | 1998-02-04 |
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| Date | Code | Title | Description |
|---|---|---|---|
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Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970916 |