JPH0521367B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to an improvement in a logic system, and particularly to a logic system that can be easily made fail-safe. [Background of the invention] For example, ATC (automatic train control device) for railway vehicles
Since these systems aim to prevent train collisions, protect human lives, and prevent serious damage, a high degree of fail-safe performance is required. For this reason, the circuits that make logical decisions have a multi-system configuration, and the outputs of each system are collected and the final output is determined by a fail-safe matching circuit or majority circuit. Here, in addition to making each logic circuit fail-safe, we also configured a multiplex system for these circuits to ensure complete safety. However, the majority circuit is a single system, and its fail-safety is largely related to the fail-safety of the entire device. For this reason, efforts are being made to construct fail-safe majority voting circuits, but at present only electromagnetic relays are used, which lags behind in terms of miniaturization, weight reduction, and power saving of devices. The reason why electromagnetic relays provide fail-safe properties is as follows. Failures in electromagnetic relays can be divided into contact continuity failures and non-continuity failures, but in general, the probability of occurrence of a continuity failure is less than 1/1000 of that of a non-continuity failure. This is because the cause of a continuity failure is only the welding of the contacts, whereas the cause of a non-continuity failure is poor contact due to dirt or oxidation of the contacts, disconnection or internal short circuit of the drive coil, failure of the drive power supply, breakage of the movable piece, etc. It is for a great deal. Furthermore, in order to prevent contact welding, if the contact current is suppressed below the welding limit, the only failure mode can be considered to be a non-conducting failure. Therefore, if the conduction of the contacts is made to be the control output on the dangerous side and the non-conduction side is made to be the control output on the safe side, the electromagnetic relay can be used as a fail-safe logic element. On the other hand, in the case of a semiconductor element, the probability of occurrence of a failure in a conductive state and a failure in a non-conductive state are approximately equal. In the case of semiconductors, diffusion of impurities, deterioration due to heat,
This is because failures caused by similar causes, such as breakage or contact of lead wires, short circuit or melting due to overcurrent or overvoltage, can result in either conduction or nonconduction. For this reason, in semiconductors, it is impossible to specify the logic values on the fail-safe side and the fail-out side, as is the case with electromagnetic relays, and any circuit that is constructed by combining basic logic elements, such as what is generally called random logic, can be used in any circuit. It is considered extremely difficult to make a semiconductor logic element fail-safe. [Object of the Invention] An object of the present invention is to provide a logic system that is easy to reduce in size and weight, has excellent fail-safe properties, and has a high degree of freedom in use. [Summary of the Invention] The present invention inputs a plurality of alternating signals having different frequencies for each input truth value including a positive logic "1" and a negative logic "0", and calculates a predetermined difference between the input frequency values. The truth value to be output is determined based on whether or not the result of the calculation is within the expected reference frequency band, and an alternating signal having a frequency corresponding to the corresponding output truth value is output, and an alternating signal to be output with the above calculation result. The feature is that it is possible to change the setting of the correspondence relationship with the frequency. In other words, by setting the frequency of the alternating signal to a logical value, it is possible to extremely reduce the probability that a dangerous output will be produced in the event of a self-failure, and also because a normal logic element makes a judgment regarding an abnormal input. ,
It is possible to reliably generate a safe output in the form required. In addition, before the frequency band determination described above, by performing a predetermined operation, such as addition, between the frequency values of two or more input alternating signals, commonly used AND, OR, NAND, NOR, EOR, etc. In addition to the above logic elements, it is also possible to construct a logic circuit based on a combination of these elements, such as a majority circuit, all at once. The principles of the invention will be explained in more detail in the examples described below. [Embodiment of the Invention] FIG. 1 shows a positive logic “1” according to an embodiment of the present invention.
This figure shows the distinction between a negative logic "0" and a negative logic "0" in comparison with an example of a conventional logic signal. Figure A shows electrical signals representing positive logic "1" and negative logic "0" in conventional binary logic. For example, a voltage of 5V represents positive logic "1" and 0V represents negative logic. It shows “0”. On the other hand, Figure B is an example of the logic signal according to the present invention, in which the 300Hz alternating signal is a positive logic
, the 50Hz alternating signal represents negative logic "0". In this way, different truth values are expressed depending on the difference in frequency.
It is shown in Figs. Figure 2 is an example of the simplest frequency band division, with bands higher than any frequency ₁ being positive logic, ₁
The lower band is defined as negative logic. Figure 3 uses three-value logic, and in addition to positive and negative logic,
A band that indicates an abnormal state is set, and a band higher than any frequency ₁ is defined as positive logic, a band between ₁ and ₂ is negative logic, and a band lower than ₂ is defined as an abnormal state. In FIG. 4, positive and negative logic during normal operation are limited to different specific frequency bands, and all other bands are defined as an abnormal state. i.e. 575-625Hz band centered around 600Hz and 350Hz
The 325-375Hz band centered on is positive logic, and 100Hz
The 75 to 125 Hz band centered around is defined as negative logic, and all other bands are defined as abnormal conditions. FIG. 5 shows a block diagram of a logic scheme according to one embodiment of the invention. The logic element 2 has an input terminal 4 and an output terminal 6, and is internally equipped with a frequency band determination section 8 and an alternating signal generation section 10. When an alternating signal is input to the terminal 4, the determination unit 8 performs band determination of the frequency,
The truth value to be output is transmitted to the alternating signal generator 10. The alternating signal generating section 10 generates an alternating signal of a frequency corresponding to the given output truth value, and outputs an alternating signal to the terminal 6.
Output to. Now, suppose this logic element 2 is a NOT element,
If positive logic for both input and output is defined as frequency band _P , negative logic as frequency band _N , and other frequency bands _E as abnormal states, the operation will be as shown in Table 1.

[Table] In Table 1, truth values are shown in brackets. In this way, by outputting the alternating signals of the frequencies shown in Table 1 in response to the three different determination results of the band determination section 8, the logic element 2 is configured to NOT
(Inversion) It can function as an element. At this time, the probability of erroneously determining that the frequency of the input alternating signal is a frequency that represents an erroneous truth value is extremely low, and it is also easy to narrow the frequency band for band determination that produces a dangerous output. , it is possible to improve fail-safe properties. Furthermore, even if the alternating signal generator fails, the probability of generating an alternating signal with a frequency corresponding to a specific dangerous truth value is also extremely low, making it impossible to obtain a highly fail-safe logic element. can. Of course, it is not necessary that the frequencies corresponding to the input truth value and the output truth value be the same; they may be reversed,
It is also possible to allocate different frequency bands to each. In the present invention, the settings of the band determining section 8 can be changed. For example, when it is determined that the frequency band _E indicates an abnormality, instead of outputting the frequency _E that indicates the abnormality, output the frequency _N that indicates the truth value on the safe side.
Alternatively, fail-safety can be maintained even if _P is output. FIG. 6 is a block diagram of a logic scheme according to another embodiment of the present invention. This logic element 12 differs from the one shown in FIG. 5 in that it is equipped with another input terminal 5 and an arithmetic unit 7, and in addition to the NOT element described above, it has a two-input type.
OR, AND, EOR, NOR, NAND elements, etc. can be configured. The calculation unit 7 performs a predetermined calculation between the frequency values of the two alternating signals applied to the input terminals 4 and 5. This operation may be addition, subtraction, multiplication, or division, but if addition is taken as an example as the most desirable embodiment, the logic element 12 performs operations as shown in Table 2. Note that changing the settings of the band determining section 8 will be described later for convenience of explanation.

[Table] Here, regarding the NOT element, the fifth
In addition to being able to be constructed using the logic element 12 without the arithmetic unit 7 shown in the figure, it is also possible to use Table 1 without using one of the two input terminals 4 and 5 shown in FIG. However, as another example, a case where input terminals 4 and 5 are commonly connected is shown here.
In this case, the input is unified to one of the frequencies _P , _N , or _E , and in order to add these, 2 _P ,
There are only 3 options: 2 _N or 2 _E. Therefore, when those frequency band determinations are obtained, _N and
It is sufficient to output an alternating signal with a frequency of _P or _E. Next, to explain specifically using an OR element as an example, input positive logic _P = 300Hz, input negative logic _N = 50Hz
Then, the band determination section 8 of the OR element in Table 2 is
The operation shown in FIG. 4 described above may be performed. That is,
In term No. 1 of Table 2, the addition result is _a = 2 _P = 600 Hz, which is determined to be positive logic, and a frequency _P = 300 Hz corresponding to the output positive logic is output. Also, the section in Table 2
In No. 2 and 3, _a = _P + _N = 350Hz,
After all, it is determined to be positive logic, and a frequency _P = 300Hz corresponding to the output positive logic is output. In term No. 4, _a =
2 _N = 100Hz, it is determined to be negative logic, and an alternating signal with a frequency _N = 50Hz corresponding to the output negative logic is output. In the following items No. 5 to 9, since the abnormal frequency _E is included, it is possible to output a frequency _E (for example, 0 Hz) that is a frequency band other than the above three bands and represents "abnormality". It is clear that AND, EOR, NOR, and NAND elements can be constructed by similarly generating output signals as shown in Table 2 in accordance with the frequency band determination results. FIG. 7 is a block diagram of another embodiment of the present invention, which achieves even more complete fail-safety. The logic element 13 includes two input terminals 4 and 5, a calculation unit 7 that performs calculations such as addition between the frequencies of the alternating signals input to these terminals, and a band determination unit 8 that performs frequency band determination of the calculation result 14. and its judgment signal 1
It is provided with an alternating signal generating section 10 that generates a frequency corresponding to the output truth value of No. 5, and an output terminal 6, and further has a failure detection circuit signal 16 and its output terminal 17. In such a configuration, the logical method is
This is the same as in FIG. 6 above, but when both the band determining section 8 and the alternating signal generating section 10 are normal,
The failure detection cycle signal 16 is made to be an alternating signal of a predetermined frequency, and as long as this signal 16 appears at the terminal 17, the logic element 13 is defined as being normal. The embodiment shown in FIG. 7 will be explained in more detail below. FIG. 8 is a block diagram showing the embodiment of FIG. 7 in more detail. This embodiment is called ring calculation, and employs a calculation method that is a modification of DDA (Direct Differential Analyzer). This ring calculation method is widely used in the field of ATC, and is well known and described in detail in the specifications of Japanese Patent No. 923327, Japanese Patent No. 964816, Japanese Patent No. 1072745, and the like. Now, the logic element 13 is composed of a calculation section 7, a band judgment section 8, and an alternating signal generation section 10, but the band judgment section 8 and the alternation signal generation section 10 share the same calculation route in a time-sharing manner. ing. Note that in this embodiment, the calculation unit is shared by time-sharing calculation, so
It is difficult to label the determination signal 15 and the circulating signal 16 in FIG. 7 in exact correspondence. In order to add the frequencies of the alternating signals given to the input terminals 4 and 5, the arithmetic unit 7 of this embodiment includes sampling circuits 18 and 20 and an exclusive OR EOR.
It is equipped with 22. Each sampling circuit 18 and 20 receives out-of-phase clock signals 26 and 28, respectively, from a clock generation circuit 24, thereby ensuring that the rising and falling edges of the two input alternating signal waveforms are staggered. As a result, EOR22 is
It is possible to output an alternating signal 14 having a frequency that is reliably the sum of the frequencies of two input alternating signals. The frequency band determination section 8 is basically configured as follows. That is, the frequency-added alternating signal 14 is the alternating signal 32 having the reference frequency generated by the alternating signal generating circuit 30.
The frequency comparison circuit 34 performs a band determination. At this time, in order to make determinations in a plurality of frequency bands as illustrated in FIG.
4 also compares the alternating signal 14 with a plurality of reference alternating signals 32 in a time-division manner to enable band determination. Therefore, the frequency band is determined depending on the timing at which the magnitude comparison determination signal 36 of the frequency comparison circuit 34 is generated. Next, the alternating signal generating section 10 performs the above-mentioned band judgment in a time-division manner, and uses the alternating signal generating circuit 30 in common to generate an alternating signal having a frequency corresponding to the output truth value according to the band judgment result. It causes it to occur. The details will be explained below. A clock signal 38 generated by the clock signal generating circuit 24 is converted into an address signal 42 by an address circuit 40, and the device repeats high-speed calculations in units of one address cycle (ring calculation) using this address signal. Address signal 42 is input to timing circuit 44, which generates a plurality of timing signals 46, 48, 50, and 52 necessary for time-sharing operations. The memory 54 stores the data shown in FIG.
Accordingly, data strings 56 and 58 can be read, respectively. The data string 56 is obtained by time-divisionally reading out data representing a plurality of reference frequencies ₁₀ to _7, respectively, and is inputted to the alternating signal generation circuit 30 via the data switching circuit 60. As a result, the alternating signal generation circuit 30 can generate multiple different reference frequencies.
₁₀ to ₇ are generated in time division. This provides the reference value for the frequency comparison described above. As mentioned above, the result of this comparison depends on the timing of generation of the determination signal 36. Therefore, at the timing when this judgment signal 36 is generated, one data in the data string 58 is latched, and an alternating signal having a frequency (corresponding to the output truth value) expressed by the latched data is generated. In other words, as shown in FIG. 9, the data string 58 has a frequency _P corresponding to positive logic,
Data representing a frequency _N corresponding to negative logic and a frequency _E corresponding to an abnormality are sequentially read out, and one of the above data is latched into the latch circuit 62 depending on the timing at which the judgment signal 36 is generated. This latched data then represents the result of band determination. Latch data _P , _N or
_E is transmitted to the alternating signal generating circuit 30 by the data switching circuit 60 at a time slot to which an output function within one address period is assigned, and is an alternating signal having a frequency _P , _N , or _E corresponding to the truth value to be output. 32 can be generated. Of the alternating signals 32, only those generated at the above timing should be output, so they are regulated by the timing signal 50 and output from the logic output circuit 64 to the output terminal 6. Error detection circuit 66 and failure detection output circuit 6
8 also operates in one allocated time division slot, but the details will be described in the detailed explanation of the operation. Next, the specific operation will be explained using the case of an OR element as an example, with reference to FIG. One period t of the address signal 42 is divided into six time slots _t1 to _t6 , and functions are assigned to each time slot. In this example, in FIG. 10, the frequency band determination function is assigned to time slots _t1 to _t4 , and the function of generating an alternating signal to be output is assigned to time slot _t5 . Additionally, the final time slot _t6 is assigned a failure detection function to ensure complete fail-safety. The data stored in the memory 54 as shown in FIG. 9 is sequentially read out in parallel as data columns 56 and 58 at each time slot t ₁ -t ₆ represented by the address signal 42. The following processing steps are all based on the timing signals 46, 4 generated by the timing circuit 44.
8, 49, 50 and 52. First, in four time slots _t1 to _t4 ,
An alternating signal generating circuit 30 generates alternating signals of four different frequencies, ₁₀ to ₇ . That is, in FIG. 9, stored data strings 56 corresponding to frequencies ₁₀ to ₇ are read from the memory 54 at time slots _t1 to _t4, respectively, and are applied to the alternating signal generation circuit 30 through the data switching circuit 60. The address period t is, for example, 96 μs, and each time slot t ₁ to t ₆ occurs once every 96 μs. Therefore, if a pulse is output every time the corresponding slot appears, an alternating signal with a frequency of 1/96 μs≈10 KHz will be generated. Now, if you want to generate a 5KHz alternating signal, you can output a pulse every time the corresponding slot appears twice, that is, divide the frequency by 1/2. In this way, by dividing the frequency of the corresponding slot, an alternating signal of the frequency represented by the stored data ₁₀ to ₇ can be generated for each slot. As a result, as shown in FIG. 10, _the output ₃₂ of the alternating signal generation circuit 30 is
Each has a different frequency, ₁₀ = 620Hz, ₉
= 330Hz, ₈ = 120Hz, ₇ = 90Hz. The frequency comparison circuit 34 is supplied with the output 32 of the alternating signal generation circuit 30 and the frequency addition signal 14 of the alternating signals applied to the input terminals 4 and 5, and compares the frequencies between the two for each slot. . Note that the addition signal 14 is a signal that does not alternate within one address period t. The input frequency of positive logic is _P = 300Hz, the input frequency of negative logic is _N = 50Hz, and the frequency that occurs when the logic element in the previous stage that supplies input to this logic element is abnormal is _E =
Set to 0Hz. Here, the frequency comparison circuit 34 employs the ring calculation method described in the above-mentioned patent specification. Let's explain its operation. Now, let's focus on time slot _t1 . High speed (96μs
Among the time slots t ₁ that appear one after another in
Signal 32 is "1" (positive) only in the divided slot corresponding to ₁₀ = 620 Hz. On the other hand, the other input 14 has a frequency that is the sum of inputs 4 and 5, and if this is _2P , all slots t ₁
Of these, the signal 14 becomes "1" (positive) only in the divided slot corresponding to _2P = 600Hz. These two input pulse trains 32 and 14 are compared in frequency within time slot _t1 by up-counting with one pulse and down-counting with the other pulse, and when the difference between them reaches a predetermined value, this time slot An output signal 36 is generated within lot _t1 . In this example, signal 32 is 620
Hz and signal 14 is 600 Hz, signal 32>signal 14, and when the integrated value of the frequency difference reaches the predetermined value, the determination signal 36 becomes "1" in slot _t1 . As mentioned above, this calculation is extremely fast, and in the above example, the decision signal ₃ at time slot t1
It takes only a few ms for 6 to become "1". Similarly, the alternating signals 32 and 14 are compared in time slots _t2 to _t4 , but the input alternating signal 14 on the other side has the same frequency as that in time slot _t1 . On the other hand, one input alternating signal 32 changes every time slot _t1 to _t4 , as shown in FIG. The result of the frequency comparison at each time slot is identified by a decision signal 36 for each slot. In this way, the judgment signal 36 representing the frequency comparison result is obtained, and its falling edge, that is, the change from "1" to "0", is selectively extracted by the timing signal 46, and the latch circuit 62 is triggered. do.
At this time, if the alternating signal applied to input terminal 4 or 5 does not include the frequency _E = 0Hz, the judgment signal 36 is output at time slot t ₂ or t ₄ .
is always “0”. Until the time slot before that, all the determination signals 36 are "1". This is because in terms No. 1 to 3 in Table 2, 2 _P =
Since it is 600Hz or _P + _N = 350Hz, the reference frequency is between ₁₀ = 620Hz and ₉ = 330Hz, and the judgment signal 36 is "1" at slot _t1 .
At _t2 , the determination signal 36 becomes "0". Also, the second
In term No. 4 in the table, 2 _N = 100Hz, so
The reference frequency is between ₈ = 120Hz and ₉ = 90Hz,
The determination signal 36 should be "1" up to slot _t3 , and should be "0" at slot _t4 . Therefore, the data 58 latched in the latch circuit 62 by the falling edge trigger of the determination signal 36
In the above items No. 1 to 3, the time slot
At time slot _t2 , data _P is present, and in term No. ₄ , data _N is present at time slot t4. Furthermore, if the judgment signal 36 falls at time slot t ₃ other than time slots t ₂ and t ₄ , it means that there is an abnormality before this frequency band judgment, and in that case, data _E must be latched. become. Data _P , _N or _E of the data string 58 in the latched memory 54 is stored in the time slot.
At t ₅ , the data is transferred from the data switching circuit 60 to the alternating signal generation circuit 30 . Therefore, the alternating signal generating circuit 30 generates an alternating signal of frequency _P (positive logic), frequency _N (negative logic), or frequency _E (abnormality) at time slot _t5 in the same manner as described above.
The logic output circuit 64 delivers to the output terminal 6 an alternating signal of said frequency _P , _N or _E with the aid of a timing signal 50 which occurs only in time slot _t5 . Now, if the sum of the frequencies of the input alternating signals, that is, the frequency of the alternating signal 14, exceeds the reference frequency ₁₀ or is erroneously determined to have exceeded the reference frequency ₇ ,
If it is incorrectly determined that the value is below or below the
The determination signal 36 is “0” between time slots t ₁ to _{t 4}
Alternatively, it remains at "1" and does not generate a falling edge trigger signal. Therefore, there is no data latched by the latch circuit 62 from the data string 58, and the alternating signal generating circuit 30 does not generate an alternating signal at time slot _t5 . As described above, an alternating signal with frequency _P (positive logic), _N (negative logic), or _N (abnormality) is received at input terminals 4 and 5, and an alternating signal with corresponding frequency is sent to output terminal 6. by frequency logic
The function of the OR element is achieved. As is clear from this operation, input terminals 4 and 5
If an abnormal frequency other than the normal frequencies _P and _N is input to at least one of them, or if an abnormality occurs in the calculation and judgment of the frequency value inside this logic element and the generation operation of the alternating signal, the normal frequency Output frequency
The probability of outputting _P and _N is extremely low, making it possible to provide a highly fail-safe logic element. Furthermore, by narrowing the frequency band that is determined to be a normal frequency, it is possible to increase the probability of detecting an abnormality, and it is also easy to further improve fail-safe performance. The above was about the OR elements in Table 2, but
All of the other logic elements in Table 2 can be configured by simply rewriting the data string 56 (reference frequency data) or the data string 58 (frequency data corresponding to the output truth value) in the memory shown in FIG. can be easily understood. When used as an AND element, based on Table 2, only when the frequency band determination result is _2P ,
The positive logic frequency _P may be output, and the negative logic frequency _N may be output for other normal input combinations. Therefore, of the reference frequency data in the data string 56 to be stored in the memory 54, ₁₀ = 620
Leave Hz and ₇ = 90Hz as is, ₉ = 580Hz,
Just rewrite it to ₈ = 360Hz. Also, in the data string 58, time slot t ₂
It is clear from Table 2 that by replacing the data _P and _N of and _t4 , the above OR and AND elements can be converted into NOR and NAND elements, respectively. In the conventional binary logic system, the EOR logic element is
Although it is necessary to configure using several binary logic elements of AND, OR, and NOT, according to this embodiment, EOR logic can be realized with a single logic element. In other words, the function of the EOR logic element is to output _P only when the frequency of signal 14 is _P + _N , and output _N when the frequency is 2 _P or 2 _N.
As shown in the figure, frequency comparison time slots t ₅ and t ₆ are further added than in the example of _FIG .
620Hz, ₉ to 580Hz, ₈ to 370Hz, ₇ to 340Hz, ₆ to
110Hz, ₅ is 90Hz, and _P and _N are 300Hz and 50Hz, respectively, as in the previous embodiment. FIG. 11A shows the operation when the inputs are both _P and match, B is the case when the inputs are different, and FIG. 11C is the operation when the inputs are both _N and the same. Also, the 2-out-of-3 majority circuit is the 8th
This can be realized by making slight changes to FIG. 9 and FIG. First, the arithmetic unit 7 in FIG. 8 is replaced with the one in FIG. That is, by adding the input terminal 70, the sampling circuit 72, its clock signal 74, and the EOR 76, an alternating signal 14 having a frequency equal to the sum of the three inputs is obtained. Next, the reference frequency data ₁₀ to ₇ of the data string 56 in the memory in FIG. 9 are as follows: ₁₀ = 1000Hz, ₉ = 620Hz,
Rewrite the data to represent ₈ = 420Hz and ₇ = 120Hz. In this way, when the frequency of the sum of the three inputs is 3 _P = 900 Hz and 2 _P + _N = 650 Hz, it is possible to output an alternating signal of frequency _P that represents the output truth value "1", and _P + 2 _N = When 400 Hz or 3 _N = 150 Hz, an alternating signal of frequency _N representing the output truth value "0" can be output. When it is determined that the frequency is any other, an alternating signal of frequency _E indicating "abnormality" can be output (no alternating if _E = 0 Hz). The result is a 3-input majority circuit, ie, a 2-out-of-3 logic function. Now, in the embodiments shown in FIGS. 8 to 10,
Time slot _T6 provides a failure detection function for even more complete fail-safety. That is, the error detection circuit 66 checks all input data to the alternating signal generation circuit 30. For example, a rationality check is performed for each time slot by means such as a known parity check or a cyclic code check, and the output frequency of the alternating signal generating circuit 30 in time slot _t6 is switched according to the result. If there is no error at all within one address period t, an alternating signal of the maximum possible frequency is generated, while if there is data containing even one error, the signal is switched to 0 Hz. If this maximum frequency _nax is set higher than the normal maximum frequency _2P of the signal 14, the determination signal 36 will be "1" if there is no error in the data, and "0" if there is an error. On the other hand, data is stored in the memory 54 in two ways as shown in FIG.
Since the memory 54 feeds back the judgment signal 36 as one of its address signals, the judgment signal 36 is "1" and "0".
Different data can be read. Different data is stored only in time slot _t6 , and the content of the data string 58 is data ED containing an error when the determination signal 36 is "1"; 0”, data RD is set to have no error. By doing so, if there is no failure, the determination signal 36 in time slot _t6 becomes an alternating signal with a frequency higher than a predetermined frequency. That is, at time slot _t6 , the judgment signal 36 indicating normality is
When “1” is output, the next time slot t ₆
Then, data ED containing an error is read out, and the determination signal 36 becomes "0" due to the functions of the error detection circuit 66 and frequency comparison circuit 34. Therefore, in the next time slot _t6 , normal data RD is read out, and the determination signal 36 similarly returns to "1". Since this process is repeated thereafter, the determination signal 36 alternates. However, for the sake of simplicity, this explanation assumes that the frequency comparator circuit 34 can determine the magnitude for each calculation slot, but in reality, it is an integral type frequency comparison, so it is assumed that the frequency comparison circuit 34 can perform a magnitude determination for each calculation slot. After t ₆ , the magnitude of the frequency is determined. Therefore, the alternating frequency is a frequency higher than the predetermined value, which is lower than the above-described calculation frequency of 10 KHz. The alternating signal 36 in this time slot _t6
is sent from the fault detection output circuit 68 to the output terminal 17 with the aid of a timing signal 52 which occurs only in this slot _t6 . The alternating signal sent to the output terminal 17 continues as long as the circuit in the logic element is operating normally, and the alternating signal generation circuit 3 used for normal logic processing continues.
Even if a failure occurs in any of the 0, the frequency comparison circuit 34, etc., and the error detection circuit 66, the alternation is stopped. Therefore, by monitoring this alternating signal from the outside, it is possible to know the occurrence of any abnormality. Next, an embodiment will be described in which the degree of freedom in fail-safe logic design according to the present invention is increased. The output frequency of a logic element is three values: _P , _N , and _E , but in general, according to the classification of fail-safe three-value logic, if there is even one abnormal input to the input terminal as shown in Table 2, the output frequency will be a value that indicates an abnormal output. This type of fail-safe control is called a C-type fail-safe. C-type fail-safe is the most rigorous fail-safe method in that if a failure occurs at even one point in the system, the effect will be immediately reflected in the system's final output, but it is suitable for systems that must continue to operate for a certain amount of time even if a failure occurs. There are some things that are not true. Compared to the C type, a type that has durability in the event of a failure (fault tolerance) is called a φ type fail-safe. φ-type fail-safe is a system that continues normal output when one of the inputs is abnormal and it is safe to determine the output based only on the other input value.OR,
For each logical function of NOR, AND, and NAND,
This φ-type fail-safe function can be provided.

〔Effect of the invention〕

According to the present invention, it is possible to provide a fail-safe logic system that achieves a high degree of fail-safety even when using a semiconductor element or the like that itself fails out, is easy to reduce in size and weight, and has a high degree of freedom in use.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a logic signal according to the present invention in comparison with a conventional logic signal, FIGS. 2 to 4 are diagrams showing different examples of frequency band determination according to the present invention, and FIG. FIG. 6 is a block diagram of a logic system according to an embodiment of the present invention, FIG. 6 is a block diagram of another embodiment, FIG. 7 is a block diagram of yet another embodiment, and FIG.
The figure is a block diagram embodying the embodiment of FIG. 7, FIG. 9 is a diagram showing the data stored in the memory of FIG. 8, and FIG. 10 shows the operating situation when the device shown in FIG. 8 is used as an OR element. Time chart, Figure 11 is 8th
Fig. 12 is a block diagram showing an example of replacing the arithmetic unit to use Fig. 8 as a majority circuit, Fig. 13 shows the function of Fig. 8. FIG. 3 is a diagram of an improved embodiment; 2, 12, 13... Logic element, 4, 5, 70... Input terminal, 6... Output terminal, 7... Arithmetic unit, 8... Band determining unit, 10... Alternating signal generating unit, 77... Setting change means.

Claims (1)

[Scope of Claims] 1. A logic device that performs logical operations by associating different truth values with alternating signals having different frequencies, which inputs at least two of the above alternating signals and performs one type of operation between these input frequency values. a single calculation means for performing a calculation, a band determination means for determining in which frequency band the calculation result falls within a frequency band having a predetermined width including a plurality of planned different frequencies; an alternating signal generating means that outputs an alternating signal having a different frequency corresponding to each of the output truth values, and a correspondence relationship between the calculation result that is the output of the calculating means and the frequency of the alternating signal output by the alternating signal generating means. and a setting change means for changing the settings. 2. The logical device according to claim 1, wherein the setting changing means is a means for changing the setting of the determination frequency band of the band determining means. 3. The logic device according to claim 1, wherein the setting changing means is means for changing the setting of the correspondence between the determination result of the band determining means and the frequency of the alternating signal output by the alternating signal generating means. 4. The logic device according to claim 1, wherein the frequency band corresponding to the input truth value and the frequency band corresponding to the output truth value are the same. 5. The logic device according to claim 1, wherein the single calculation means for performing the above-mentioned one type of calculation is addition means. 6. The logic device according to claim 5, wherein the adding means is means for directly adding the input alternating signals by shifting the phase of the input alternating signals. 7. The logic device according to claim 1, wherein the frequency corresponding to the input truth value is selected in a frequency band in which the frequency of the calculation result does not overlap with the frequency corresponding to any of the input truth values. 8. In claim 1, the band determination means compares each of the reference alternating signals having upper and lower frequency limits for each scheduled reference frequency band with the above calculation results on a time-sharing basis, and calculates the results of this comparison. A logic device that is a means for determining the band of an alternating signal as a result of calculation based on the change timing of . 9. The logic device according to claim 8, which shares the alternating signal generating means with the means for generating a reference alternating signal having upper and lower limit frequencies for each of the scheduled reference frequency bands. 10. The logic device according to claim 1, further comprising a memory for storing the frequency of the alternating signal outputted by the oscillation means, and wherein the setting changing means comprises means for exchanging the memory. 11. In claim 1, the invention further comprises a memory for storing the frequency of the alternating signal output by the oscillation means, and the setting changing means reads out which one of the plurality of frequency sets stored in the memory. logical device consisting of means for switching between 12. The logic device according to claim 1, wherein when at least one of the plurality of input alternating signals has a frequency representing an abnormal state, the oscillation means outputs a frequency representing the abnormal state. 13 In claim 1, when at least one of the plurality of input alternating signals has a frequency representing an abnormal state, the output truth value is determined based on the other input alternating signals, and the output truth value corresponds to the truth value. A logic device that outputs an alternating signal with a frequency.