JPH05219045A - Coded signal decoding device - Google Patents

Abstract

(57) [Abstract] [Purpose] A coded signal decoding device that decodes a coded signal obtained by coding speech or the like in frame units. When a frame becomes discontinuous due to editing, etc. (EN) A coded signal decoding device capable of re-acquiring synchronization and preventing erroneous decoding. [Structure] A sync pattern detector 2 detects a sync pattern of an encoded signal. The frame information extraction unit 3 extracts frame length information from the encoded signal S1. The determination timing generation unit 4 predicts the next synchronization position based on the synchronization pattern based on the frame length information. The synchronization state determination unit 5 determines whether the synchronization is unlocked or locked by using the predicted synchronization signal and outputs the synchronization state information. The decryption unit 6 utilizes the synchronization status information to perform decryption. With this configuration, by controlling the operations of the determination timing generation unit 4 and the decoding unit 6 according to the synchronization status information, the synchronization re-pull-in of the discontinuous coded signal can be speeded up, and noise does not occur at the discontinuous point. You can

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coded signal decoding device for decoding a coded signal obtained by coding a signal on a frame-by-frame basis, and more particularly to detecting synchronization of the coded signal.

[0002]

2. Description of the Related Art In recent years, with the progress and development of high-efficiency coding technology, the technology for high-efficiency coding of digital signals such as voice and images is approaching its application field.

Conventionally, in the high-efficiency encoding technique, a technique has been widely used in which a frame is composed of a plurality of digital signals and the frame is encoded to achieve high-efficiency encoding. When coded data is transmitted by digital recording or a digital line using such a technique, it is common practice to add coded data with system information such as a synchronization pattern and frame period to form a coded frame. It is being appreciated. Since the synchronization information can be transmitted or recorded together with the data by adding the synchronization pattern, a separate line or recording area for synchronization becomes unnecessary. Further, by recording the frame period information, it becomes possible to deal with various frame periods.

An example of a conventional coded signal decoding device using such a technique will be described below.

FIG. 7 is a block diagram of a conventional coded signal decoding device. In FIG. 7, reference numeral 71 is a coded signal reproducing unit, 72 is a synchronization pattern detecting unit, 73 is a frame information extracting unit, 74 is a synchronization timing generating unit, and 75 is a decoding unit.

The operation of the coded signal decoding device configured as described above will be described below.

The encoded signal reproducing section 71 reproduces the signal transmitted through the communication path or the signal from the recording medium. In this case, for example, a magnetic tape is used as the recording medium, and the encoded signal is recorded in advance and reproduced.
The encoded signal reproducing unit 71 performs error correction on the signal from the recording medium and outputs the encoded signal S71 and the uncorrectable signal S72. The synchronization pattern detector 72 extracts a synchronization pattern from the encoded signal S71 and outputs a synchronization pattern detection signal S73. If the uncorrectable signal S72 indicates uncorrectable, it is regarded as not a synchronization pattern. The frame information extraction unit 73 uses the encoded signal S71 to extract the frame length information S at a predetermined position with respect to the synchronization pattern.
74 is extracted and output. The synchronization timing generation unit 74 outputs the predicted synchronization signal S75 from the synchronization pattern detection signal S73 and the frame length information S74 at the time when the next synchronization pattern should come according to the frame length information S74 with reference to the synchronization pattern detection time. This predicted sync signal S75 is obtained when the sync pattern detection signal S73 is missing by one frame.
The next prediction is performed using the immediately preceding frame length information S74 and the prediction synchronization signal S75. When the sync pattern detection signal S73 is missing for two consecutive frames, the predicted sync signal S75 is stopped. A so-called flywheel-like operation is performed to protect in the case where the sync pattern is missing due to uncorrectability or the like. The decoding unit 75 decodes the immediately preceding one frame with the coded signal S71 as the timing indicated by the prediction synchronization signal S75, and outputs the reproduction signal S76.

FIG. 8 shows an example of a coded frame structure of a coded signal. A sync pattern S is provided at the beginning of the coded frame, then frame length information T showing the frame length, and then a coded recording signal. It has a configuration called U. In FIG. 8, the synchronization pattern S is represented by eight consecutive “1” s. The frame length information T is encoded and recorded at a fixed position with respect to the synchronization pattern S, in this example, the position immediately after.

[0009]

However, in the above-described conventional coded signal decoding apparatus, when a coded signal that is discontinuous due to editing, signal switching, or the like is decoded, immediately after the period of the synchronization pattern is disturbed. However, there is a problem in that the discontinuous coded signal of is regarded as correct data and is decoded, and noise is output.

FIG. 9 shows the operation timing of the conventional coded signal decoding apparatus for showing this problem.

It is assumed that a signal as shown in the figure is output as the encoded signal S71. The hatched portion in the figure is a synchronization pattern, and one frame extends from the hatched portion to immediately before the next hatched portion. Frames a to g are frame names added for explanation. The reason why the frame period of the frame d is short is that the frames are switched because the editing is performed at the points indicated by ▼ in the figure. Further, the uncorrectable signal S72 becomes "1" when the correction is impossible. In this example, the portion of the synchronization pattern of frame c cannot be corrected and a signal as shown in the figure is output. The operation of the conventional coded signal decoding device when such coded signal S71 and uncorrectable signal S72 are output from the coded signal reproduction unit 71 will be described.

The synchronization pattern detector 72 receives the encoded signal S7.
When the synchronization pattern of 1 is detected, the synchronization pattern detection signal S73 which becomes "1" (high level) is output. When the uncorrectable signal S72 is "1", nothing is output. The frame information extraction unit 73 extracts the frame length information S74 immediately after the synchronization pattern detection signal S73 becomes "1" from the encoded signal S71. First, when the synchronization pattern of the frame a is detected, the synchronization timing generator 74 outputs the predicted synchronization signal S75 = '1' after the frame length Ta output by the frame information extractor 73. After that, the prediction synchronization signal S is generated at the cycle indicated by the frame length information S74 of each frame.
Outputs 75. If the frame length information S74 of the frame cannot be extracted due to uncorrectability or the like, the immediately preceding frame length information S74 is used. For example, Tb is used when Tc cannot be extracted in frame c. As a result, loss of synchronization due to uncorrectable frame c can be protected. Predictive sync signal S75
When = 1, the sync pattern detection signal S73 = '1'
Is checked, and if it becomes “0” twice, the predicted synchronization signal S
Stop 75. After the synchronization is lost, the next synchronization pattern detection signal S73 is waited for, and the same processing as in the case of frame a is performed. The decoding unit 75 performs decoding on a frame-by-frame basis with the prediction synchronization signal S75 as a reference. As indicated by the dotted arrow in the figure, the reproduction signal S76 is output with a delay of one frame from the encoded signal S71 due to the processing delay, so that the frames b, c, and d of the encoded signal S71 are output at the time of the frame. The reproduction signals S76 of a, b and c are reproduced. The same applies to the frame d and the frame g. The frame d is decoded because the sync pattern is correct, but the data cannot be correctly decoded because there is an edit point in the middle of the frame and the data is discontinuous.

As described above, in the conventional coded signal decoding apparatus, when a coded signal that is discontinuous due to editing or the like is decoded, the synchronization pattern is correct and thus the synchronization protection works, resulting in erroneous decoding. Had a point. Further, since the next synchronization pull-in process is started after the synchronization protection operation is completed, there is a problem that the synchronization re-pull-in is delayed.

The present invention solves the above-mentioned problems of the prior art. The synchronization is pulled in early, and once the synchronization is pulled in, it is unlikely to be disengaged due to an error such as an uncorrectable error. It is an object of the present invention to provide an encoded signal decoding device that does not perform decoding.

[0015]

To achieve this object, a coded signal decoding device of the present invention performs error correction on a signal from a transmission line or a recording medium, and outputs a coded signal and an uncorrectable signal. A coded signal reproducing means for extracting a sync pattern from the coded signal and the uncorrectable signal, and inputting the sync pattern detecting means for outputting the sync pattern detection signal, the coded signal and the sync pattern detection signal, From the frame information extracting means for extracting and outputting the frame length information recorded at a predetermined position with respect to the synchronization pattern in the encoded signal, the synchronization pattern detection signal, the frame length information and the synchronization state information Judgment timing generating means for outputting a predicted sync signal at the time when the next sync pattern should come based on the frame length information based on the sync pattern detection time according to the state information Inputs an uncorrectable signal, a sync pattern detection signal, and a predicted sync signal, determines the next state from the current sync state information by these signals, and outputs sync state information indicating a sync unlock state and a sync lock state. The sync state determining means for inputting the coded signal, the predicted sync signal and the sync state signal are input, and the coded signal is muted or coded according to the state indicated by the sync state information with reference to the timing indicated by the predictive sync signal. And a decoding means for outputting a reproduction signal obtained by decoding one frame.

Further, the coded signal decoding device of the present invention is
Coded signal reproduction means for performing error correction on a signal from a transmission line or a recording medium and outputting a coded signal and an uncorrectable signal,
A synchronization pattern detecting means for extracting a synchronization pattern from the encoded signal and the uncorrectable signal and outputting the synchronization pattern detection signal, and the encoded signal and the synchronization pattern detection signal are input to obtain a synchronization pattern in the encoded signal. On the other hand, the first synchronization state information is obtained from the frame information extraction means for extracting and outputting the frame length information recorded at a predetermined position, the synchronization pattern detection signal, the frame length information and the first synchronization state information. In accordance with the sync pattern detection time, the first determination timing generating means for outputting the first predicted sync signal at the time when the next sync pattern should come based on the frame length information, the uncorrectable signal, the sync pattern detection signal, and the 1 when the predicted synchronization signal and the first state transition control signal are input and the state transition is permitted by the first state transition control signal. First synchronization state determination means for determining the next state from the first synchronization state information and outputting first synchronization state information indicating a synchronization unlock state and a synchronization lock state, a synchronization pattern detection signal, and frame length information And the second
Second synchronization timing information that outputs a second predicted synchronization signal at the time when the next synchronization pattern should come based on the frame length information based on the synchronization pattern detection time according to the second synchronization status information. Means, the uncorrectable signal, the synchronization pattern detection signal, the second predicted synchronization signal, and the second state transition control signal are input, and when the state transition is permitted by the second state transition control signal, Second synchronization state determination means for determining the next state from the second synchronization state information of the second synchronization state information and outputting the second synchronization state information indicating the synchronization unlock state and the synchronization lock state, and the first predicted synchronization signal. The first synchronization status information, the second predicted synchronization signal, and the second synchronization status information are input, and the first synchronization status determination means and the second synchronization status information are input from the first synchronization status information and the second synchronization status information.
Of the synchronization state determining means, the first state transition control signal and the second state transition control signal for permitting the state transition of only one of them are output, and the prediction synchronization of the transition permitted one. State transition control means for outputting a signal and synchronization state information as a third predicted synchronization signal and third synchronization state information, respectively, and an encoded signal, a third predicted synchronization signal, and a third synchronization state signal are input. Decoding means for outputting a reproduction signal obtained by decoding one frame of the coded signal according to the state indicated by the third synchronization state information with reference to the timing indicated by the third predicted synchronization signal for the encoded signal. Have

[0017]

The coded signal decoding device of the present invention has the above-mentioned configuration to manage the synchronization state by the synchronization state determination means,
Since the decoding process is performed using the predicted synchronization signal and the synchronization state information, it is possible to prevent decoding by mistake when the cycle of the encoded frame is disturbed by editing or the like.

Further, the coded signal decoding device of the present invention has two judgment timing generating means and 2
By managing the one synchronization state determination means and the state transition control means, the synchronization pattern check in the encoded signal can be performed by 2
Since they can be processed simultaneously, when the cycle of the coded frame is disturbed at an edit point or the like, it is possible to quickly pull in to correct synchronization without missing the synchronization pattern.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a coded signal decoding apparatus according to the first embodiment of the present invention.

In FIG. 1, reference numeral 1 is a coded signal reproducing section, 2
Is a synchronization pattern detection unit, 3 is a frame information extraction unit, 4 is a determination timing generation unit, 5 is a synchronization state determination unit, and 6 is a decoding unit.

The operation of the coded signal decoding apparatus of this embodiment having the above configuration will be described below.

The coded signal reproducing unit 1 performs error correction on the signal from the recording medium as in the conventional example, and outputs the coded signal S1 and the uncorrectable signal S2. The synchronization pattern detection unit 2 extracts a synchronization pattern from the encoded signal S1 and outputs a synchronization pattern detection signal S3. If the uncorrectable signal S2 indicates uncorrectable, it is regarded as not a synchronization pattern. The frame information extraction unit 3 extracts the frame length information S4 at a predetermined position with respect to the synchronization pattern from the encoded signal S1 and outputs it. Judgment timing generator 4
Is the sync pattern detection signal S3, the frame length information S4, and the sync status information S6, and the sync status information S6 is C2, C.
At 3 and C4, the predicted synchronization signal S5 is predicted by predicting the time when the next synchronization pattern will come based on the frame length information S4 with reference to the falling edge of the immediately preceding synchronization signal S5.
Is output. When the synchronization status information S6 is C1, the predicted synchronization signal S5 is stopped. The synchronization state determination unit 5 determines the next state from the uncorrectable signal S2, the synchronization pattern detection signal S3, the predicted synchronization signal S5, and the synchronization state information S6, and outputs the synchronization state information S6. The decoding unit 6 decodes the immediately preceding one frame in accordance with the state indicated by the synchronization state information S6, with the encoded signal S1 as the timing indicated by the prediction synchronization signal S5, and outputs the reproduction signal S7.

FIG. 2 shows the synchronization status information S of the synchronization status determination unit 5.
It is a figure which shows an example of the state transition of 6. Synchronization status information S6
Have C1, C2, C3, and C4, the state C1 is a state in which no synchronization pattern is detected, the state C2 is a state in which the synchronization pattern is first detected, and the state C3 is a state in which synchronization is locked.
State C4 is a state in which the synchronization pattern is not detected once after locking. That is, the states C1 and C2 indicate unlocked states in which synchronization is lost, and the states C3 and C4 indicate states in which synchronization is locked. The initial state is state C1. The transition conditions between these states are shown in FIG. 2 (a), and the state transition diagram thereof is shown in FIG. 2 (b). When the uncorrectable signal S2 is "0", it indicates that the encoded signal S1 is correct, and when it is "1", it indicates that the coded signal S1 is uncorrectable. When the synchronization pattern detection signal S3 is "0", the encoded signal S1
Indicates that it is not a synchronization pattern, and when it is '1', it indicates that it is a synchronization pattern. Regarding the timing of the state determination, the state transition is always determined in the state C1, and the state C
In 2, C3 and C4, the transition state is determined at the falling edge of the prediction synchronization signal S5. Now, assuming that the state is C1, the state transitions to the state C2 only when the synchronization pattern detection signal S3 is "1". In the state C2, the state transitions to the state C3 only when the synchronization pattern detection signal S3 is "1", and otherwise returns to the state C1. In the state C3,
When the synchronization pattern detection signal S3 is "0", it transits to the state C1 and when it is "1", it stays in the state C3 and the uncorrectable signal S
When 2 is '1', the state changes to state C4. In the state C4, if the synchronization pattern detection signal S3 is "1", the state C
Return to 3, and otherwise transition to state C1.

FIG. 3 is a timing chart for explaining the operation of the first embodiment. It is assumed that the same signal as the conventional example is output as the encoded signal S1 as shown in the figure. a
.. g are frame names added for explanation. The reason why the frame period of the frame d is short is that the frames are switched because the editing is performed at the points indicated by ▼ in the figure. Further, the uncorrectable signal S2 is uncorrectable in the synchronization pattern portion of the frame c in this example. The operation when the encoded signal S1 and the uncorrectable signal S2 are output from the encoded signal reproducing unit 1 will be described.

The sync pattern detection section 2 outputs a sync pattern detection signal S3 which becomes "1" when the sync pattern of the coded signal S1 is detected. Uncorrectable signal S2 is "1"
In case of, nothing is output. The frame information extraction unit 3 extracts the frame length information S4 immediately after the synchronization pattern detection signal S3 becomes "1" from the encoded signal S1. First, when the synchronization pattern of the frame a is detected, the determination timing generator 4 outputs the predicted synchronization signal S5 = '1' after the frame length Ta output from the frame information extractor 3 with the synchronization pattern detection signal S3 as a reference. After that, prediction is performed at the cycle indicated by the frame length information S4 of each frame, and the prediction synchronization signal S5 is output. This continues until the synchronization status information S6 becomes the status C1. That is, like the prediction of the frame e based on the frame d in the example of the figure, the sync pattern is not detected even though the encoded signal S1 is not uncorrectable, or the sync pattern is corrected continuously for two frames. If it becomes impossible, stop. After that, the next synchronization pattern detection signal S3 is waited until it becomes '1', and the same processing as the frame a is performed from the frame f. The synchronization state determination unit 5 uses the uncorrectable signal S2 and the synchronization pattern detection signal S
As described in FIG. 2, the transition state is determined from 3 and the immediately preceding synchronization state information S6, and the synchronization state information S6 is output. The decoding unit 6 mutes the reproduction signal S7 when the synchronization state signal S6 is in the states C1 and C2, that is, in the unlock state, and when the synchronization state signal S6 is in the unlock state, using the predicted synchronization signal S5 as the frame reference, and in the states C3 and C4, In the locked state, the encoded signal S1 is decoded and the reproduced signal S7 is output. Since the reproduction signal S7 is delayed by one frame due to the processing delay as in the conventional example, the frames a, b and c are output at the times of the frames b, c and d of the encoded signal S1 and the frame f is output at the time of the frame g. ..

As described above, according to the first embodiment, the synchronization state determination unit 5 manages the synchronization state information S6 and the synchronization state information S6 controls the mute of the decoding process. When the cycle of the encoded frame is disturbed, decoding is not performed by mistake, noise is not generated in the reproduction signal S7, and when the synchronization pattern does not come to the point predicted by the determination timing generation unit 4, the state is set to C1. As a result, the next prediction is stopped, so that the synchronization can be re-pulled in earlier, which is possible from one frame before in comparison with the conventional example.

FIG. 4 is a block diagram showing the configuration of the coded signal decoding apparatus according to the second embodiment of the present invention.

In FIG. 4, 1 is a coded signal reproducing section, 2
Is a synchronization pattern detection unit, 3 is a frame information extraction unit, 41
Is a first determination timing generation unit, 42 is a first synchronization state determination unit, 43 is a second determination timing generation unit, 44 is a second synchronization state determination unit, 45 is a state transition control unit, and 6 is decoding. It is a department.

The coded signal reproducing section 1, the sync pattern detecting section 2, the frame information extracting section 3, and the decoding section 6 are the same as those in the first embodiment. The first determination timing generation unit 41 and the second determination timing generation unit 43 are the same as the determination timing generation unit 4 of the first embodiment. The first synchronization state determination unit 42 and the second synchronization state determination unit 44 are the same as the synchronization state determination unit 5 of the first embodiment except that control is performed to permit state transition.

The operation of the coded signal decoding apparatus of the second embodiment having the above configuration will be described below.

The coded signal reproducing section 1 outputs the coded signal S1 and the uncorrectable signal S2 as in the first embodiment. The synchronization pattern detection unit 2 extracts a synchronization pattern from the encoded signal S1 and outputs a synchronization pattern detection signal S3. The frame information extraction unit 3 extracts the frame length information S4 at a predetermined position with respect to the synchronization pattern from the encoded signal S1 and outputs it. The first determination timing generator 41 determines the first synchronization status information S42 from the synchronization pattern detection signal S3, the frame length information S4, and the first synchronization status information S42.
Is in the states C2, C3, C4, the first predicted sync signal S4 is obtained by predicting the time when the next sync pattern will come based on the sync pattern detection time based on the frame length information S4.
1 is output. That is, at this time, the same operation as that of the determination timing generator 4 of the first embodiment is performed. In the state C1, the first prediction synchronization signal S41 is stopped. The first synchronization state determination unit 42 uses the uncorrectable signal S2, the synchronization pattern detection signal S3, the predicted synchronization signal S41, and the first synchronization state information S4.
2 and the first state transition control signal S45 to determine the next state, and output the first synchronization state information S42. In addition, the second determination timing generation unit 43 uses the synchronization pattern detection signal S3, the frame length information S4, and the second synchronization state information S44.
Therefore, the second synchronization status information S44 indicates that the statuses C2, C3,
At the time of C4, the second predicted synchronization signal S43 is output at the time when the next synchronization pattern should come according to the frame length information S4 with reference to the synchronization pattern detection time. That is, at this time, the same operation as that of the determination timing generator 4 of the first embodiment is performed. In the state C1, the second predicted synchronization signal S43
Will stop. The second synchronization state determination unit 44 determines the next state from the uncorrectable signal S2, the synchronization pattern detection signal S3, the second predicted synchronization signal S43, the second synchronization state information S44, and the second state transition control signal S46. It is determined and the second synchronization status information S44 is output. The state transition control unit 45 determines the first state transition control signal S45 and the first state transition control signal S45 from the first predicted synchronization signal S41, the first synchronization state information S42, the second predicted synchronization signal S43, and the second synchronization state information S44. The second state transition control signal S46 permits only one of the state transitions of the first synchronization state determination unit 42 and the second synchronization state determination unit 44, respectively. That is, in the case of one synchronization pattern detection signal S3 or uncorrectable, the predicted synchronization signal acts only on one of the synchronization state determinations having a higher priority. Also, the first synchronization status information S42
And the synchronization state information of the one of the second synchronization state information S44 that is permitted to be transitioned is output as the third synchronization state information S48. The logical sum signal of the first prediction synchronization signal S41 and the second prediction synchronization signal S43 is output as the third prediction synchronization signal S47. The decoding unit 6 uses the encoded signal S1 as a reference with respect to the timing indicated by the third prediction synchronization signal S47.
The immediately preceding 1 according to the state indicated by the third synchronization state information S48.
The frame is decoded and the reproduction signal S7 is output.

The state determination conditions of the first state determination section 42 and the second state determination section 44 are the first state transition control signal S4.
The description is omitted because it is the same as that described in FIG. 2 in the first embodiment except that the state transition may be stopped by 5 and the second state transition control signal S46.

FIG. 5 is a diagram for explaining the operation of the state transition control unit 45. In the figure, the state transition control unit 45 permits the state transition of either the first synchronization state determination unit 42 or the second synchronization state determination unit 44 from the first synchronization state information S42 and the second synchronization state information S44. This is indicated by "1" or "2". The crosses in the figure are combinations that do not occur. This permission control is performed by the first synchronization state determination unit 42 and the second synchronization state determination unit 42.
This is performed only when both of the synchronous state determination units 44 of (1) and (2) are in a condition of simultaneously making a state transition, and when one of them is in a condition of being able to make a state transition, that state makes a state transition and no control operation is performed. For example, if the first synchronization status information S42 is status C3
If the second synchronization state information S44 is the state C1, then the first
If the predicted synchronization signal S41 of 1 and the synchronization pattern detection signal S3 temporally coincide with each other, the determination timings of both state transitions become the same, and therefore the first synchronization state determination unit 42 from the figure.
Only the state transition is permitted, and the second synchronization state information is C1.
Will remain.

FIG. 6 is a timing chart for explaining the operation of the second embodiment. As the coded signal S1 and the uncorrectable signal S2, the same signals as in the first embodiment are output as shown in the figure. The operation when the encoded signal S1 and the uncorrectable signal S2 are output from the encoded signal reproducing unit 1 will be described.

Since the operations of the synchronization pattern detecting section 2 and the frame information extracting section 3 are exactly the same as those in the first embodiment, their explanations are omitted. The state transition control unit 45 initially sets both the first synchronization state information S42 and the second synchronization state information S44 to the state C.
Since it is 1, only the first state transition control signal S45 is set to "1", and only the first synchronization state determination unit 42 is allowed to undergo state transition. First, when the first synchronization state information becomes the state C2 due to the synchronization pattern of the frame a, the determination timing of the first synchronization state determination unit 42 is only the trailing edge of the first predicted synchronization signal S41. The state transition control signal S46 sets the second state transition control signal S46 to "0" according to the priority order of FIG. 5 only during the period when the first predicted synchronization signal is "1", and the second synchronization state determination unit at this time Stop the state transition of 44. Therefore, the operations of the first determination timing generation unit 41 and the first synchronization state determination unit 42 up to the switching point of the encoded signal S1 shown by ▼ in the drawing are the same as the determination timing generation unit 4 of the first embodiment. And the operation of the synchronization state determination unit 5 is the same. Next, the synchronization pattern detection signal S3 of the frame e is input immediately after the switching point of the encoded signal S1 shown by ▼ in the figure, but the first synchronization state determination unit 42 is in the state C3. Timing is first
Only the trailing edge of the predicted synchronization signal S41 of (1), the state transition does not occur, and the second synchronization state determination unit 44 enters the state C2. Immediately after this, the first synchronization state determination unit 42 determines that the uncorrectable signal S2 is "0", but the synchronization pattern detection signal S3.
Is 0, the state becomes C1. When the synchronization pattern detection signal S3 of the next frame f becomes '1', the first synchronization state information S42 is the state C1 but the second synchronization state information is the state C2, so the second synchronization state determination is made. The priority of the unit 44 is high, and the second synchronization status information S44 becomes the status C3. After that, when the second state transition control signal S46 is "1" of the second predicted synchronization signal S43, it becomes "1",
The synchronization state determination unit 44 continues to be locked. The third synchronization status information S48 is the first synchronization status information S4 according to FIG.
Since the higher priority state of the second and second synchronization state information S44 is output, the state is as shown in FIG. The decoding unit 6 mutes the reproduction signal S7 when the synchronization state signal S6 is in the states C1 and C2, and the encoded signal S in the states C3 and C4 with the third predicted synchronization signal S47 as the frame reference.
1 is decoded and a reproduction signal S7 is output. The reproduction signal S7 is delayed by one frame with respect to the encoded signal S1 by the processing delay as in the first embodiment.

As described above, according to the second embodiment, the state transition control unit 45 selects the transition of the synchronization state between the first synchronization state determination unit 42 and the second synchronization state determination unit 44, When one is in the synchronization lock, the other operates so as to check the synchronization pattern that is not in the synchronization lock. Therefore, when the cycle of the encoded frame is disturbed by editing or the like, the synchronization can be re-pulled in quickly. .. In this embodiment, re-drawing can be performed from two frames before the conventional example.

[0038]

As described above, the coded signal decoding apparatus of the present invention can quickly and surely detect the correct frame synchronization in the coded signal, switch the transmission signal, and edit on the recording medium. Even if the encoded signal becomes discontinuous due to overwriting due to, etc., noise will not occur due to incorrect decoding, and synchronization pull-in at the start of decoding and follow-up at frame switching can be ensured quickly. it can.

Particularly, the effect is great when the discontinuity of the coded signal frequently occurs, such as when performing special reproduction such as fast-forward reproduction of the signal recorded on the disk or tape medium.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a coded signal decoding device according to a first embodiment of the present invention.

FIG. 2A is an explanatory diagram showing an example of a state transition condition of the synchronization state determination unit 5 in the first embodiment. FIG. 2B is a state transition diagram of the synchronization state determination unit 5 in the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the coded signal decoding apparatus in the first embodiment.

FIG. 4 is a block diagram showing a configuration of a coded signal decoding device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram illustrating a state transition control operation of a state transition control unit 45 in the second embodiment.

FIG. 6 is a timing chart for explaining the operation of the coded signal decoding device according to the second embodiment.

FIG. 7 is a block diagram showing a configuration of a conventional compression coded signal recording / reproducing device.

FIG. 8 is a schematic diagram showing an example of a frame configuration of an encoded signal.

FIG. 9 is a timing chart for explaining problems in the operation of the conventional compression coded signal recording / reproducing apparatus.

[Explanation of symbols]

 1 coded signal reproducing unit 2 synchronization pattern detecting unit 3 frame information extracting unit 4 determination timing generating unit 5 synchronization state determining unit 6 decoding unit

Claims (2)

[Claims] 1. Use for decoding a coded signal in which a signal such as voice is coded in frame units and a frame synchronization pattern for frame synchronization and frame information for transmitting information such as frame length are added thereto. A coded signal decoding device for performing error correction on a signal from a transmission line or a recording medium, and outputting a coded signal and an uncorrectable signal, the coded signal and the uncorrectable signal A sync pattern is extracted from the signal, and a sync pattern detection unit that outputs a sync pattern detection signal, and the coded signal and the sync pattern detection signal are input,
Frame information extracting means for extracting and outputting the frame length information recorded at a predetermined position with respect to the synchronization pattern in the encoded signal, the synchronization pattern detection signal, the frame length information, and synchronization state information. From the synchronization state information, the determination timing generating means for outputting a predicted synchronization signal at the time when the next synchronization pattern should come according to the frame length information based on the synchronization pattern detection time, the uncorrectable signal and the synchronization pattern detection signal And a synchronization state determination means for inputting the predicted synchronization signal, determining the next state from the current synchronization state information by these signals, and outputting synchronization state information indicating a synchronization unlock state and a synchronization lock state, Input a coded signal, the prediction synchronization signal, and the synchronization state signal, and indicate the coded signal by the prediction synchronization signal. Based on the timing of, coded signal decoding apparatus characterized by having a decoding means for outputting a reproduced signal obtained by decoding the muting or coded signal frame according to the state indicated by the synchronization status information. 2. Use for decoding a coded signal in which a signal such as voice is coded in frame units, and a frame synchronization pattern for frame synchronization and frame information for transmitting information such as frame length are added to the coded signal. A coded signal decoding device for performing error correction on a signal from a transmission line or a recording medium, and outputting a coded signal and an uncorrectable signal, the coded signal and the uncorrectable signal A sync pattern is extracted from the signal, and a sync pattern detection unit that outputs a sync pattern detection signal, and the coded signal and the sync pattern detection signal are input,
Frame information extraction means for extracting and outputting the frame length information recorded at a predetermined position with respect to the synchronization pattern in the encoded signal; the synchronization pattern detection signal, the frame length information, and the first
From the synchronization state information of the first synchronization state information, the first determination timing for outputting the first predicted synchronization signal at the time when the next synchronization pattern should come based on the frame length information based on the synchronization pattern detection time. Generating means, the uncorrectable signal, the synchronization pattern detection signal, the first predictive synchronization signal, and the first state transition control signal are input, and the state transition is permitted by the first state transition control signal. In this case, first synchronization state determination means for determining the next state from the current first synchronization state information and outputting first synchronization state information indicating a synchronization unlock state and a synchronization lock state, and the synchronization pattern Detection signal, frame length information, and second
Second synchronization timing information based on the synchronization state detection time according to the second synchronization state information, and a second prediction synchronization signal is output at the time when the next synchronization pattern should come based on the frame length information. Generating means, the uncorrectable signal, the synchronization pattern detection signal, the second predictive synchronization signal, and the second state transition control signal are input, and the state transition is permitted by the second state transition control signal. In this case, a second synchronization state determination unit that determines the next state from the current second synchronization state information and outputs second synchronization state information indicating a synchronization unlock state and a synchronization lock state; From the first synchronization state information and the second synchronization state information by inputting the first synchronization state information, the first synchronization state information, the second prediction synchronization signal, and the second synchronization state information. Previous A first state transition control signal and a second state transition control signal for permitting a state transition of only one of the first synchronization state determination means and the second synchronization state determination means. State transition control means for outputting and outputting the predicted synchronization signal and synchronization state information of which transition is permitted as the third predicted synchronization signal and the third synchronization state information, respectively, the coded signal and the third state. The predicted synchronization signal and the third synchronization state signal are input, and the encoded signal is muted according to the state indicated by the third synchronization state information with reference to the timing indicated by the third predicted synchronization signal. A coded signal decoding device, comprising: decoding means for outputting a reproduction signal obtained by decoding one frame of the coded signal.