JPH0522461A - Synchronizing terminal station equipment - Google Patents

Synchronizing terminal station equipment

Info

Publication number
JPH0522461A
JPH0522461A JP3176415A JP17641591A JPH0522461A JP H0522461 A JPH0522461 A JP H0522461A JP 3176415 A JP3176415 A JP 3176415A JP 17641591 A JP17641591 A JP 17641591A JP H0522461 A JPH0522461 A JP H0522461A
Authority
JP
Japan
Prior art keywords
signal
clock
level
external
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3176415A
Other languages
Japanese (ja)
Inventor
Shigeru Kawabuchi
茂 河渕
Akira Watanabe
明 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP3176415A priority Critical patent/JPH0522461A/en
Publication of JPH0522461A publication Critical patent/JPH0522461A/en
Pending legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To eliminate the need for wiring with a clock supply device for an extended device. CONSTITUTION:A clock reception section 2 receives a clock signal 7 from a clock supply device 1. An IC level signal conversion section 9 converts a received clock signal 7 into a signal of an IC level and distributes the result. An external clock signal output section 5 outputs a signal converted into an IC level to an external device. An external clock signal input section 6 receives an external IC level signal. A clock selection section 3 selects either the distributed IC level signal or the external IC level signal and outputs the selected signal to a system section 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は同期端局装置に関し、特
に外部クロック入出力可能な入出力部を有する同期端局
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous terminal device, and more particularly to a synchronous terminal device having an input / output unit capable of inputting / outputting an external clock.

【0002】[0002]

【従来の技術】従来の同期端局装置は図2に示すよう
に、クロック供給装置22からのクロック信号25を受
けICレベルの信号に変換するクロック信号受信部21
と、ICレベル信号によって制御される複数のシステム
部23とを有して構成されている。
2. Description of the Related Art A conventional synchronous terminal device, as shown in FIG. 2, receives a clock signal 25 from a clock supply device 22 and converts it into an IC level signal.
And a plurality of system units 23 controlled by the IC level signal.

【0003】[0003]

【発明が解決しようとする課題】上述した同期端局装置
において、増設を行なった場合、図2に示すように、ク
ロック供給装置22からのクロック信号25は各同期端
局装置毎に供給される。この為増設が行なわれる毎にク
ロック供給装置22のクロック出力部24も増設する必
要がある。またクロック供給装置22と各同期端局装置
間の接続を行う必要もある。
When the above-mentioned synchronous terminal equipment is expanded, as shown in FIG. 2, the clock signal 25 from the clock supply device 22 is supplied to each synchronous terminal equipment. . Therefore, it is necessary to add the clock output unit 24 of the clock supply device 22 every time the addition is performed. It is also necessary to connect the clock supply device 22 and each synchronous terminal device.

【0004】[0004]

【課題を解決するための手段】本発明の同期端局装置
は、クロック供給装置からのクロック信号を受信する受
信部と、受信した前記クロック信号をICレベルに変換
して分配する信号変換部と、前記ICレベルに変換され
た信号を外部に出力する信号出力部と、外部からのIC
レベル信号を入力する信号入力部と、分配された前記I
Cレベル信号と外部からのICレベル信号との一方を選
択する選択部とを有する。
A synchronizing terminal device of the present invention comprises a receiving section for receiving a clock signal from a clock supply apparatus, and a signal converting section for converting the received clock signal into an IC level for distribution. A signal output unit for outputting the signal converted to the IC level to the outside, and an IC from the outside
A signal input section for inputting a level signal, and the I
It has a selection unit for selecting one of a C level signal and an IC level signal from the outside.

【0005】[0005]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例のブロック図である。
The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

【0006】本実施例は、クロック供給装置1のクロッ
ク信号に従属して動作する同期端局装置8において、ク
ロック供給装置1からのクロック信号7を受信するクロ
ック受信部2と、受信したクロック信号7をICレベル
に変換して分配するICレベル信号変換部9と、ICレ
ベルに変換された信号を外部に出力する外部クロック信
号出力部5と、外部からのICレベル信号を入力する外
部クロック信号入力部6と、分配されたICレベルの信
号と外部からのICレベル信号の一方を選択しシステム
部4に出力するクロック選択部3とを備えている。
In this embodiment, in the synchronous terminal device 8 which operates depending on the clock signal of the clock supply device 1, the clock receiving section 2 which receives the clock signal 7 from the clock supply device 1 and the received clock signal. An IC level signal converter 9 for converting 7 into an IC level for distribution, an external clock signal output unit 5 for outputting the signal converted into the IC level to the outside, and an external clock signal for inputting an IC level signal from the outside An input unit 6 and a clock selection unit 3 for selecting one of a distributed IC level signal and an external IC level signal and outputting the selected signal to the system unit 4 are provided.

【0007】このようにすると、増設装置10では、外
部クロック出力部15と増設架の外部クロック入力部1
6を接続する事によりクロック供給装置1から直接、ク
ロック信号7を受ける必要がなくなる。またクロック信
号受信部12とICレベル変換部19とが必要なくな
る。
In this way, in the expansion device 10, the external clock output unit 15 and the external clock input unit 1 of the expansion rack are installed.
The connection of 6 eliminates the need to receive the clock signal 7 directly from the clock supply device 1. Further, the clock signal receiving section 12 and the IC level converting section 19 are unnecessary.

【0008】[0008]

【発明の効果】以上説明したように本発明は、クロック
供給装置からのクロック信号をICレベルに変換して分
配する回路と、ICレベルに変換された信号を外部に出
力する回路と、外部からのICレベル信号の一方を選択
する回路とを備えることにより、同期端局装置が増設さ
れるたびにクロック供給装置のクロック出力部を増設す
る必要がなくなる。また、クロック供給装置と同期端局
装置間の配線数も減少する。また同期端局装置が隣接す
る場合には外部クロック出力部のクロック信号を外部信
号入力部に入力することにより、クロック信号受信部が
不要となるという効果を有する。
As described above, according to the present invention, a circuit for converting a clock signal from a clock supply device to an IC level for distribution, a circuit for outputting a signal converted to the IC level to the outside, and an external circuit. By providing a circuit for selecting one of the IC level signals of 1), it is not necessary to add the clock output unit of the clock supply device every time the synchronous terminal device is added. Also, the number of wires between the clock supply device and the synchronous terminal device is reduced. Further, when the synchronous terminal devices are adjacent to each other, by inputting the clock signal of the external clock output section to the external signal input section, there is an effect that the clock signal receiving section becomes unnecessary.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】従来の同期端局装置の一例のブロック図であ
る。
FIG. 2 is a block diagram of an example of a conventional synchronous terminal device.

【符号の説明】[Explanation of symbols]

1 クロック供給装置 2,12 クロック受信部 3,13 クロック選択部 4,14 システム選択部 5,15 外部クロック信号出力部 6,16 外部クロック信号入力部 7 クロック信号 8 同期端局装置 9,19 ICレベル信号変換部 1 Clock Supply Device 2, 12 Clock Reception Unit 3, 13 Clock Selection Unit 4, 14 System Selection Unit 5, 15 External Clock Signal Output Unit 6, 16 External Clock Signal Input Unit 7 Clock Signal 8 Synchronous Terminal Equipment 9, 19 IC Level signal converter

Claims (1)

【特許請求の範囲】 【請求項1】 クロック供給装置からのクロック信号を
受信する受信部と、受信した前記クロック信号をICレ
ベルに変換して分配する信号変換部と、前記ICレベル
に変換された信号を外部に出力する信号出力部と、外部
からのICレベル信号を入力する信号入力部と、分配さ
れた前記ICレベル信号と外部からのICレベル信号と
の一方を選択する選択部とを有することを特徴とする同
期端局装置。
Claim: What is claimed is: 1. A receiving unit that receives a clock signal from a clock supply device, a signal conversion unit that converts the received clock signal into an IC level and distributes it, and a signal conversion unit that converts the received clock signal into the IC level. A signal output unit for outputting the external signal to the outside, a signal input unit for inputting an external IC level signal, and a selection unit for selecting one of the distributed IC level signal and the external IC level signal. A synchronous terminal device having.
JP3176415A 1991-07-17 1991-07-17 Synchronizing terminal station equipment Pending JPH0522461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3176415A JPH0522461A (en) 1991-07-17 1991-07-17 Synchronizing terminal station equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3176415A JPH0522461A (en) 1991-07-17 1991-07-17 Synchronizing terminal station equipment

Publications (1)

Publication Number Publication Date
JPH0522461A true JPH0522461A (en) 1993-01-29

Family

ID=16013293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3176415A Pending JPH0522461A (en) 1991-07-17 1991-07-17 Synchronizing terminal station equipment

Country Status (1)

Country Link
JP (1) JPH0522461A (en)

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