JPH05226372A - Field-effect transistor and low noise amplifier circuit using same - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a high-performance low-noise amplifier using the FET, which can suppress the decrease in carrier mobility that greatly contributes to the performance of the FET device. [Structure] The channel has a multi-layer structure having different carrier mobilities, and a material having a large band gap and a large carrier mobility is used for the central layer. [Effect] Carriers are confined in the central portion of the channel, the spread of carrier distribution to the carrier supply layer is suppressed, and the observed carrier mobility is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor manufactured by epitaxial growth, and more particularly to a compound semiconductor field effect transistor having a large carrier mobility and a low noise, which has a large influence on its performance, and a field effect transistor using the same. The present invention relates to a low noise amplifier circuit.

[0002]

2. Description of the Related Art F produced by epitaxial growth
The channel of ET (Field Effect Transistor) is, for example, in Japanese Patent Application No. 1-94675 in HEMT (High Electron Mobility Transistor) using GaAs as a channel material, and in InGaAs channel HEMT of higher performance. In the specification of Japanese Patent Application No. 64-66972, and in the case of using InP as a substrate material, Japanese Patent Application No. 3-50839
As described in the specification, it was formed of only a single semiconductor layer.

[0003]

Transconductance is one of the important performance indexes of FETs. When the voltage applied to the gate is close to the threshold voltage, the transconductance is proportional to the carrier mobility, so that it can be said that the carrier mobility influences the performance in this region. The improvement of carrier mobility is achieved by reducing the influence of a scattering source which causes mobility reduction or by using a high mobility material.

Impurity scattering, which is the main cause of the decrease in mobility, is improved by the HEMT structure as shown in FIG. 2, that is, by spatially separating the carrier supply layer and the channel, and between the carrier supply layer and the channel layer. It is further improved by increasing the width of the spacer layer. For example, in the case of a GaAs channel HEMT, when the spacer layer width is 20 nm or more, the electron mobility is about 8000 cm ² / Vs, which is the maximum attainable by GaAs. However, if the spacer layer width is too large, the number of carriers generated in the channel decreases, and as a result, mutual conductance also decreases. In the usual case, the optimum width of the spacer layer is about 2 to 4 nm, and the electron mobility at this time is about 5000 cm ² / Vs. Although InGaAs has been used as a high mobility material, this material has a larger lattice constant than GaAs, and dislocations occur in the channel when the layer thickness increases, so that the characteristics as a high mobility material are effective. It was not available.

Further, in mobile communication terminals such as cellular phones and cordless phones, there is an increasing demand for miniaturization and low power consumption. Therefore, low current operation is required even for devices such as FETs. However, in a low current operation, the transconductance generally decreases significantly, and the noise figure, which is an index of noise characteristics, increases.

A first object of the present invention is to provide a structure having a large electron mobility that greatly contributes to the performance of FET devices, and a second object is to provide a high performance low noise amplifier.

[0007]

The above-mentioned first object is as shown in FIG.
As described above, it is achieved by a structure in which a semiconductor material having a high electron mobility and a small band gap is arranged in the center of the channel. The second object is achieved by constructing a circuit using the above FET.

[0008]

FIG. 3 shows a schematic view of the band structure and electron density distribution under the gate electrode of the conventional HEMT. In the normally used current region, the electron density distribution is large in the central portion of the channel as shown in FIG. The electrons that have spread to the carrier supply layer 9 are more likely to be scattered than the electrons that move in the channel, leading to a decrease in the mobility of the entire channel. Further, the distribution of electrons to the spacer layer side is not preferable due to the influence of diffusion of impurities not included in the calculation.
Further, the electrons bleeding to the substrate side change according to the magnitude of the voltage applied to the gate. This means that the change of the transconductance with respect to the gate voltage changes in a multi-dimensional function, and the output distortion becomes large when used in an amplifier or the like.

FIG. 4 shows the band structure and electron density distribution under the gate electrode of the FET of the present invention. In the figure, a material having a large mobility and a small band gap is used in the central portion (semiconductor layer 2) of the channel. Most of the carriers are distributed in the semiconductor layer 2 having high mobility, and most of the remaining electrons are distributed in the semiconductor layers 1 and 3, and electrons oozing into the carrier supply layer are uniform channels. Significantly less than.

FIG. 5 shows the channel thickness dependence of the mutual conductance of the field effect transistor according to the embodiment of the present invention. At this time, the device has a gate length of 0.1 μm and a gate width of 200 μm, and the source-drain voltage is 2 μm.
The figure shows the operation at V and drain current of 2 mA.

As the channel thickness increases, the transconductance decreases, but especially when the gate thickness is 20 nm. This is because the electron mobility distribution shown in Fig. 4 must be obtained as a necessary condition for increasing the observed mobility, that is, the channel can be regarded as a quantum well, and the center of gravity of the electron distribution is near the center of the channel. caused by. When the channel thickness is 20 nm, the energy difference between the ground level and the first excitation level of the quantum levels generated in the channel is about 60 me.
It becomes V. This means that the electron distribution of the channel at the gate voltage at the time of 2 mA operation is the minimum energy difference satisfying the condition of the electron distribution, and for this purpose, the thickness of the channel needs to be 20 nm or less. I understand.

When the electrons occupy only the ground level of the quantum well, 50 out of the region from the center to the end of the channel.
The number of electrons existing in% is about 90 of the electrons in the entire channel.
%. In a region narrower than this, the number of electrons is significantly reduced, and the effect of the superlattice channel is diminished. Therefore, the effect is particularly remarkable when the central semiconductor layer thickness is 50% or more of the channel layer thickness. Further, as the thickness of the semiconductor layer 3 increases, the electric field strength between the semiconductor layer 3 and the carrier supply layer decreases, and the concentration of the two-dimensional electron gas accumulated in the channel decreases.

When the spacer layer width between the carrier supply layer and the channel is 2 nm, which is usually used, when InGaAs having an In composition of 0.3 is used as the semiconductor layer 2 and GaAs is used as the semiconductor layer 3, The thickness of the semiconductor layer 3 is 5
Below nm, the maximum value of the two-dimensional electron gas concentration is 1.2 × 1
It is 0 ¹² / cm ² , which is about the same as the conventional structure in the GaAs channel. If the semiconductor layer 3 becomes thicker than this, the maximum value of the two-dimensional electron gas concentration will drastically decrease, the source resistance will increase, and as a result, the mutual conductance will decrease. Therefore, the effect is remarkable when the thickness of the semiconductor layer 3 is 5 nm or less. When such a condition is satisfied, the observed electron mobility increases and the mutual conductance also increases. In addition, since the change in the center of gravity of the electron distribution with respect to the change in the gate voltage is small, the amplifier circuit and mixer using this element have low noise and high gain, and the output distortion is small.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. Hereinafter, as a material description, AlGaAs means that some of Ga atoms in GaAs are replaced with Al, and InGaAs means that some of Ga atoms in GaAs is replaced by In.

<Embodiment 1> FIG. 6 shows a sectional view of an embodiment of the present invention. First, MB on the semi-insulating GaAs substrate 6
Undoped GaA by E (Molecular Beam Epitaxy)
s (thickness: 200 nm) 7, undoped AlGaAs /
Undoped GaAs superlattice layer (thickness: 3/50 nm ×
5) 14, undoped AlGaAs buffer layer (Al composition 0.3, thickness: 20 nm) 15, channel layer (undoped GaAs (thickness: 2 nm) 2, undoped InGa)
As (In composition 0.4, 4 nm) 3, undoped GaA
s (thickness: 2 nm) 4), undoped AlGaAs spacer layer (Al composition 0.3, 2 nm) 8, n-AlGaA
s carrier supply layer (Al composition: 0.3, 10 nm, Si concentration: 5 × 10 ¹⁸ / cm ³ ) 9, undoped AlGaAs layer (Al composition: 0.3, 15 nm) 10, and finally n-GaAs cap layer (Si concentration: 7 × 10 ¹⁹ / c
m ³ , 160 nm) 16 is deposited.

After element isolation is performed by mesa etching, a SiO ₂ film is vapor-deposited, and holes for the source electrode 11 and the drain electrode 12 are formed by a normal photolithography process. The SiO ₂ film on the surface of this hole is ground by dry etching to remove the n-GaAs cap layer 16 by 4 times.
About 0 nm is opened by wet etching. Furthermore S
Side-etch the iO ₂ film by wet etching,
Make the shape easy to lift off. AuZn / M on top of this
vapor deposition of o / Au and heat treatment in a nitrogen atmosphere (400 ° C,
5 minutes). Further, a gate pattern is formed by using an EB (electron beam) drawing method. Next, by wet etching and selective dry etching, undoped Al is well controlled.
The GaAs layer 10 was removed by etching up to the front. Further, Al was vapor-deposited and then lifted off to form a gate electrode 13 having a gate length of 0.1 μm and a gate width of 200 μm. In this way, the FET having the structure shown in FIG. 5 was realized.

The device according to the present embodiment has a withstand voltage: 6 V, a source resistance R: 0.6 Ω · mm, a mutual conductance g at a drain current of 2 mA, g: 175 mS / mm, 12 GHz.
In the figure, the noise figure NF was 0.4 and the performance was high.

In the epitaxial crystal growth in the manufacturing process, the same result can be obtained by using an apparatus capable of controlling the growth in atomic layer units instead of MBE shown here, such as MOCVD. Also, the cap layer 1
The material of 6 is not limited to GaAs, but a material that easily forms ohmic contact, such as InGaAs, may be used. Further, the undoped AlGaAs layer 10 just below the gate has an n-AlG density of 1 × 10 ¹⁸ / cm ² or less so as not to reduce the breakdown voltage.
aAs may be used. Although the buffer layer 15 may be omitted, the transconductance is affected in the operation in the region where the drain current is small. Further, if the Al composition is too small, the pinch-off characteristic deteriorates, and if it is too large, the crystallinity deteriorates. Therefore, in the usual case, an Al composition of 0.2 to 0.5 and a thickness of 5 nm to 100 nm are preferable. The results are shown.

In this embodiment, the Al composition of the AlGaAs layer is 0.3, but the same result can be obtained by using a value of 0.15 to 0.4. The channel layer is I
Although InGaAs having an n composition of 0.4 was used, it was 0.2 to 0.0.
The In composition may be about 6 and the thickness may be such that dislocations do not enter, and the channel layers 2 and 4 are made more In than the channel layer 3.
InGaAs having a small composition may be used, or the materials of the two semiconductor layers may be different. Further, the channel layer is not limited to the three-layer structure, but may have a structure in which the In composition changes stepwise or a superlattice structure in which the material is different for each atomic layer. The material is not limited to InGaAs, but GaA
sSb may be used, and the layer structure is GaAs / AlG.
Not limited to aAs, for example, InGaAs / InAlAs
Similar results are obtained when a combination of materials such as InAs / (Al, Ga) (Sb, As) is used. The substrate material is not limited to GaAs, and InP or the like may be used.

In this embodiment, an example of an N-channel field effect transistor is shown, but good results can be obtained with a P-channel. In this case, this is achieved by making the N-doped layer of this embodiment a P-doped layer.

Although the present embodiment describes the HEMT, it goes without saying that good results can be obtained even when applied to another heterojunction element, that is, a HIGFET or the like.

<Embodiment 2> FIG. 7 shows a sectional view of an embodiment of the present invention. First, MBE is applied on the semi-insulating InP substrate 6.
(Molecular beam epitaxy) device enables undoped InGa
As (In composition 0.5, thickness: 200 nm) 7, undoped InAlAs buffer layer (In composition 0.5, thickness:
20 nm, 15, channel layer (undoped InGaAs)
(In composition 0.3, thickness: 2 nm) 2, undoped In
GaAs (In composition 0.7, 4 nm) 3, undoped In
GaAs (In composition: 0.3, thickness: 2 nm) 4), undoped InAlAs spacer layer (In composition: 0.5, 2n)
m) 8, n-InAlAs carrier supply layer (In composition 0.5, 10 nm, Si concentration: 5 × 10 ¹⁸ / cm ³ ) 9, undoped InAlAs layer (In composition 0.5, 15 nm)
10 is grown, and finally an n-InGaAs cap layer (Si concentration: 7 × 10 ¹⁹ / cm ³ , 160 nm) 16 is deposited.

After element isolation is performed by mesa etching, a SiO ₂ film is vapor-deposited, and holes for the source electrode 11 and the drain electrode 12 are formed by a normal photolithography process. The SiO ₂ film on the surface of the hole is ground by dry etching to remove the n-InGaAs cap layer 16
Is bored by wet etching to about 40 nm. Further, the SiO ₂ film is side-etched by wet etching to form a shape that facilitates lift-off. AuZn on this
/ Mo / Au by vapor deposition and heat treatment (400
℃, 5 minutes). Further, a gate pattern is formed by using an EB (electron beam) drawing method. Next, by wet etching and selective dry etching, the undoped AlGaAs layer 10 was etched and removed with good controllability. Further, Al is vapor-deposited and then lifted off to obtain a gate electrode 13 having a gate length of 0.1 μm and a gate width of 200 μm.
Formed. In this way, the FE having the structure shown in FIG.
Realized T.

The device according to this embodiment has a withstand voltage: 6 V, R =
0.5 Ω ・ mm, g = 203 mS / mm, NF = 0.35 dB
And showed high performance.

In the epitaxial crystal growth in the manufacturing process, a similar result can be obtained by using an apparatus capable of controlling the growth in atomic layer units instead of MBE shown here, such as MOCVD. The undoped InAlAs layer 10 just below the gate may be made of n-InAlAs of 1 × 10 ¹⁸ / cm ² or less, as long as the breakdown voltage is not reduced. Although the buffer layer 15 may be omitted, the transconductance is affected in the operation in the region where the drain current is small. Further, if the Al composition is too small, the pinch-off characteristic deteriorates, and if it is too large, the crystallinity deteriorates.
Normally, Al composition is 0.2 as InAlGaAs.
.About.0.5 and a thickness of 5 nm to 100 nm show good results.

In this embodiment, In is used as the carrier supply layer.
An AlAs layer was used, but InA with a Ga composition of 0.3 or less was used.
Similar results can be obtained using lGaAs. Further, although InGaAs having an In composition of 0.7 was used for the channel layer,
The In composition may be about 0.5 to 1.0 and the thickness may be such that dislocations do not enter, and the channel layers 2 and 4 may be InGaAs having an In composition smaller than that of the channel layer 3,
The materials of the two semiconductor layers may be different.
Further, the channel layer is not limited to the three-layer structure, but may have a structure in which the In composition changes stepwise or a superlattice structure in which the material is different for each atomic layer. The material is not limited to InGaAs, GaAsSb may be used, and the layer structure is InG.
Not limited to aAs / InAlAs, but InGaAs /
InAlAs / InAlGaAs or InGaAs / (I
Similar results are obtained with combinations of materials such as n, Al, Ga) (Sb, As).

Although the present embodiment describes the HEMT, it goes without saying that good results can be obtained even when applied to other heterojunction elements, that is, HIGFET and the like.

<Third Embodiment> FIG. 8 shows a circuit diagram of an embodiment of the present invention. The FET described in the first or second embodiment is formed on a semiconductor substrate. At that time, a matching circuit using strip lines and capacitors is formed on the same substrate as shown in FIG. The low noise amplifier obtained in this way is FET
1 drain voltage 106 and FET 2 drain voltage 1
07 is 2.5V, the drain current of the first stage FET1 is 6m
A, good performance with a minimum noise figure of 1.0 dB at 12 GHz and a gain of 18.5 at 12 GHz was obtained under the condition that the drain current of the FET 2 in the next stage was 10 mA.

Although the example of the two-stage amplifier is shown in this embodiment, a good result can be obtained even with the one-stage amplifier. Also,
Although an example of a so-called monolithic IC in which the matching circuit is on the same substrate is shown, a good result can be obtained even with a hybrid IC which is slightly deteriorated in performance but is easily manufactured, that is, the matching circuit is not on the same substrate.

In the present embodiment, only the low noise amplifier in the 12 GHz band is described, but good characteristics were obtained in other frequency bands by changing the matching circuit. Also this
Good characteristics can be obtained even if the FET is used in other circuits such as a mixer.

[0031]

According to the present invention, a field effect transistor whose performance is improved by high carrier mobility can be obtained, and when applied to a low noise amplifier or the like, a great effect can be obtained.

[Brief description of drawings]

FIG. 1 is an explanatory diagram in the vicinity of a channel of an FET showing an embodiment of the present invention.

FIG. 2 is a sectional view of a HEMT showing a conventional example.

FIG. 3 is a band structure and electron density distribution chart near a channel of a HEMT showing a conventional example.

FIG. 4 is a band structure and electron density distribution diagram near a channel of a HEMT showing an embodiment of the present invention.

FIG. 5 is an explanatory diagram of channel thickness dependence of transconductance of HEMT showing an example of the present invention.

FIG. 6 is a sectional view of a HEMT showing an embodiment of the present invention.

FIG. 7 is a sectional view of a HEMT showing an embodiment of the present invention.

FIG. 8 is a system diagram of a low noise amplifier using HEMT showing an embodiment of the present invention.

[Explanation of symbols]

1 ... Buffer layer, 2 ... Undoped GaAs channel layer,
3 ... Undoped InGaAs channel layer, 4 ... Undoped GaAs channel layer, 5 ... Barrier layer.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Masao Yamane Inventor Masao Yamane 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Design Development Center

Claims (10)

[Claims] 1. A field effect transistor, wherein a channel layer is formed of two or more kinds of semiconductor layers having different carrier mobilities, and a semiconductor layer having a relatively high carrier mobility is used in a central portion of the channel. And a field effect transistor. 2. A field effect transistor, wherein a channel layer is formed of two or more kinds of semiconductor layers having different band gaps, and the semiconductor layer having a relatively small band gap is used in a central portion of the channel. Field effect transistor to be. 3. The channel according to claim 1, wherein the channel is composed of three layers, and the semiconductor layer on the substrate side and the semiconductor layer on the front surface side are different from a semiconductor layer sandwiched between the same material or two semiconductor layers. A field effect transistor that is a material. 4. The field effect transistor according to claim 3, wherein the thickness of the channel layer is 20 nm or less, and the thickness of the semiconductor layer on the front surface side is 50% or more of the channel layer thickness. 5. The field effect transistor according to claim 3, wherein the thickness of the semiconductor layer on the front surface side is 5 nm or less. 6. The method according to claim 1, 2, 3, 4 or 5.
The channel material is such that when the semiconductor substrate is GaAs, the substrate-side semiconductor layer and the surface-side semiconductor layer are GaAs,
Alternatively, it is InGaAs having a relatively low In concentration, and the sandwiched semiconductor layer is InGa having a relatively high In concentration.
As, and when the semiconductor substrate is InP, the substrate-side semiconductor layer and the surface-side semiconductor are InGaAs having a relatively low In concentration, and the sandwiched semiconductor layer is relatively I.
A field-effect transistor made of InGaAs having a large n concentration, and having an In composition and a film thickness such that dislocations do not enter the channel. 7. The lattice constants of the substrate-side semiconductor layer and the surface-side semiconductor layer and the semiconductor layer sandwiched therebetween are shifted in the opposite direction with respect to the lattice constant of the substrate, so that strain is offset in the entire channel. -Effect transistor using various materials. 8. The field effect transistor according to claim 1, wherein a channel layer of the field effect transistor is an undoped layer which does not intentionally contain impurities, and N
To a field effect transistor having a HEMT structure, which is spatially separated from a carrier supply layer containing a P-type impurity. 9. The semiconductor material according to claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein the buffer layer, that is, the semiconductor layer on the substrate side of the channel layer, is made of a semiconductor material having a bandgap larger than that of the channel layer. Field effect transistor used. 10. A low noise amplifier circuit using the field effect transistor according to claim 1 for a low noise amplifier.