JPH05226376A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] [Object] To reduce the contact resistance between a channel layer or a base layer and a contact layer in an FET or a bipolar transistor. [Configuration] For example, in an FET, an InGaAs buffer layer 4 is provided on the substrate side of an InGaAs channel layer 5,
Due to the effect of wraparound of carriers passing through this layer, In
The GaAs channel layer 5 and the contact layer 5 are brought into contact with each other with low resistance. [Effect] InGaAs channel layer 5 and contact layer 8
The contact resistance of can be reduced to 10Ω per 10 μm width, and as a result, the value of the transconductance coefficient K of the FET can be reduced to 10
It can be improved up to 14 mA / V ² per μm.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique suitable for application to a field effect transistor and a bipolar transistor using a III-V group compound semiconductor.

[0002]

2. Description of the Related Art For example, in order to improve the performance of a GaAs / AlGaAs heterojunction field effect transistor, it is necessary to reduce the source resistance. Therefore, a method has been devised to reduce the source resistance by using a high-concentration contact layer formed by a selective growth technique in the contact portion between the source electrode and the semiconductor layer.

For example, in Japanese Patent Application No. 2-268361,
The following methods are described.

FIG. 2 is a sectional view of this conventional field effect transistor. N-type Ga on the semi-insulating GaAs substrate 1
After epitaxially growing the active layer having the As channel layer 105, the active layer in the contact portion is removed by etching, and then the high concentration n is formed in the contact portion by the MOCVD method.
The type GaAs contact layer 8 is selectively grown. In this method, the source resistance is reduced due to the structure in which the channel layer 105 and the contact layer 8 are in direct contact with each other.

Further, in order to improve the performance of the GaAs / AlGaAs heterojunction bipolar transistor, it is necessary to reduce the base resistance. Here, too, a resistance reduction method using a high-concentration contact layer formed by the selective growth technique has been devised. (For example, IEICE Technical Report ED90-136, 25
page)

[0006]

In the above-mentioned prior art, GaAs is used as the material of the channel layer or the base layer, but if InGaAs is used instead of it, the electron saturation speed can be improved and the doping concentration can be increased. Performance improvement can be expected.

However, when InGaAs is used for the channel layer or the base layer, there is a problem that the contact resistance between the channel layer or the base layer and the contact layer increases.

An object of the present invention is to provide a structure of a semiconductor device having a contact portion having a small contact resistance between a conductive layer such as a channel layer or a base layer and a contact layer separate from the conductive layer, and a method of manufacturing the same. To do.

[0009]

The above object is to bring a semiconductor layer (hereinafter referred to as a carrier sneaking path forming layer), which is made of a material having a carrier band level continuous with the material of the conductive layer, into contact with the conductive layer, and This can be achieved by the structure of the semiconductor device formed so as to be in direct contact with the contact layer via the conductive layer or without the conductive layer. Here, a material whose band level is continuous with the material of the conductive layer refers to a semiconductor layer having an electron affinity equal to that of the material of the conductive layer when the conductive layer is n-type, and a material of the conductive layer when the conductive layer is p-type. It refers to a semiconductor layer having the same material, electron affinity, and bandgap sum.

Further, the above-mentioned object is to form a semiconductor layer which becomes an active part of a device such as a conductive layer and a carrier sneak path forming layer on a substrate, and thereafter etch away the semiconductor layer in a region where a contact layer is formed. This can be achieved by a method of manufacturing a semiconductor device in which a contact layer is formed in the etching removed portion by selective growth.

[0011]

The function of the present invention will be described below. 3 (a) and 3 (b) are diagrams for explaining the cause of increase in contact resistance in the field effect transistor.
FIG. 6 is a cross-sectional view of a contact portion in the case of an s channel layer and the case of an InGaAs channel layer.

The first cause of the increase in contact resistance is that a high-concentration interface state is generated in the contact portion between the undoped AlGaAs layer 6 and the n-type GaAs contact layer 8, and the channel layer 10
This is considered to be due to the effect of depleting the vicinity of the contact portion between the contact layers 5 and 5 and the contact layer 8.

The second cause is as follows. The depletion effect exists for both GaAs channel 105 and InGaAs channel 5. However, as shown in FIG. 3A, in the case of the n-type GaAs channel 105, since the substrate side of the channel layer 105 is the buffer layer 3 also made of GaAs, carriers easily move around the substrate side of the depleted region 202. And reaches the channel layer 105 through the carrier rounding path 203 formed in the buffer layer 3. Therefore, the contact portion has a low resistance and causes no problem. On the other hand, as shown in FIG. 3B, the n-type I
When nGaAs is used, since the buffer layer 3 on the substrate side of the n-type InGaAs channel layer 5 is made of GaAs, the junction surface between the two is the hetero junction surface 204, and the conduction band in the band diagram is discontinuous. As a result, the wraparound of carriers from the substrate side is obstructed by the InGaAs / GaAs hetero interface 204, and the contact portion has a high resistance (for example, 1 k to 100 kΩ). Therefore, the second cause of the increase in contact resistance is that the layer existing in contact with the channel layer forms a heterojunction (band discontinuity) with the channel layer.

Here, the concentration of the generated interface state differs depending on the material. Among the III-V group compound semiconductors, AlGaAs containing Al has a higher interface state concentration than others.

Also in the case of a GaAs / AlGaAs heterojunction bipolar transistor, the contact resistance increases due to the same cause as in the case of a field effect transistor. In this case, the channel layer and the buffer layer of the field effect transistor may be replaced with the base layer and the collector layer of the bipolar transistor, respectively.

Further, the object of the present invention is not limited to the field effect transistor or the bipolar transistor as long as it is a semiconductor device in which the contact failure occurs.

In the present invention, since the carrier sneak path forming layer in which the band related to the carrier is continuous with the conductive layer is provided, the carriers in the contact layer flow into the conductive layer through the carrier sneak path forming layer. Alternatively, conversely, carriers in the conductive layer flow into the contact layer via the carrier sneak path forming layer. As a result, it is possible to alleviate the interference of carriers from wrapping around due to band discontinuity on the heterojunction surface, and it is possible to obtain a contact portion with low resistance.
FIG. 1 is a sectional view of an example of a field effect transistor according to the present invention, and FIG. 4 is a view showing a band structure of the field effect transistor of FIG. For example, InGaAs channel layer 5
From the InGaAs layer 4 or InGaAs to the substrate side of G
The graded layer 4 having the In composition changed to aAs is inserted (see FIGS. 1 and 4). This makes InGaAs
/ GaAs heterojunction surface (junction surface between the layers 5 and 3) is suppressed by the discontinuity of carriers due to band discontinuity, and the contact portion has a low resistance as in the case of using GaAs as the channel layer.

The formation place of the carrier sneak path forming layer is on the substrate side with respect to the conductive layer in FIGS. 1 and 4.
It is clear from the technical idea of the present invention that the side opposite to the substrate may be used.

Further, from the technical idea of the present invention, Ga
It is clear that the As layer 3 may be omitted and that the contact layer and the conductive layer may not be in contact with each other.

Further, the undoped AlGaAs layer 6 is
In particular, the interface states are often generated, but the interface states are also generated in the InGaAs channel layer 5, and there is a depletion layer generated thereby. Therefore, the present invention is also effective for a semiconductor device having a structure that does not have the undoped AlGaAs layer 6.

[0021]

EXAMPLE Example 1 This example is an application example to a field effect transistor.
FIG. 3 is a sectional view of the field effect transistor of the first embodiment of the present invention. The manufacturing method is shown below.

Semi-insulating GaAs substrate 1 by MBE method
An undoped GaAs layer (thickness 300 nm) 2, p-type GaAs layer (Be impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 30)
0 nm) 3, p-type InGaAs layer (In composition 0.2, B
e Impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 15 nm 4 4, n-type InGaAs layer (In composition 0.2, Si impurity concentration 1 ×)
10 ¹⁹ / cm ³ , thickness 5 nm) 5, undoped AlGaAs
Layer (Al composition 0.3, thickness 10 nm) 6, undoped G
An aAs layer (thickness: 35 nm) 7 is sequentially grown. The substrate temperature during growth was set to 480 to 540 ° C., carrier compensation, re-evaporation of In, and diffusion of impurities were suppressed.

Here, the p-type InGaAs layer 4 and the n-type In
Since the GaAs layer 5 has a different lattice constant from the underlying GaAs, crystal defects occur in these layers if they are too thick (exceeding the critical thickness). Therefore, it is necessary to set the total thickness of those layers to be equal to or less than the critical film thickness. In this embodiment, the total thickness of those layers is 20 nm.
To prevent crystal defects from entering.

Next, the semiconductor layer at the contact portion is etched by 50 to 150 nm from the surface by the ECR plasma etching method using SiCl ₄ gas, and then M
The n-type GaAs layer (S
An impurity concentration of 1 × 10 ¹⁹ / cm ³ and a thickness of 700 nm) 8 is selectively grown. The substrate temperature during the selective growth was 540 ° C., and I
The diffusion of impurities in the nGaAs channel layer was suppressed.

Next, n-type GaAs is formed by the lift-off method.
On the layer 8, a source electrode 9 of a AuGe / Ni / Au laminated film,
The drain electrode 10 is formed and alloying treatment is performed at 400 degrees. The undoped GaAs 7 in the gate electrode forming portion is removed by etching by the reactive ion etching method using CCl ₂ F ₂ gas, and then Ti / Ti is removed by the lift-off method.
A gate electrode 11 of a Pt / Au laminated film is formed.

In the field effect transistor manufactured by the above process, the n-type InGaAs layer 5 and the n-type GaAs are formed by the effect of inserting the p-type InGaAs layer 4 serving as a carrier conduction auxiliary layer on the substrate side of the n-type InGaAs channel layer 5.
The contact resistance of layer 8 could be reduced to 10Ω per 10 μm width. As a result, since the source resistance is as small as 25Ω per 10 μm width, the value of transconductance coefficient K is 10 μm width.
As a result, a good transistor characteristic with a large mutual conductance of 14 mA / V ² was realized.

Further, in this embodiment, the carrier conduction auxiliary layer is provided on the substrate side with respect to the channel layer, but it goes without saying that the effect of the present invention can be obtained even if it is provided on the opposite side to the substrate. However, the distance from the gate to the channel layer becomes long, and the practicability as a field effect transistor decreases.

Second Embodiment A second embodiment of the present invention will be described with reference to the sectional view of FIG. This embodiment is also an application example to a field effect transistor. The manufacturing method is shown below.

Semi-insulating GaAs substrate 1 by MBE method
An undoped GaAs layer (thickness 300 nm) 2, p-type GaAs layer (Be impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 30)
0 nm) 3, p-type InGaAs layer (In composition 0.2, B
e Impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 15 nm 4 4, n-type InGaAs layer (In composition 0.2, Si impurity concentration 1 ×)
10 ¹⁹ / cm ³ , thickness 5 nm) 5, undoped AlGaAs
A layer (Al composition 0.3, thickness 10 nm) 6 is sequentially grown. The substrate temperature during growth was set to 480 to 540 ° C., carrier compensation, re-evaporation of In, and diffusion of impurities were suppressed.

Next, by dry etching using NF ₃ gas, WSi / WSi / is formed on the undoped AlGaAs layer 6.
The gate electrode 11 of the W laminated film is formed.

The semiconductor layer at the contact portion is etched by 15 to 50 nm from the surface by the ECR plasma etching method using SiCl ₄ gas. Then CH ₃ B
The p-type GaAs layer 3, the p-type InGaAs layer 4, and the n-type InGaAs layer 5 are selectively set to 1 with respect to the undoped AlGaAs layer 6 by an optical dry etching method using r gas.
00nm isotropic etching, undoped AlGaAs
The underside of layer 6 is undercut. Then MOCV
By the D method, an n-type GaAs layer (Si impurity concentration 1 × 10 ¹⁹ / cm ³ , thickness 700 nm) 8 is selectively grown on the contact portion. The substrate temperature during the selective growth is 540 ° C. and InGa
The diffusion of impurities in the As channel layer 5 was suppressed.

The source electrode 9 and the drain electrode 10 of the AuGe / Ni / Au laminated film are formed on the n-type GaAs layer 8 by the lift-off method, and are alloyed at 400 degrees.

In the field effect transistor manufactured by the above process, p-type InGa is formed on the substrate side of the n-type InGaAs layer 5.
Due to the effect of inserting the As layer 4, the n-type InGaAs layer 5
And the contact resistance of the n-type GaAs layer 8 per 10 μm width
It was possible to reduce to Ω. Further, in this embodiment, the n-type GaAs layer 8 was brought close to the gate electrode 11 by undercutting, so that the parasitic resistance below the undoped AlGaAs layer 6 could be reduced to 2Ω. As a result, the source resistance could be reduced to 17Ω per 10 μm width.

Third Embodiment A third embodiment of the present invention will be described with reference to the sectional view of FIG. This embodiment is also an application example to a field effect transistor.

In this embodiment, as the contact layer, n-type InGaAs is used instead of the n-type GaAs layer 8 of the first embodiment.
Layer (In composition 0.2, Si impurity concentration 1 × 10 ¹⁹ / cm ³ ,
A laminated structure of a 20 nm thick 13 and an n-type GaAs layer 8 (Si impurity concentration 1 × 10 ¹⁹ / cm ³ , thickness 680 nm) 8 is used. The other structure and manufacturing method are similar to those of the first embodiment.

In the first embodiment, the contact portion between the n-type InGaAs layer 5 and the n-type GaAs layer 8 having a small contact area is a heterojunction, and the notch generated in the band structure of the junction portion adversely affects the contact resistance. .. In the present embodiment, the contact portion between the n-type InGaAs layer 5 and the n-type InGaAs layer 13 having a small contact area has a homojunction and an n-type I which is a heterojunction.
Since the contact area between the nGaAs layer 13 and the n-type GaAs layer 8 has a large contact area, the increase in contact resistance due to the notch of the band structure can be ignored.

In the present embodiment, the effect of inserting the p-type InGaAs layer 4 on the substrate side of the n-type InGaAs layer 5 and the n-type Ga.
Due to the effect of inserting the n-type InGaAs 13 on the substrate side of the As layer 8, the contact resistance between the n-type InGaAs layer 5 and the n-type GaAs layer 8 could be reduced to 6Ω per 10 μm width. As a result, the source resistance was 21Ω per 10 μm width, and the K value was 15 mA / V ² per 10 μm width, and good transistor characteristics were realized.

Fourth Embodiment A fourth embodiment of the present invention will be described with reference to the sectional view of FIG. This embodiment is also an application example to a field effect transistor. The manufacturing process is shown below.

The semi-insulating InP substrate 14 is formed by the MBE method.
An undoped InAlAs layer (In composition 0.53, thickness 300 nm) 15, p-type InAlAs layer (In composition 0.53, Be impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 300).
nm) 16, p-type InGaAs layer (In composition 0.53,
Be impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 50 nm) 4, n
Type InGaAs layer (In composition: 0.53, Si impurity concentration: 1 × 10 ¹⁹ / cm ³ , thickness: 5 nm) 5, And-type InAl
As layer (In composition 0.53, thickness 10 nm) 17, undoped InGaAs layer (In composition 0.53, thickness 35 n)
m) 18 are grown in sequence. The substrate temperature during growth was set to 480 to 540 ° C., carrier compensation, re-evaporation of In, and diffusion of impurities were suppressed.

Next, the semiconductor layer at the contact portion is etched by 50 to 150 nm from the surface by the ECR plasma etching method using SiCl ₄ gas, and then M
An n-type InGaAs layer (In composition 0.53, Si impurity concentration 1 × 10 ¹⁹ / cm ³ ,
Selectively grows (thickness 700 nm) 19. The substrate temperature during the selective growth was set to 540 ° C. to suppress the diffusion of impurities in the InGaAs channel layer 5.

The source electrode 9 of the AuGe / Ni / Au laminated film is formed on the n-type InGaAs layer 19 by the lift-off method.
The drain electrode 10 is formed and alloying treatment is performed at 400 degrees.

By an optical dry etching method using CH ₃ Br gas, undoped InGaA in the gate electrode forming portion is formed.
The s layer 18 is removed by etching, and then the gate electrode 11 of the Ti / Pt / Au laminated film is formed by the lift-off method.

In the field effect transistor manufactured in the above process, p-type InGa is formed on the substrate side of the n-type InGaAs layer 5.
Due to the effect of inserting the As layer 4, the n-type InGaAs layer 5
And the contact resistance of the n-type InGaAs layer 19 could be reduced to 6Ω per 10 μm width. As a result, the source resistance has a width of 10
It was possible to reduce to 21Ω per μm.

Fifth Embodiment A fifth embodiment of the present invention will be described with reference to the sectional view of FIG. This embodiment is an application example to a bipolar transistor. The manufacturing process is shown below.

Semi-insulating GaAs substrate 1 by MBE method
An n-type GaAs layer (thickness 600 nm, Si impurity concentration 5 × 10 ¹⁸ / cm ³ ) 20, an and-up GaAs layer (thickness 400 nm) 21, and an and-in InGaAs layer (In
Composition ratio 0.2, thickness 15 nm) 22, p-type InGaAs
Layer (In composition ratio 0.2, Be impurity concentration 6 × 10 ¹⁹ / c
m ³ , thickness 5 nm) 23, n-type AlGaAs layer (Al composition ratio 0.3, Si impurity concentration 1 × 10 ¹⁸ / cm ³ , thickness 100 nm) 24, n-type GaAs layer (Si impurity concentration 5)
25 × 10 ¹⁸ / cm ³ and a thickness of 200 nm) are sequentially laminated. The substrate temperature during growth is set to 480 to 540 degrees, and I
The re-evaporation of n and the diffusion of impurities were suppressed.

The semiconductor layer other than the emitter portion is etched by 250 nm from the surface by the wet etching method.
Next, the semiconductor layer of the base contact portion is 100 nm thick by ECR plasma etching using SiCl ₄ gas.
After etching, a p-type GaAs layer (Zn impurity concentration 1 × 10 ^{20 is formed on the} base contact portion by MOCVD.
/ Cm ³ , thickness 250 nm) 26 is selectively grown. The substrate temperature during the selective growth was set to 540 ° C. to suppress the diffusion of impurities in the InGaAs base layer 23. Next, the semiconductor layer of the collector electrode forming portion is
nm etching.

By the lift-off method, AuGe / Ni / A
A collector electrode 27 and an emitter electrode 29 of a u laminated film are formed and alloyed at 400 degrees. Similarly, the lift-off method is used to form the base electrode of the AuZn / Au laminated film,
Alloying treatment is performed at 00 degrees.

In the bipolar transistor manufactured through the above steps, the p-type InGaAs layer 22 is inserted on the substrate side of the p-type InGaAs layer 23, so that the p-type InGaAs layer 22 is inserted.
The contact resistance between the GaAs layer 23 and the p-type GaAs layer 26 can be made sufficiently low. Therefore, as shown in this embodiment,
It was possible to use InGaAs having a high electron traveling speed for the base layer and to reduce the thickness of the base layer to 5 nm.
As a result, the base running time is shortened and the cutoff frequency is 6
It improved to 0 GHz.

Sixth Embodiment A sixth embodiment of the present invention will be described with reference to the sectional view of FIG. In this embodiment, HEMT (high elect)
It is an application example to a ron mobility transistor). The manufacturing process is shown below.

Semi-insulating GaAs substrate 1 by MBE method
An undoped GaAs layer (thickness 600 nm) 2 and an undoped InGaAs layer (In composition 0.2, thickness 20 n)
m) 30, n-type AlGaAs layer (Al composition 0.2, Si
An impurity concentration of 1 × 10 ¹⁸ / cm ³ and a thickness of 25 nm 31 and an undoped GaAs layer (thickness 35 nm) 7 are sequentially grown.
The substrate temperature during growth was set to 480 to 540 ° C., carrier compensation, re-evaporation of In, and diffusion of impurities were suppressed.

Next, the semiconductor layer at the contact portion is etched by 60 to 160 nm from the surface by the ECR plasma etching method using SiCl ₄ gas, and then M
The n-type GaAs layer (S
An impurity concentration of 1 × 10 ¹⁹ / cm ³ and a thickness of 700 nm) 8 is selectively grown.

Then, n-type GaAs is formed by the lift-off method.
On the layer 8, a source electrode 9 of a AuGe / Ni / Au laminated film,
The drain electrode 10 is formed and alloying treatment is performed at 400 degrees. The undoped GaAs 7 in the gate electrode forming portion is removed by etching by the reactive ion etching method using CCl ₂ F ₂ gas, and then Ti / Ti is removed by the lift-off method.
A gate electrode 11 of a Pt / Au laminated film is formed.

In the field effect transistor manufactured by the above process, the undoped InGaAs layer 30 has a channel layer 32 in the vicinity of the interface with the n-type AlGaAs layer 31 in which a two-dimensional electron gas is generated, and the other portions wrap around carriers. It functions as the path forming layer 33. Therefore, the contact resistance between the channel layer 32 and the n-type GaAs layer 8 can be substantially reduced by sufficiently increasing the thickness of the undoped InGaAs layer 30 and ensuring the route around the carriers.

In this embodiment, the thickness of the undoped InGaAs layers 30 and 31 is set to 20 nm which is almost equal to the critical thickness.
The channel layer 31 and the n-type GaA
The contact resistance of the s layer 8 could be reduced to 10Ω per 10 μm width. As a result, the source resistance is 25Ω per 10 μm width
Therefore, the value of the transconductance coefficient K is 10 μm.
Good transistor characteristics with large transconductance of 10 mA / V ² per m were achieved.

Seventh Embodiment A seventh embodiment of the present invention will be described with reference to the sectional view of FIG. The present embodiment is an application example to the field effect transistor without the AND-type AlGaAs layer 6 on the channel layer 5 in the first embodiment. The manufacturing method is shown below.

Semi-insulating GaAs substrate 1 by MBE method
An undoped GaAs layer (thickness 300 nm) 2, p-type GaAs layer (Be impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 30)
0 nm) 3, p-type InGaAs layer (In composition 0.2, B
e Impurity concentration 3 × 10 ¹⁶ / cm ³ , thickness 15 nm 4 4, n-type InGaAs layer (In composition 0.2, Si impurity concentration 1 ×)
10 ¹⁹ / cm ³ , thickness 5 nm) 5, and undoped GaAs layer (thickness 45 nm) 7 are sequentially grown. The substrate temperature during growth was set to 480 to 540 ° C., carrier compensation, re-evaporation of In, and diffusion of impurities were suppressed.

Then, the semiconductor layer at the contact portion is etched by 50 to 150 nm from the surface by the ECR plasma etching method using SiCl ₄ gas, and then M
The n-type GaAs layer (S
An impurity concentration of 1 × 10 ¹⁹ / cm ³ and a thickness of 700 nm) 8 is selectively grown. The substrate temperature during the selective growth was 540 ° C., and I
The diffusion of impurities in the nGaAs channel layer was suppressed.

Then, n-type GaAs is formed by the lift-off method.
On the layer 8, a source electrode 9 of a AuGe / Ni / Au laminated film,
The drain electrode 10 is formed and alloying treatment is performed at 400 degrees. The undoped GaAs 7 in the gate electrode forming portion is removed by 35 nm by etching with an aqueous solution of H ₃ PO ₄ and H ₂ O ₂ , and subsequently, the gate electrode 11 of a Ti / Pt / Au laminated film is formed by the lift-off method.

In the case of the present embodiment, A in which interface states are often generated
Since it does not have the lGaAs layer, the effect of inhibiting the carrier conduction is small as compared with the other embodiments having this layer. However, by providing the carrier sneak path forming layer, the cross-sectional area of the carrier conduction path increases, and as a result, the contact resistance between the n-type InGaAs layer 5 and the n-type GaAs layer 8 can be reduced. In this embodiment, the contact resistance is set to 1
It was possible to reduce to 10Ω per 0 μm. As a result, since the source resistance was as small as 25Ω per 10 μm width, the value of the mutual conductance coefficient K was as large as 14 mA / V ² per 10 μm width, and good transistor characteristics with large mutual conductance could be realized.

[0060]

According to the present invention, by inserting a graded layer having a changed composition into the substrate side of the channel layer or the base layer, a contact portion having a small contact resistance between the channel layer or the base layer and the contact layer is formed. realizable. As a result, a heterojunction field effect transistor having a small source resistance or a heterojunction bipolar transistor having a base layer having a small base resistance can be realized, and the transistor performance can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of an example of a conventional field effect transistor.

FIG. 3A is a diagram for explaining a cause of an increase in contact resistance in a field effect transistor, and is a cross-sectional view of a contact portion in the case of a GaAs channel layer. (B) is a diagram for explaining the cause of increase in contact resistance in a field effect transistor, and is a cross-sectional view of a contact portion in the case of an InGaAs channel layer.

FIG. 4 is a band structure diagram of the field effect transistor of Example 1 of the present invention.

FIG. 5 is a sectional view of a field effect transistor of Example 2 of the present invention.

FIG. 6 is a cross-sectional view of a field effect transistor of Example 3 of the present invention.

FIG. 7 is a sectional view of a field effect transistor of Example 4 of the present invention.

FIG. 8 is a sectional view of a bipolar transistor of Example 5 of the present invention.

FIG. 9 is a sectional view of a field effect transistor of Example 6 of the present invention.

FIG. 10 is a sectional view of a field effect transistor of Example 7 of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs,
3 ... p-type GaAs, 4 ... p-type InGaAs, 5 ... n-type I
nGaAs, 6 ... Undoped AlGaAs, 7 ... Undoped GaAs, 8 ... N-type GaAs, 9 ... Source electrode, 1
0 ... Drain electrode, 11 ... Gate electrode, 13 ... N-type In
GaAs, 14 ... Semi-insulating InP substrate, 15 ... Undoped InAlAs, 16 ... P-type InAlAs, 17 ... Undoped InAlAs, 18 ... Undoped InGaAs,
19 ... n-type InGaAs, 20 ... n-type GaAs, 21 ...
Undoped GaAs, 22 ... Undoped InGaAs,
23 ... p-type InGaAs, 24 ... n-type AlGaAs, 2
5 ... n-type GaAs, 26 ... p-type GaAs, 27 ... collector electrode, 28 ... base electrode, 29 ... emitter electrode, 30
... undoped InGaAs, 31 ... n-type AlGaAs,
32 ... Channel layer, 33 ... Carrier sneaking path formation layer, 105 ... N-type GaAs, 201 ... Interface state, 202
... Depletion layer, 203 ... Carrier sneak path 204 ... In
GaAs / GaAs heterojunction surface, 205 ... conduction band, 2
06 ... Forbidden band, 207 ... Fermi level, 208 ... Valence band.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication H01L 21/331 29/73 (72) Inventor Yasunari Umemoto 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Yoko Uchida 1-280 Higashi Koigokubo, Kokubunji, Tokyo Hitachi Central Research Laboratory Ltd. (72) Inventor Takeyuki Hiruma 1-280 Higashi Koikeku, Kokubunji, Tokyo Hitachi Central In the laboratory

Claims (31)

[Claims] 1. An n-type conductivity type first semiconductor layer and a second semiconductor layer formed in contact with one surface of the first semiconductor layer and containing no impurities or p-type impurities. A third semiconductor layer formed on the side opposite to the first semiconductor layer with respect to the second semiconductor layer, to which no impurities are added or p-type impurities are added, and the first semiconductor layer. Has a fourth semiconductor layer of n-type conductivity type formed as a separate body, the first semiconductor layer and the second semiconductor layer have the same electron affinity, and the third semiconductor layer is the second semiconductor layer. A semiconductor device having an electron affinity smaller than that of a semiconductor layer, and the first or second semiconductor layer and the fourth semiconductor layer are in direct contact with each other. 2. The semiconductor device is further formed on the opposite side of the first semiconductor layer from the second semiconductor layer,
The semiconductor device according to claim 1, further comprising a fifth semiconductor layer containing no impurities or a p-type impurity. 3. A first semiconductor layer of p-type conductivity type and a second semiconductor layer formed in contact with one surface of the first semiconductor layer and containing no impurities or n-type impurities. A third semiconductor layer formed on the side opposite to the first semiconductor layer with respect to the second semiconductor layer, to which no impurity is added or an n-type impurity is added, and the first semiconductor layer. Has a p-type conductivity type fourth semiconductor layer formed as a separate body, and the first semiconductor layer and the second semiconductor layer have the same electron affinity and the same bandgap, and the third semiconductor layer has the same structure. A semiconductor device, wherein the layer has a smaller sum of electron affinity and band gap than the second semiconductor layer, and the first or second semiconductor layer and the fourth semiconductor layer are in direct contact with each other. 4. The semiconductor device is further formed on the opposite side of the first semiconductor layer from the second semiconductor layer,
The semiconductor device according to claim 3, further comprising a fifth semiconductor layer to which no impurities are added or an n-type impurity is added. 5. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is formed in contact with the first semiconductor layer and the second semiconductor layer. 6. The semiconductor device according to claim 2, wherein the fourth semiconductor layer is formed in contact with the first semiconductor layer and the second semiconductor layer. 7. The semiconductor device according to claim 3, wherein the fourth semiconductor layer is formed in contact with the first semiconductor layer and the second semiconductor layer. 8. The semiconductor device according to claim 4, wherein the fourth semiconductor layer is formed in contact with the first semiconductor layer and the second semiconductor layer. 9. The first semiconductor layer comprises InGaAs, the second semiconductor layer comprises InGaAs, the third semiconductor layer comprises GaAs, and the sum of the thicknesses of the first and second semiconductor layers is The semiconductor device according to claim 5, wherein the thickness is not more than the critical thickness of InGaAs. 10. The first semiconductor layer comprises InGaAs, the second semiconductor layer comprises InGaAs, the third semiconductor layer comprises GaAs, and the sum of the thicknesses of the first and second semiconductor layers is 8. The critical thickness of InGaAs or less
The semiconductor device described. 11. The first semiconductor layer is InGaAs, the second semiconductor layer is InGaAs, the third semiconductor layer is GaAs, the fifth semiconductor layer is AlGaAs, and the first and second semiconductor layers are made of InGaAs. The sum of the thicknesses of the semiconductor layers is InG
7. The semiconductor device according to claim 6, wherein the thickness is equal to or less than the critical film thickness of aAs. 12. The first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InGaAs, the third semiconductor layer is made of GaAs, the fifth semiconductor layer is made of AlGaAs, and the first and second semiconductor layers are made of InGaAs. The sum of the thicknesses of the semiconductor layers is InG
9. The semiconductor device according to claim 8, wherein the critical thickness is aAs or less. 13. The first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InGaAs, the third semiconductor layer is made of AlGaAs, the fifth semiconductor layer is made of GaAs, and the first and second semiconductor layers are formed. InG is the sum of the thicknesses of the semiconductor layers of
7. The semiconductor device according to claim 6, wherein the thickness is equal to or less than the critical film thickness of aAs. 14. The first semiconductor layer is InGaAs, the second semiconductor layer is InGaAs, the third semiconductor layer is AlGaAs, the fifth semiconductor layer is GaAs, and the first and second semiconductor layers are made of GaAs. InG is the sum of the thicknesses of the semiconductor layers of
9. The semiconductor device according to claim 8, wherein the critical thickness is aAs or less. 15. The first semiconductor layer comprises InGaAs, the second semiconductor layer comprises InGaAs, the third semiconductor layer comprises InAlAs, and the composition of each of these layers is In.
The semiconductor device according to claim 5, which is selected so as to be lattice-matched to the P substrate. 16. The first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InGaAs, the third semiconductor layer is made of InAlAs, and the composition of each of these layers is In.
The semiconductor device according to claim 7, which is selected so as to be lattice-matched to the P substrate. 17. The first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InGaAs, the third semiconductor layer is made of InAlAs, the fifth semiconductor layer is made of InAlAs, and the composition of each of these layers is InP. 7. The semiconductor device according to claim 6, which is selected so as to be lattice-matched to the substrate. 18. The first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InGaAs, the third semiconductor layer is made of InAlAs, the fifth semiconductor layer is made of InAlAs, and the composition of each of these layers is InP. 9. The semiconductor device according to claim 8, which is selected so as to be lattice-matched to the substrate. 19. The semiconductor device according to claim 17, wherein the first semiconductor layer is a channel layer of a field effect transistor, the fourth semiconductor layer is a source / drain contact layer, and is made of InGaAs. 20. The semiconductor device according to claim 18, wherein the first semiconductor layer is a channel layer of a field effect transistor, the fourth semiconductor layer is a source / drain contact layer, and is made of InGaAs. 21. The first semiconductor layer is a channel layer of a field effect transistor, the fourth semiconductor layer is a source / drain contact layer, and the first and second semiconductor layers of the fourth semiconductor layer. In contact with the semiconductor layer is In
The semiconductor device according to claim 5, wherein the semiconductor device is made of GaAs, and a GaAs layer is laminated on the InGaAs layer. 22. The first semiconductor layer is a channel layer of a field effect transistor, the fourth semiconductor layer is a source / drain contact layer, and the first and second layers of the fourth semiconductor layer. In contact with the semiconductor layer is In
8. The semiconductor device according to claim 7, which is made of GaAs and has a GaAs layer laminated on the InGaAs layer. 23. At a contact portion between the first semiconductor layer and the fourth semiconductor layer, a part of the surface of the fourth semiconductor layer is formed in substantially the same plane as one surface of the first semiconductor layer. The semiconductor device according to claim 6. 24. At a contact portion between the first semiconductor layer and the fourth semiconductor layer, a part of the surface of the fourth semiconductor layer is formed in substantially the same plane as one surface of the first semiconductor layer. The semiconductor device according to claim 8. 25. The semiconductor device according to claim 6, wherein the first semiconductor layer is a base layer of a bipolar transistor, and the fourth semiconductor layer is a base contact layer. 26. The semiconductor device according to claim 8, wherein the first semiconductor layer is a base layer of a bipolar transistor, and the fourth semiconductor layer is a base contact layer. 27. A first InGaAs layer of n-type conductivity;
Formed in contact with one surface of the first InGaAs layer,
The semiconductor device has an n-type conductivity type semiconductor layer formed as a separate body from the second InGaAs layer to which no impurity is added or a p-type impurity is added, and the first InGaAs layer. The type semiconductor layer is formed of the first and second InGa.
A semiconductor device, which is formed in contact with an As layer. 28. A first InGaAs layer of p-type conductivity,
Formed in contact with one surface of the first InGaAs layer,
The semiconductor device has a p-type conductivity type semiconductor layer formed as a separate body from the second InGaAs layer to which no impurities are added or an n-type impurity is added, and the first InGaAs layer, and the separate p-type conductivity type. Type semiconductor layer is formed of the first and second InG
A semiconductor device, which is formed in contact with an aAs layer. 29. A method of manufacturing a semiconductor device according to claim 1 or 3, wherein a step of stacking the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer on a substrate in this order. And a step of etching away the first and second semiconductor layers in a region where the fourth semiconductor layer is formed, and a step of forming the fourth semiconductor layer in the etching removed portion by selective growth. A method of manufacturing a semiconductor device, comprising: 30. The method of manufacturing a semiconductor device according to claim 2, wherein the third semiconductor layer, the second semiconductor layer, the first semiconductor layer, and the fifth semiconductor layer are formed on a substrate. In this order, a step of etching away the fifth, first and second semiconductor layers in the region where the fourth semiconductor layer is formed, and a step of removing the fourth semiconductor layer in the etching removed portion. And a step of forming by selective growth. 31. The method of manufacturing a semiconductor device according to claim 2 or 4, wherein the fifth semiconductor layer, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed on a substrate. In this order, a step of etching away the third, second and first semiconductor layers in a region where the fourth semiconductor layer is formed, and a step of removing the fourth semiconductor layer in the etching removed portion. And a step of forming by selective growth.