JPH05227003A - Output circuit device - Google Patents

Abstract

PURPOSE:To suppress the generation of overshooting and undershooting due to overcurrents by inputting respective signal waveforms with a moderate change and a sharp change to individual MOSFETs. CONSTITUTION:When an input is change from 'H' to 'L', an FET Mp1 in the 1st control circuit COT1 is turned on and the potential of a point A is 5 raised almost simultaneously with the trailing time of an input waveform. In the 2nd control circuit COT2, FETs Mp2, Mp3 are also turned on and the potential of a point B is moderately raised as compared with the point A. Thereby the undershooting phenomenon of an output waveform is reduced. When the input is turned from 'L' to 'H', the potential of the point B falls almost simultaneously with the leading time of the input waveform and the potential of the point A falls slowly falls in comparison with the point A. Thereby the overshooting phenomenon of the output waveform can be suppressed without allowing a sharp transient current to flow into a transistor(TR) Mp4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit device for a semiconductor integrated circuit, and more particularly to an output circuit device for suppressing undershoot and overshoot of output voltage.

[0002]

2. Description of the Related Art A conventional output circuit device will be described by taking a CMOS output buffer as an example. FIG. 4A shows the output wiring and VDD.
It is described in consideration of the inductive load component (inductance component) of the wiring and the GND wiring. P-channel MOS transistor Mp6 and N-channel MOS transistor Mn6
The output inverter configured by the above becomes a CMOS output buffer by being driven by the pre-invert buffer. P
The source of the channel MOS transistor Mp6 is VDD
To the VDD via the inductance L1 parasitic in the wiring,
The source of the N-channel MOS transistor Mn6 is GN
GND via the inductance L2 parasitic on the D wiring
The drains of the transistors Mp6 and Mn6 are connected to the external load capacitance C via the inductance L3 parasitic on the output wiring.
It is connected to the. The output of the pre-invert buffer B is input to the gates of the transistors Mp6 and Mn6.
When a “low” level (GND level) signal is input to this gate, the transistor Mp6 becomes conductive (“ON” state), the transistor Mn6 becomes non-conductive (“OFF” state), and VDD The external load capacitance C is “high” through the transistor Mp6 in the “ON” state.
Charged to the level (VDD level), and the output terminal is VDD
Become a level. When a VDD level signal is input, the transistor Mp6 is in the “OFF” state, the transistor Mn6 is in the “ON” state, and the charges accumulated in the external load capacitance C flow into the GND via the transistor Mn6 and output. The terminal becomes GND level.

[0003]

In order to invert the output signal at high speed in this conventional CMOS output buffer,
It is necessary to increase the channel width of the transistors Mn6 and Mp6 to enhance the current capability of the transistors. At this time, as described above, there is a parasitic inductance between VDD and GND and the load capacitance, and these are parasitic transistors Mp.
6 and Mn6 are connected in series when they are "ON",
An LC resonance circuit will be formed. When the waveform input to FIG. 4A changes from the VDD level to the GND level, the transistor Mn6 is in the "ON" state, the charge accumulated in the load capacitance rapidly flows into the GND, and the output level is the VDD level. Changes to the GND level. At this time, a transient current flows near the output reaching the GND level and an undershoot phenomenon occurs.

Further, even when the load capacitance is rapidly charged from VDD through the transistor Mp6 in the "ON" state, a transient current flows near the output reaching the VDD level and an overshoot phenomenon occurs. Figure 4 shows these situations.
It shows in (b). This phenomenon has a problem that the output circuit transmits an incorrect logic level.

Further, in a semiconductor device having a large number of output circuits such as a gate array, when a large number of output buffers operate at the same time, the VDD and GND levels of the semiconductor device itself change due to the effects of undershoot and overshoot, There is also a problem of causing a malfunction of the semiconductor device.

In order to suppress the undershoot and overshoot, the change in the signal waveform input to the output transistor may be made gentle. That is, if the rise time and fall time of the input waveform are lengthened, the large current that flows instantaneously decreases, and undershoot and overshoot also decrease. However, in this case, the time in which the output transistors Mn6 and Mp6 are simultaneously turned “ON” becomes long, the through current between VDD and GND increases, and the CMOS
A new problem arises in that the advantage of low current consumption, which is the characteristic of the above, is lost.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel output circuit device capable of solving the above-mentioned problems inherent in the prior art. To do.

[0008]

In order to achieve the above object, an output circuit device according to the present invention includes a CMOS inverter circuit which inverts and outputs a signal, and a gate of a P-channel transistor of the inverter circuit. It is configured to include a first control circuit connected thereto and a second control circuit connected to the gate of the N-channel transistor of the inverter circuit.

Each of the first and second control circuits has a P-channel transistor or an N-channel transistor of the same size in order to make the rise time faster (or slower) and the fall time slower (or faster). It is used by increasing the “on” resistance by connecting multiple units in series.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be specifically described with reference to the drawings for each of its preferred embodiments.

FIG. 1 is a circuit configuration diagram showing a first embodiment of a CMOS output buffer circuit according to the present invention.

Referring to FIG. 1, a P channel MOS transistor Mp4 and an N channel MOS transistor Mn4.
To form an output inversion buffer (hereinafter, P-channel MOS transistor is represented by a transistor Mp, and N-channel MOS transistor is represented by a transistor Mn). The source of the transistor Mp4 is VDD, the source of the transistor Mn4 is GND, and the transistor Mp4 is
And the drains of the transistors Mn4 are commonly connected to the output. Waveforms controlled by the first control circuit COT1 and the second control circuit COT2 are input to the gate of the transistor Mp4 and the gate of the transistor Mn4, respectively.

The first control circuit COT1 is constructed as follows. The transistors Mn1 and Mn3 are connected in series, the source of the transistor Mn1 is connected to GND, the drain of the transistor Mn3 is connected to the drain of the transistor Mp1, and the output of the first control circuit COT1 is obtained. The source of the transistor MP1 is connected to VDD. Also transistor M
The gates of n1, Mn3 and Mp1 are all common and connected to the input of the circuit of FIG.

The second control circuit COT2 is constructed as follows. The transistor Mp2 and the transistor Mp3 are connected in series, the source of the transistor Mp2 is connected to VDD, the drain of the transistor Mp3 is connected to the drain of the transistor Mn2, and it becomes the output of the second control circuit COT2. The source of the transistor Mn2 is connected to GND. Also transistor M
The gates of p2, Mp3, and Mn2 are all common, and C in FIG.
It is connected to the input of the MOS output buffer.

Next, the case where the input signal shown in FIG. 2 is applied to the CMOS output buffer having the above-described structure will be described.

Referring to FIGS. 1 and 2, the input is "high".
When the level (“H” level) changes to “low” level (“L” level), the first control circuit C
The transistor Mp1 of the OT1 is turned "ON", and the potential at the point A in FIG. 1 rises in a time almost equal to the fall time of the input waveform. Also, the transistors Mp2 and Mp3 of the second control circuit COT2 are also turned "ON".
Since the two transistors are connected in series, the “ON” resistance is higher than that of the transistor Mp1, and the potential at the point B rises more slowly than at the point A. Therefore, the fast rising waveform of the first control circuit COT1 is input to the transistor Mp4, and the transistor Mp4
4 turns "OFF" rapidly. In addition, the waveform of the second control circuit COT2 having a gentle rising edge has a transistor M
It is input to n4 and the transistor Mn4 slowly turns to "O".
Therefore, a steep transient current does not flow in the transistor Mn4, so that the undershoot phenomenon of the output waveform is reduced.

Next, when the input changes from the "L" level to the "H" level, the second control circuit COT2
The transistor Mn2 of is turned "ON", and the potential at the point B falls at a time almost the same as the rise time of the input waveform. In addition, the transistor Mn of the first control circuit COT1
Similarly, 3 and Mn1 also turn on, but since these two transistors are connected in series, the transistor M
The “ON” resistance is higher than that of n2, and the potential at point A falls gently compared to point B. Therefore, the transistor Mn4 to which a waveform with a fast falling edge is input is rapidly turned "OFF", while the transistor Mp4 to which a waveform with a gentle falling edge is input is slowly turned "ON". No current flows,
The output waveform overshoot phenomenon is suppressed. The state of the above signal waveforms is shown in FIG.

Further, when either of the transistors Mp4 and Mn4 is turned "ON", the timing is different from that of the transistor turned "OFF".
4 and Mn4 are “ON” at the same time as when the control circuit of FIG.
A low noise CMOS output buffer in which overshoot and undershoot are suppressed can be obtained without increasing the through current between NDs.

FIG. 3 is a circuit configuration diagram showing a second embodiment according to the present invention.

When a large-scale LSI having a large number of outputs (eg, a gate array) is tested by an LSI tester, a large number of output buffers change at the same time, so that V of the device under test is changed.
There are cases where the DD and GND levels change and malfunction occurs. This is due to overshoot and undershoot phenomena that occur due to the effect of inductance parasitic on the wiring on the LSI tester. Although the present invention can address the above-mentioned problems, the transistors Mn3 and Mp3 of FIG.
Although the noise generation (overshoot, undershoot) can be suppressed by setting the resistance of the higher, the problem that the transmission delay time of the output buffer becomes longer occurs.

Therefore, as shown in FIG. 3, in the second embodiment of the present invention, the transistors Mn3 and Mn are tested during the test.
Only p3 is effective, and the transistors Mn5 and Mp5 are connected to the transistor M during normal use (when mounted in a device or the like).
This is an example in which the "ON" resistance is lowered by connecting in parallel with n3 and Mp3 to improve the transmission delay time. The switching of the test mode is effective by setting the test control terminal of FIG. 3 to the “H” level, and is normally used by setting it to the “L” level.

[0022]

As described above, according to the present invention,
The signal waveforms input to the output transistors of the CMOS output buffer are P-channel MOS transistors and N-channel MOS transistors separately. The signal waveform with a gentle change is input to the transistor that turns on and the transistor that turns off has a steep slope. By inputting a signal waveform having various changes, it is possible to obtain the effect of suppressing the occurrence of overshoot and undershoot due to the transient current flowing in the transistor that is rapidly turned “ON”.

In addition, according to the present invention, the time when both P and N transistors are turned on at the same time can be shortened, so that a low noise output buffer can be obtained without increasing the through current between VDD and GND. The effect of being able to be obtained is also obtained.

Further, according to the present invention, since a transistor having a large "ON" resistance is formed by connecting a plurality of transistors in series, it can be applied to a case where the transistor size such as a gate array is predetermined. Since it is not necessary to provide a special delay circuit, a relatively small size can be achieved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is a diagram showing input / output to and from the circuit shown in FIG. 1 and signal waveforms at points A and B in FIG.

FIG. 3 is a circuit configuration diagram showing a second embodiment according to the present invention.

4A is a circuit diagram of a conventional example, and FIG. 4B is an input / output signal waveform diagram for the circuit shown in FIG.

[Explanation of symbols]

 Mn1 to Mn6 ... N channel MOS transistors Mp1 to Mp6 ... P channel MOS transistors COT1 ... First control circuit COT2 ... Second control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (3)

[Claims] 1. A CMOS inverter circuit that inverts and outputs a signal, and a first control circuit connected to a gate of a P-channel transistor of the inverter circuit,
A second control circuit connected to the gate of an N-channel transistor of the inverter circuit, wherein the inputs of the first control circuit and the second control circuit have the same signal waveform. apparatus. 2. The first control circuit comprises one P
A channel transistor and two or more Ns connected in series
A channel transistor, the P channel, N
The output circuit device according to claim 1, wherein inputs of the channel transistors are common. 3. The second control circuit comprises one N
A channel transistor and two or more Ps connected in series
A channel transistor, the P channel, N
The output circuit device according to claim 1, wherein inputs of the channel transistors are common.