JPH0522979Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field The present invention relates to a limiter amplifier integrated with an IC (integrated circuit) used in the signal amplification system of television receivers, etc. The present invention relates to a limiter amplifier configured by connecting dynamic amplification circuits in multiple stages. (b) Conventional technology In order to obtain a high gain limiter amplifier, it is necessary to have good DC balance. As a method of achieving the DC balance, a method is known in which a capacitor for removing the AC component is placed in the feedback signal path from the output stage to the input stage of the limiter amplifier to provide negative DC feedback. However, since a limiter amplifier consisting of a differential amplifier circuit connected in multiple stages has a large gain, the alternating current component in the feedback signal is not sufficiently attenuated, which affects the input signal. Furthermore, since multiple stages of differential amplifier circuits are continuously connected, phase rotation becomes large. As a result, oscillation may occur. In order to prevent oscillation, it is sufficient to make the capacitor large enough, but large capacitance capacitors are
There was a problem that it could not be built into the IC and the number of external parts increased. For example, there is a limiter amplifier disclosed in Japanese Utility Model Application Laid-Open No. 60-72018 as a solution to such problems. FIG. 2 is a circuit diagram showing the limiter amplifier, and the dash-dotted line indicates an IC. The input signal applied to the input terminal 1 is amplified by the differential amplifier circuits 2, 3 , 4 , 5 , and 6 , and the first and second output transistors 7 are connected as emitter follower.
and applied to the base of 8. Therefore, output signals are generated at output terminals 9 and 10 connected to the emitters of the first and second output transistors 7 and 8. Further, the output DC signal of the first output transistor 7 is fed back to the base of the transistor 12 constituting the feedback differential amplifier circuit 11 , and the output AC signal of the first output transistor 7 is fed back from the resistor 13 and the capacitor 14. Filter circuit 1 for removing alternating current consisting of
It is removed in 5. On the other hand, the output DC signal of the second output transistor 8 is fed back to the base of the transistor 16 constituting the differential amplifier circuit 11 , and the output AC signal of the second output transistor 8 is fed back to the base of the transistor 16 constituting the differential amplifier circuit 11. It is removed by a removal filter circuit. Further, the output DC signal of the second output transistor 8 is used for bias setting of the differential amplifier circuit 2 . The collectors of the transistors 12 and 16 are connected to the differential amplifier circuit 4.
Since the control signal corresponding to the difference between the feedback DC signals applied to the bases of the transistors 12 and 16 is connected to the bases of the differential pair transistors constituting the differential amplifier circuit 4 , It is applied to the base of the paired transistor, and a negative feedback operation is performed. As a result, the DC balance of the differential amplifier circuits 4 , 5 , and 6 can be maintained well.
Also, the loop gain of the feedback amplifier circuit consisting of the differential amplifier circuits 4 , 5 , and 6 and the feedback differential amplifier circuit 11 is the loop gain when DC negative feedback is applied to all stages of the multistage differential amplifier circuit. Since it is smaller than , the capacitance of the filter circuit capacitor can be reduced.
Can be built into the IC. Note that the capacitor 18 is also used as a decoupling capacitor that removes the AC component of the input signal, so its value is large and the IC
Since it cannot be built in, it is attached externally. (c) Problems to be solved by the invention However, although it is possible to stabilize the DC balance of the third and subsequent stages of differential amplifier circuits that are provided with negative feedback in the configuration shown in Figure 2, the negative feedback First stage and second stage differential amplifier circuit 2 without
There was a problem that the DC balance of 3 and 3 became unstable. (d) Means for solving the problems The present invention has been made in view of the above points, and includes a first multi-stage differential amplifier circuit that amplifies an input signal, and an output of the first multi-stage differential amplifier circuit. a first output transistor to which a signal is applied to the base; and an output signal obtained at the emitter of the first output transistor to the first output transistor;
a first feedback circuit that feeds back to the input end of the multistage differential amplifier circuit; a resistor whose one end is connected to the emitter of the first output transistor; and a second multistage differential amplifier whose input terminal is connected to the other end of the resistor. an amplifier circuit;
It has a second output transistor to which the output signal of the multistage differential amplifier circuit is applied to its base, and a second feedback circuit that feeds back the output DC signal of the second output transistor to the other end of the resistor. (E) Effect According to the present invention, a limiter amplifier consisting of differential amplifier circuits connected in multiple stages is divided into first and second multi-stage differential amplifier circuits, and each of the first and second multi-stage differential amplifier circuits Negative feedback is applied to the first and second multi-stage differential amplifier circuits, and an output transistor and a resistor provided between the multi-stage differential amplifier circuit prevent the influence of the feedback signal from the latter stage from being transmitted to the previous stage. The gain of each dynamic amplifier circuit can be lowered, and the DC balance of the entire limiter amplifier can be stabilized. (F) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention.
19 is an input terminal; 20 is a first differential amplifier circuit to which an input signal is applied from the input terminal 19; 21 is a transistor that determines the DC bias of the first differential amplifier circuit 20 ; and 22 and 23 are the first differential amplifiers. second and third circuits for further amplifying the output signal from the dynamic amplifier circuit 20;
Differential amplifier circuits 24 and 25 are emitter follower type first and second output transistors to which the output signal of the third differential amplifier circuit 23 is applied to their respective bases; 26 is a differentially connected first and second output transistor; 2 transistors 27 and 28 and a capacitor 29; a fourth differential amplifier circuit that negatively feeds back the emitter DC voltage of the first and second output transistors 24 and 25; 30 and 31 are the first and second output transistors; Fifth and sixth differential amplifier circuits 32 and 33 further amplify the output signals of 24 and 25; The output transistor 34 is a differentially connected third and fourth transistor 35 and 36 and a capacitor 37.
a seventh differential amplifier circuit that negatively feeds back the emitter DC voltage of the third and fourth output transistors 32 and 33; 38 and 39 are connected to the output terminals of the third and fourth output transistors 32 and 33; are the first and second output terminals. The second and third differential amplifier circuits 22 and 23 constitute a first multistage differential amplifier circuit, and the fifth and sixth differential amplifier circuits 30 and 31 constitute a second multistage differential amplifier circuit. do. Furthermore, the entire circuit is constructed on an IC board. Next, the operation shown in FIG. 1 will be explained. When an input signal is applied to the input terminal 19, the input signal is applied to the base of the transistor 40 of the first differential amplifier circuit 20, and an equal value is applied to the bases of the differential pair transistors 40 and 41 by the transistor 21. A DC bias is applied. For this reason,
The input signal is amplified by the first differential amplifier circuit 20 and then amplified by the second and third differential amplifier circuits 22 and 2.
3 and applied to the bases of the first and second output transistors 24 and 25. The first
The output signals from the emitters of the second output transistors 24 and 25 are applied to the fifth differential amplifier circuit 30 and the first output signal of the fourth differential amplifier circuit 26.
and is applied to the bases of second transistors 27 and 28 via resistors 42 and 43, respectively. 1st
The output signals having opposite phases applied to the bases of the second transistors 27 and 28 are removed by the capacitor 29, so that the DC voltage obtained at the emitters of the first and second output transistors 24 and 25 is reduced. only the first and second
The signal is fed back from the collectors of the transistors 27 and 28 to the bases of the differential pair of transistors constituting the second differential amplifier circuit 22 . As a result, the DC balance between the second and third differential amplifier circuits 22 and 23 is maintained well. At this time, since the loop gain of the first multistage amplifier circuit is relatively small, the output signals of the first and second output transistors 24 and 25 are smaller than the input signal, and the capacitance of the capacitor 29 can be small. Capacitor 29 can be built into the IC.
The second multi-stage differential amplifier circuit consisting of the fifth and sixth differential amplifier circuits 30 and 31 is subjected to negative feedback by the seventh differential amplifier circuit 34 , similarly to the first multi-stage differential amplifier circuit. Therefore, it performs the same operation as the first multistage differential amplifier circuit. Therefore, the limiter amplifier shown in FIG .
By amplifying with a multistage differential amplifier circuit, output signals limited to the first and second output terminals 38 and 39 can be obtained. In particular, at this time, the emitter impedance of each of the first and second output transistors 24 and 25 is low, and the effect of negative DC feedback from the seventh differential amplifier circuit 34 is exerted on the third differential amplifier circuit 23 in the previous stage. prevent this from happening. Further, if a direct current bias is applied to the first differential amplifier circuit 20 by the emitter follower type transistor 21, a decoupling capacitor that is conventionally required is no longer necessary. (g) Effects of the invention As described above, according to the invention, the influence of the feedback signal from the latter stage is not transmitted to the earlier stage, and the signal from the former stage can be efficiently transmitted to the latter stage, and the configuration is simple and stable. A multi-stage differential amplifier circuit can be connected. Further, according to the present invention, the number of stages in each of the first and second multi-stage differential amplifier circuits can be reduced, so the gain of each can be reduced and phase rotation can be minimized, and the capacitor in the feedback circuit can be reduced. It is possible to provide a high gain limiter amplifier that can prevent unnecessary oscillation even if the capacitance of is reduced. Further, according to the present invention, since the capacitor can be built into the IC, it is possible to provide a limiter amplifier suitable for use as an IC with a small number of pins and external parts.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional limiter amplifier. 19...input terminal, 20 , 22 , 23 , 26 ,
30, 31 , 34 ... Differential amplifier circuit, 24, 2
5, 32, 33...output transistor, 38, 3
9...Output terminal.

Claims (1)

[Scope of utility model registration request] a first multi-stage differential amplifier circuit that amplifies the input signal;
A first output transistor to which the output signal of the first multi-stage differential amplifier circuit is applied to the base, and an output signal obtained at the emitter of the first output transistor is fed back to the input terminal of the first multi-stage differential amplifier circuit. a first feedback circuit; a resistor having one end connected to the emitter of the first output transistor; a second multistage differential amplifier circuit having an input terminal connected to the other end of the resistor; and the second multistage differential amplifier. A limiter amplifier having a second output transistor to which an output signal of the circuit is applied to the base, and a second feedback circuit that feeds back the output DC signal of the second output transistor to the other end of the resistor.