JPH05257516A - Numerical controller - Google Patents

Abstract

PURPOSE:To protect a data input/output circuit by controlling the wrong access to the data input/output circuit due to the malfunction of a master. CONSTITUTION:Plural masters 1 and 2 are provided with master discrimination signal generating circuits 7a and 7b respectively. Further, a master discriminating circuit 8 which discriminates a master discrimination signal is provided. A decoder 5 generates a prescribed control signal based on the discrimination result and informs the master, which accesses the data input/output circuit 4, of whether the access is effective or not. An I/O 6 is controlled by the generated control signal, and the master which accesses it is informed of whether the access is effective or not, thus controlling the wrong access to the data input/output circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-bus master type numerical controller.

[0002]

2. Description of the Related Art Conventionally, a multi-bus master type numerical control device is known. As shown in FIG. 5, this numerical control device has a system bus 3 to which a plurality of masters 1, 2 ... Are connected and a data input / output circuit 4 is connected. There is. The data input / output circuit 4 includes a decoder 5 and an I / O 6.

Therefore, when the address of the data input / output circuit 4 connected to the system bus 3 is in the common area of the plurality of masters 1 and 2, the predetermined master 1 is determined.
It may be necessary to prohibit access from masters 2 other than. In such a case, the master 2 masks the area corresponding to the address of the data input / output circuit 4 as an access-prohibited area by software or circuit to prevent the occurrence of abnormal access, thereby preventing the data input / output circuit 4 from being accessed. Protects.

[0004]

In the conventional multi-bus master type numerical control device, when access is prohibited by software, if the master causes an abnormal operation due to a software defect, the access prohibited area will be erased. There is a problem that the data input / output circuit cannot be protected because there is no means for blocking access. In particular, in a numerical control device for machine tools, the data input / output circuit may directly control the operation of the machine, and it is necessary to reliably prevent the machine from malfunctioning due to software defects. Also, when access is prohibited in terms of circuitry, it is necessary to change the masking circuit each time a prohibited area is added or deleted, and it is not possible to easily add or delete functions. There was a problem.

The present invention has been made in order to solve the above problems, and an object of the present invention is to prevent unauthorized access to the data input / output circuit due to malfunction of the master, thereby controlling the data input / output circuit. It is to provide a numerical control device for protection.

[0006]

A numerical control apparatus according to the present invention identifies a master identification signal, which is provided in each of a plurality of masters connected to a bus and which generates a master identification signal. Master identification means, control signal generation means for generating a predetermined control signal based on the identification result of the master identification means, data input / output circuit controlled by the control signal, and whether access is effective based on the identification result of the master identification means. And a notifying means for notifying the master who has made an access.

[0007]

In the numerical controller according to the present invention, the master identification signal generated by the master identification signal generating means is identified by the master identification means. Further, based on the identification result of the master identification means, a predetermined control signal is generated by the control signal generation means to control the data input / output circuit, while the access master is informed whether the access is valid or not, and the data input / output is performed. The unauthorized access to the circuit is regulated and the data input / output circuit is protected from the malfunction of the master.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a numerical controller according to an embodiment of the present invention. As shown in FIG. 1, this numerical controller has a system bus 3, and a plurality of masters 1, 2, ... Are connected to the system bus 3. The masters 1, 2 are master identification signals, respectively. It has master identification signal generating circuits 7a and 7b for generating. A data input / output circuit 4 is connected to the system bus 3, and the data input / output circuit 4 generates a master identification circuit 8 for identifying a master identification signal and a predetermined control signal based on the identification result. A decoder 5 and an I / O (for example, a memory or a circuit operated by an I / O instruction) 6 for notifying the master 1 or 2 that has made access whether the access by the master 1 or 2 is valid are provided.
The master identification signal generating circuits 7a and 7b are realized as a circuit that changes the state of a preset master-specific signal line or a circuit that outputs a preset master-specific signal code. , Thereby generating a master identification signal unique to each master. Further, as shown in FIG. 2, the master identification circuit 8 decodes the identification signal line 9 connected to the system bus 3 and the data input from the identification signal line 9, and controls the access permission signal 102 according to the result. It is composed of a decoder 10.

Next, the operation of this embodiment will be described.
When the master 1 accesses the data input / output circuit 4, the master identification signal generation circuit 7 a outputs the master identification signal 101 together with the access signal 100. The master identification signal 101 output from the master identification signal generation circuit 7 a is input to the data input / output circuit 4 via the system bus 3 and interpreted by the master identification circuit 8 of the data input / output circuit 4. The master identification circuit 8 outputs the access permission signal 102 to the decoder 5 after confirming that the access is from the master 1. The decoder 5, which has received the access permission signal 102, outputs the I / O select signal 103 according to the content of the access signal 100 in addition to the decoding condition of the access permission signal 102, and the system bus 3 is normally accessed. A response signal 104 indicating that is output. Further, the master 1 detects that the access is normally performed by monitoring the response signal 104. On the other hand, the I / O 6 receiving the I / O select signal 103 operates according to the content of the signal. In this way, the access from the master 1 ends normally.

As shown in FIG. 3, when the master 2 accesses the data input / output circuit 4, the master identification signal generating circuit 7b outputs the master identification signal 201 together with the access signal 200. Master identification signal 201 output from master identification signal generation circuit 7b
Is input to the data input / output circuit 4 via the system bus 3 and interpreted by the master identification circuit 8 of the data input / output circuit 4. However, since the access is from the master 2 whose access is prohibited, the access permission signal 20
2 is not output, the decoder 5 that uses the access permission signal 202 as a decoding condition does not satisfy the decoding condition, and the I / O select signal 203 is not output.
This allows I / O for access from the master 2.
Protect 6 Further, at this time, the decoder 5 generates the response signal 204 indicating that the access is not normally performed and outputs it to the system bus 3. Then, by monitoring the response signal 204, the master 2 knows that the access is invalid. If the response signal is configured to be monitored by all masters, all masters can detect which master the abnormal operation has occurred in the response signal and the master identification signal. Therefore, it is possible to display an error based on this information.

In the above embodiment, the master identification circuit 8 is replaced with the identification signal line 9 connected to the system bus 3.
And the decoder 10 which decodes the data input from the identification signal line 9 and controls the access permission signal 102 according to the result, but is not limited to this, and corresponds to each master as shown in FIG. Signal lines 9a, 9
b, 9c and the signal line 9a, 9b, 9c may be used as a switch 11 for selecting which signal line to use as an access permission signal.

[0012]

As described above, according to the present invention,
Since the master identification signal is generated by the master identification signal generation means and the master identification means is used for identification, and the notification to the master that has controlled and accessed the data input / output circuit is executed, the data input / output circuit is illegal. Such access can be restricted to protect the data input / output circuit from the malfunction of the master. Further, since the validity / invalidity of access is determined on the data input / output side, even if a data input / output circuit having a new function is added, the function can be easily added without changing the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a numerical control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a master identification circuit according to the present embodiment.

FIG. 3 is a diagram for explaining the operation of the present embodiment.

FIG. 4 is a block diagram showing a configuration of a master identification circuit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional numerical control device.

[Explanation of symbols]

 1, 2 master 3 system bus 4 data input / output circuit 5 decoder 6 I / O 7a, 7b master identification signal generation circuit 8 master identification circuit 9 identification signal line

Claims (1)

[Claims] 1. A multi-bus master type numerical control device comprising: master identification signal generating means provided for each of a plurality of masters connected to a bus to generate a master identification signal; and master identification means for identifying the master identification signal. , A control signal generating means for generating a predetermined control signal based on the identification result of the master identifying means, a data input / output circuit controlled by the control signal, and whether or not the access is valid based on the identification result of the master identifying means A numerical control device comprising: a notifying unit for notifying the master who has performed.