JPH05258558A - Serial access memory - Google Patents

Abstract

(57) [Abstract] [Purpose] Improve the integration density of serial access memory,
It is easy to increase the capacity. [Structure] A plurality of memory blocks 1 each composed of a plurality of memory cells each composed of one transistor and one capacitor, and a write bit address pointer 2 and a write word address pointer 4 provided one by one for each memory block 1. A read bit address pointer 5 and a read word address pointer 7 are provided. The bit address pointers 2 and 5 of the same memory block share the same bit line, and the word address pointers 4 and 7 share the same word line. A difference is provided between the addresses for writing and reading by the number of addresses corresponding to one memory block or more, and the memory block for writing and the memory block for reading are always different. [Effect] A memory cell having one transistor and one capacitor can be used, and the degree of integration is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial access memory, and more particularly to a technique for improving the degree of integration and obtaining a large capacity serial access memory.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the structure of a conventional serial access memory. In the figure, 19 is a memory block composed of a plurality of memory cells having 3 transistors, 8 is a data input terminal, 9 is a data output terminal, and 10, 12, 13, and 15 are registers. The register 10 is connected in a loop to form a ring pointer. This ring pointer is the write bit address pointer 2. Reference numeral 11 is a switch that is controlled by the connected register 10 and switches whether to supply the 8-bit data input from the data input terminal 8 to the bit line 20. The register 12 is the first memory block 19
The memory cell is controlled through the word line 22 of. The register 12 is connected in a loop to form a ring pointer. This ring pointer is the write word address pointer 4. The register 13 is connected in a loop to form a ring pointer. This ring pointer is the read bit address pointer 5. 1
Reference numeral 4 is a sense amplifier connected to the second bit line 21 of the memory block 19 and controlled by the register 13 to read data. The register 15 controls the memory cell via the second word line 23 of the memory block 19. The register 15 is connected in a loop to form a ring pointer. This ring pointer is the read word address pointer 7.

Next, the operation of the serial access memory shown in FIG. 4 will be described. First, the data write operation will be described. One of the plurality of switches 11 is selected and turned on by the write bit address pointer 2 in which the register 10 is connected in a loop. And
The first bit line 2 connected to the turned-on switch 11
8-bit input data input from the input terminal 8 is supplied to 0. Further, one of the first word lines 22 is selected by one of the plurality of registers 12 by the write word address pointer 4 in which the registers 12 are connected in a loop. Then, the selected first word line 22 and bit line 2 in the memory block 19
Input data is written in the memory cell at the intersection of 0s. Next, the data for controlling the switch 11 of the register 10 is transferred to the next register 1 without moving the register 12 as it is.
One is moved to 0, the next bit line 20 is selected by the next switch 11, and the input data is written in the memory cell of this bit line 20. When this operation is repeated and the write bit address pointer 2 loops once, the data for selecting the bit line 22 of the register 12 is sequentially moved to the next register 12 by the signal of the register 10 at the end of the loop. The next first word line 23 is selected,
Data is written in the memory cell at the intersection of the first word line 23 and the bit line 20. Further, the above-described operation is repeated to move the first word line 22 in order, and when the loop of the write word address pointer 4 is looped once, the write processing ends.

Next, the read operation of the data stored in the memory cell is performed by selecting one of the plurality of sense amplifiers 14 by the read bit address pointer 5 which connects the register 13 in a loop. Also, one of the second word lines 23 is selected by one of the plurality of registers 15 by the read word address pointer 7 in which the registers 15 are connected in a loop. Then, the second word line 23 connected to the selected second word line 23 and the second word line 23 connected to the selected sense amplifier 14 are connected.
The data in the memory cell at the intersection with the bit line 21 is read out. Next, the register 15 is not moved and the data for controlling the sense amplifier 14 of the register 13 is moved to the next register 13 by one and the sense amplifier 14 connected to the next bit line 21 is selected. Bit line 21
The data in the memory cell is read out. When this operation is repeated and the read bit address pointer 5 loops once, the data of the register 15 is moved to the next register 15 by the signal of the register 13 at the end of the loop, and the next second word line is selected. , Its second word line 23
The data of the memory cell at the intersection of the bit line 21 and the bit line 21 is read. Then, by repeating the above operation, the next second
The word line 23 is selected. Further, when the loop of the read word address pointer 7 is cycled by repeating the above operation, the read processing ends.

Next, the memory cells forming the memory block 19 will be described with reference to FIG. In FIG. 5, 24 is an AND gate having one input end connected to the word line 22 connected to the write word address pointer 12,
40 is a signal line for transmitting the control signal of the write bit address pointer 10 to the other input end of the AND gate 24, 25 is a MOS transistor having one electrode connected to the bit line 20 and the output end of the AND gate 24 connected to the control electrode, 26
Has one electrode grounded and the control electrode is the MOS transistor 2
MOS transistor connected to the other electrode of 5, and 27 is M
One electrode is connected to the other electrode of the OS transistor 26,
A MOS transistor in which the control electrode is connected to the word line 23 and the other electrode is connected to the bit line 21, and one end of the MOS transistor 28 is M
A capacitor connected to the other electrode of the OS transistor 25 for storing data. In addition, 29 has shown the earthing | grounding of an element etc. Thus, one AND gate 24 is provided for one memory cell.

[0006]

Since the conventional serial access memory is constructed as described above, the bit line 20 and the word line 22 which perform the write operation and the bit line 21 and the word line 23 which perform the read operation are distinguished from each other. It is necessary to use two bit lines 20 and 21 and two word lines 22 for one memory cell by using three transistors in order to write and read data to and from one serial access memory at the same time. , 23 are required, which hinders the improvement of the degree of integration of the serial access memory and makes it difficult to increase the capacity of the serial access memory.

The present invention has been made to solve the above problems, and an object thereof is to obtain a large-capacity serial access memory by improving the integration degree of the serial access memory.

[0008]

A serial access memory according to the first invention comprises a plurality of memory cells each including one transistor and one capacitor, and a bit line and a word connected to each memory cell. A plurality of memory blocks having a plurality of lines; and a group of write bit address pointers, each of which is composed of a plurality of first registers connected in a loop and has a one-to-one correspondence with the memory block, connected in a loop. A read bit address pointer group having a plurality of read bit address pointers each having a one-to-one correspondence with the memory block, the read bit address pointer group having a plurality of second registers connected in a loop, and the word line of the corresponding memory block A plurality of third registers for controlling the memory cells via The same number of write word address pointers as the memory blocks, and the same number of read word address pointers as the memory blocks, the read word address pointers having a plurality of fourth registers for controlling the memory cells via the word lines of the corresponding memory blocks. , A plurality of selectors controlled by the corresponding write bit address pointers and supplying input data to the bit lines selected by the write bit address pointers, and the read bit address pointers controlled by the corresponding read bit address pointers A plurality of sense amplifiers for detecting the data output from the bit line selected by the pointer, and the write word address pointer and the address to which the write bit address pointer is writing, and the read word address pointer. Address-less pointer and the read bit address pointer is performing the read is characterized in that a separation of at least the number of addresses one portion of the memory block.

In the serial access memory according to the second aspect of the invention, in the first memory block of the plurality of memory blocks, the write bit address pointer corresponding to the first memory block is the first register. The write word address pointer corresponding to the first memory block sequentially selects the word lines to write data every time the loop is made, and the write word address pointer is changed to the third word block.
The data write process to the first memory block is completed when the loop constituted by the registers is completed, and the memory block other than the first memory block and the write bit address pointer and the write word address corresponding to the memory block In the second memory block of the plurality of memory blocks, the read bit address pointer corresponding to the second memory block is transferred at the same time as the write processing to the first memory block Each time one loop of the loop constituted by the second register is performed, the word line is sequentially selected by the read word address pointer corresponding to the second memory block to read data, and the read word address is further read. The pointer consists of the loop composed of the fourth register When the circuit is cycled, the reading process of the second memory block is terminated and the process is shifted to the process using the read bit address pointer and the read word address pointer corresponding to the memory block other than the second memory block, or , In a first memory block of the plurality of memory blocks, each time the write word address pointer corresponding to the first memory block goes through a loop constituted by the third register, the first memory block Data is written by sequentially selecting the bit lines by the write bit address pointer corresponding to the block, and further, when the write bit address pointer goes through the loop constituted by the first register, the first bit line The processing of the memory block is completed and the plurality of memory blocks are processed. Of the memory blocks other than the first memory block and the write bit address pointer and the write word address pointer corresponding to the memory block, and at the same time as the writing process to the first memory block In the second memory block of the blocks, every time the read word address pointer corresponding to the second memory block goes through the loop formed by the fourth register, the read bit corresponding to the second memory block Data is read by sequentially selecting the bit lines by the address pointer, and when the read bit address pointer completes a loop formed by the second register, the processing of the second memory block is completed. A second memory block of the plurality of memory blocks. The process is shifted to a process using a memory block other than the memory block, the read bit address pointer and the read word address pointer corresponding thereto.

Serial access memory according to the third invention
Is a first memory block of the plurality of memory blocks.
In the lock, before corresponding to the first memory block
The write bit address pointer is the first register.
Each time the loop composed of
By the write word address pointer corresponding to
Data is written by sequentially selecting the word lines,
Further, the write word address pointer is
The first memory when the loop composed of
The process of writing data to the block is completed and
Memory blocks other than the first memory block
Memory block and the write bit address corresponding to it
Address pointer and the write word address pointer.
Write to the first memory block.
At the same time as the first processing of the plurality of memory blocks.
The second memory block in the second memory block.
The read word address pointer corresponding to
The read is made every time the loop made up of 4 registers is cycled.
Select the bit lines sequentially by the bit address pointer
In addition, the read bit address pointer is
When the loop composed of registers is cycled, the second memory
Memory block processing is terminated and a plurality of memory blocks are
Memory blocks other than the second memory block
And the corresponding read bit address pointer
And the read word address pointer
Or of the plurality of memory blocks
In the first memory block of
The write word address pointer corresponding to the
Each time the loop made up of the third register is cycled,
The write bit address corresponding to one memory block
The bit lines are sequentially selected by a pointer,
The write bit address pointer consists of the register of 1 above.
The first memory block when the loop is completed
Of the plurality of memory blocks to complete the process
Corresponding to memory blocks other than 1 memory block
The write bit address pointer and the write
The process proceeds to the processing by the
Write to the memory block of
The second memory block of the memory blocks
The read bit corresponding to the second memory block.
Address pointer constructed by the second register.
Correspond to the second memory block every cycle
The word line by the read word address pointer
Are sequentially selected to read the data, and
The word address pointer is composed of the fourth register
Of the second memory block
When the reading process is completed and the plurality of memory blocks
And the memory blocks other than the second memory block.
The read bit address pointer corresponding to
Move to processing with read word address pointer
It is characterized by

A serial access memory according to a fourth aspect of the present invention is composed of a plurality of memory cells each including one transistor and one capacitor, and bit lines for transmitting signals to the memory cells and first and second words. A plurality of memory blocks having a plurality of lines; a write bit address pointer composed of a plurality of first registers connected in a loop; a read bit address pointer composed of a plurality of second registers connected in a loop; A write word address pointer having a plurality of third registers for controlling the memory cells via the first word lines of the memory block, and controlling the memory cells via the second word lines of the memory block. A read word address pointer having a plurality of fourth registers, and the write bit address A plurality of switches controlled by a pointer and supplying input data to the bit lines of the memory block selected by the write bit address pointer; and a switch controlled by the read bit address pointer and selected by the read bit address pointer A plurality of sense amplifiers for detecting data output from the bit lines of the memory block, and a common connection to the control electrodes of the plurality of transistors, and the first and second word lines and the write bit address pointer. And the read bit address pointer, and the write bit address pointer is controlled by the write bit address pointer, the write word address pointer, the read bit address pointer, and the read word address pointer. Data, the intersection of the bit line selected by the write word address pointer and the first word line, the bit line selected by the read bit address pointer and the read word address pointer, and the second word line. Selection means for turning on only the transistor of the memory cell at the intersection of the write bit address pointer and the write bit address pointer sequentially turning on the bit line every time the write word address pointer makes a round in the loop constituted by the third register. Each time the read word address pointer makes a round in the loop constituted by the fourth register, the bit line is sequentially selected by the read bit address pointer to read data, and the write bit address pointer and the write bit address pointer Write word address pointer and write The address being read, and the address being read by the write bit address pointer and the write word address pointer are separated from each other by at least as many addresses as the number of registers of the write word address pointer or the read word address pointer. It is characterized by

[0012]

According to the first aspect of the present invention, the write bit address pointer and the write word address pointer are writing the address and the read bit address pointer and the read word address pointer are reading the address from at least one of the memory blocks. To be apart from each other by the number of addresses means that the address for writing and the address for reading are different from each other by the number of addresses corresponding to one memory block. Therefore, the memory block to which the write bit address pointer and the write word address pointer write is always different from the memory block to which the read bit address pointer and the read word address pointer read. Therefore, even if the read and write access to one serial access memory are performed at the same time, the write bit address pointer and the write word are not simultaneously written and read using the same bit line or word line. The bit line and the word line can be shared by the address pointer, the read bit address pointer, and the read word address pointer, and the number of transistors can be reduced.

The order of writing to each memory cell of the memory block by the write bit address pointer and the write word address pointer in the second invention,
The read order of the read bit address pointer and the read word address pointer from each memory cell of this memory block can be the same, and the order of the input data and the output data can be the same.

The order of writing to each memory cell of the memory block by the write bit address pointer and the write word address pointer in the third invention,
In the reading order from each memory cell of this memory block by the read bit address pointer and the read word address pointer, the row and the column of this memory block can be exchanged.

The selection means in the fourth aspect of the present invention is the intersection of the bit line and the word line selected by the write bit address pointer and the write word address pointer or the bit line selected by the read bit address pointer and the read word address pointer. Since only the transistor of the memory cell at the intersection of the line and the word line is turned on, the transistor of the memory cell at the intersection of the write bit address pointer and the read word address pointer and the intersection of the read bit address pointer and the write word address pointer is not turned on.

Further, the write bit address pointer is writing and the read bit address pointer is reading from the address, which is at least as many as the write word address pointer or the register of the read word address pointer. Therefore, the write bit address pointer and the read bit address pointer write different bit lines.

Therefore, even if the serial access memory is simultaneously accessed for writing and for reading, the same bit line is not used at the same time, and a memory cell composed of one transistor and one capacitor is used. Can be used.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 1 is a memory block including a plurality of memory cells each including one transistor and one capacitor, 8 is a data input terminal, 9 is a data output terminal, and 2 is a register connected in a loop. , A write bit address pointer provided for each memory block, and 3 selects which bit line 17 the 8-bit data input from the data input terminal 8 is controlled by the write bit address pointer 2 connected thereto. Selector 4, which is configured by connecting registers in a loop, and a write word address pointer provided for each memory block 1, 5 is configured by connecting registers in a loop, provided by each memory block 1. The read bit address pointer 6 is provided for each memory block 1 and Sense amplifier group sense amplifier gathered more for being controlled by less pointer 5 reads data of memory cells of the memory block 1,
Reference numeral 7 is a read word address pointer which is formed by connecting registers in a loop and is provided for each memory block 1. Further, the plurality of write bit address pointers 2 and the plurality of read bit address pointers 5 are connected in a loop. The relationship between the write bit address pointer 2 and the write word address pointer 4 and the relationship between the read bit address pointer 5 and the read word address pointer 7 provided in the same memory block 1 are the same as in the conventional case. Further, the write bit address pointer 3 and the read bit address pointer 5 provided in the same memory block 1 share the same bit line, and the write word address pointer 4 and the read word address pointer provided in the same memory block 1 are shared. 7
Share the same word line (not shown in FIG. 1).

Next, the operation of the serial access memory shown in FIG. 1 will be described. First, the input data write operation will be described. The bit line 17 is selected by the selector 3 which is controlled by the write bit address pointer 2 in which registers are connected in a loop as in the conventional case. Then, the 8-bit input data input from the input terminal 8 is supplied to the bit line 17. The write word address pointer 4 selects one of the plurality of word lines. Then, the input data is written in the memory cell at the intersection of the selected word line and bit line 17 in the memory block 1. Further, the next bit line 17 is sequentially selected by the write bit address pointer 2 without moving the word line, and the input data is written in the memory cell of this bit line 17. When this operation is repeated and the loop constituted by the register of the write bit address pointer 2 is cycled, the next word line is selected, and the input data is written in the memory cell at the intersection of the word line and the bit line 17. Also in this word line, the next bit line 17 is sequentially selected by the write bit address pointer 2 without moving the selected word line, and the memory cell at the intersection of each bit line 17 and the word line is selected. Input data is written in. By repeating these operations, the loop composed of the register of the write bit address pointer 2 is cycled. Further, by repeating the above operation, the write word address pointer 4
When the loop constituted by the register of 1 is completed, the write processing of the memory block 1 is completed, and the write processing is performed by the write bit address pointer 2 and the write word address pointer 4 connected to the next memory block 1. That is, when the writing of one memory block 1 is completed, the data for the number of addresses of one of the memory blocks 1 is written, and the address of the data being written is larger than that before the writing is started. It means that it is preceded by 1 of 1.

Next, in the data read operation, the read bit address pointer 5 in which the registers are connected in a loop is used.
Thus, one of the plurality of sense amplifiers in the sense amplifier group 6 is selected. Further, one of the plurality of word lines is selected by the read word address pointer 7 having the registers connected in a loop. The data of the memory cell at the intersection of the selected word line and the bit line 17 connected to the selected sense amplifier is read out. Next, the selected word line is not moved and the next sense amplifier is sequentially selected by the read bit address pointer 5 and the data of the memory cell connected to the bit line 17 is read. When this operation is repeated to complete a loop of the read bit address pointer 5, the next word line connected to the read word address pointer 7 is selected,
The data of the memory cell at the intersection of the word line and the bit line 17 is read out. Furthermore, even in this word line,
The word line to be selected does not move and the next sense amplifier is sequentially selected by the read bit address pointer 5 without any change, and the data of the memory cell connected to the bit line 17 is read out. By repeating this operation, the loop constituted by the register of the read bit address pointer 5 is cycled. Further, when the loop constituted by the register of the read word address pointer 7 is cycled by repeating the above operation, the read processing is completed, and the read bit address pointer 5 connected to the next memory block 1
And the write processing is performed by the read word address pointer 7.

Next, the relationship between the memory block 1 in which the read operation is performed and the memory block 1 in which the write operation is performed will be described. For example, a read processing timing signal is delayed with respect to a write processing timing signal input from the outside, and the address of the memory cell in which writing is performed is always relative to the address of the memory cell in which reading is performed. The memory block 1 is preceded by at least one address. Therefore, the memory block 1 of the write bit address pointer 2 and the write word address pointer 4 which is writing and the memory block 1 of the read bit address pointer 5 and the read word address pointer 7 which are reading are always different.

Therefore, even if read and write access are simultaneously performed to one serial access memory, write and read are not performed at the same time by using the same bit line or word line. 2 and the write word address pointer 4 and the read bit address pointer 5 and the read word address pointer 7 can share the bit line and the word line, and the memory cell is configured with one transistor and one capacitor to reduce the number of transistors. can do.

In the above embodiment, each time the write bit address pointer 2 goes through the loop, the write word address pointer 4 selects the next word line. Similarly, the read bit address pointer 2 makes the loop. The read word address pointer 4 is configured to select the next word line each time the read word address pointer 2 goes through the loop. Alternatively, the write word address pointer 2 may be configured to select a line, and the write bit address pointer 4 may be configured to select the next bit line each time the write word address pointer 2 makes a round in the loop. Produce the effect of.

Further, in the above embodiment, the write word address pointer 4 is configured to select the next word line every time the write bit address pointer 2 goes through the loop, and at the same time, the read bit address pointer 5 goes through the loop. The read word address pointer 7 is configured to select the next word line after each cycle, but the write bit address pointer 2 selects the next bit line each time the write word address pointer 4 cycles through the loop. The read word address pointer 7 may be configured to select the next word line each time the read bit address pointer 5 makes a round in the loop. Alternatively, the write word address pointer 4 is configured to select the next word line every time the write bit address pointer 2 makes a round in the loop,
At the same time, the read bit address pointer 5 may be configured to select the next bit line each time the read word address pointer 7 makes a round in the loop. In this case, in addition to the same effect as that of the above embodiment, the order of data when writing and the order of data when reading can be changed. When the write data and read data are displayed in a matrix, the rows and columns of the data read and written to this memory block can be exchanged,
For example, when storing image data in a memory block and the number of rows and columns of the memory block is the same, this image data can be rotated.

Next, another embodiment of the present invention will be described with reference to FIG.
3 and FIG. FIG. 2 is a block diagram of a serial access memory according to another embodiment of the present invention.
In the figure, 18 is a memory block composed of memory cells each including one transistor and one capacitor,
16 is a bit line connected to the selector 11 and the sense amplifier 14, 30 is a transistor forming a memory cell,
31 is a capacitor forming a memory cell, and 33, 3
4 is an AND gate, 35 is an OR gate, 50 is a selection circuit constituted by AND gates 33 and 34 and the OR gate 35, and 36 is a selection circuit 5 for the control signal from the register 10.
0 is a signal line, 37 is a first word line controlled by the register 12, 38 is a signal line for transmitting a control signal from the register 13 to the selection circuit 50, 39 is a second word line controlled by the register 12. Is. Other reference numerals that are the same as those in FIG. 4 indicate the same or corresponding portions as in FIG. Then, FIG. 3 shows the relationship between the selection circuit 50 and 8-bit memory cells. As shown in the figure, the gates of the transistors 30 of the memory cell for 8 bits are all connected to the output terminal of the OR gate 35.

Next, the operation of the serial access memory shown in FIG. 2 will be described. First, the data write operation will be described. As in the conventional case, the bit line 16, that is, the leftmost bit line 16 in the figure is selected by the switch 11 controlled by the write bit address pointer 2 in which the register 10 is connected in a loop. Then, the 8-bit data input from the input terminal 8 is supplied to the bit line 16. The write word address pointer 4 selects one of the plurality of first word lines 37. Then, the first selected one of the memory blocks 1
The memory cell at the intersection of the word line 37 and the bit line 16 is selected by the selection circuit 50, and the input data is written in this memory cell. Further, the next word line 37 is sequentially selected by the write word address pointer 4 without moving the bit line 16 and the data is written in the memory cell connected to this word line 37. When this operation is repeated and the loop constituted by the register 12 of the write bit address pointer 2 is cycled, the next word line 3
7 is selected, the memory cell at the intersection of the word line 37 and the bit line 16 is selected by the selection circuit 50, and data is written in this memory cell. By repeating these operations, the loop constituted by the register 12 of the write word address pointer 4 is cycled. When the loop constituted by the register 10 of the write bit address pointer 2 is cycled by repeating the above operation, the write processing of the memory block 18 is completed.

In the read operation, one of the plurality of sense amplifiers 14, here, the leftmost sense amplifier 14 is first selected by the read bit address pointer 5 in which the register 13 is connected in a loop. Further, one of the plurality of word lines 39 is selected by the read word address pointer 7 in which the register 15 is connected in a loop. The memory cell at the intersection of the selected word line 37 and the selected bit line 17 connected to the sense amplifier 14 is selected by the selection circuit 50, and the data of this memory cell is read. Next, the bit line 16 to be selected does not move, and the next register 15 is sequentially selected without changing its position.
The data of the memory cell connected to the word line 37 is read out. When this operation is repeated and the loop of the read word address pointer 7 is cycled, the next word line 37 connected to the switch 11 is selected by the read bit address pointer 7 and the memory cell at the intersection of the word line 37 and the bit line 16 is selected. Selected by the selection circuit 50, the data of this memory cell is read out. In this bit line 16 as well, the selected bit line 16 does not move, and the next register 15 is sequentially moved by the read word address pointer 7 and is connected to the selected bit line 37 by the register 15. The data in the memory cell is read out. By repeating these operations, the loop constituted by the register of the read word address pointer 5 is cycled. Further, by repeating the above-described operation, the loop constituted by the register of the read bit address pointer 7 makes one round, and the reading process is completed.

Next, the relationship between the bit line 16 on which the read operation is performed and the bit line 16 on which the write operation is performed will be described. For example, a read processing timing signal is delayed with respect to a write processing timing signal input from the outside, and the address of the memory cell in which writing is performed is always relative to the address of the memory cell in which reading is performed. The write word address pointer 4 and the read word address pointer 7 are separated from each other by at least the number of registers. Therefore, the bit line 16 of the write bit address pointer 2 and the write word address pointer 4 which is writing and the bit line 16 of the read bit address pointer 5 and the read word address pointer 7 which are reading are always different. Further, by the operation of the selection circuit 50, the intersection of the bit line 16 selected by the write bit address pointer 2 and the word line 39 selected by the read word address pointer 7 and the bit line 38 selected by the read bit address pointer 5 And the transistor 30 of the memory cell at the intersection of the word line 37 selected by the write word address pointer 4 does not turn on.

Therefore, even if read and write access are simultaneously performed to one serial access memory, write and read are not performed at the same time by using the same bit line 16, and the write bit address pointer 2 and Read bit address pointer 5 and bit line 1
6 can be shared, and one transistor and one capacitor can form a memory cell. Although there is an increase in the number of transistors due to the selection circuit 50, conventionally one AND gate is required for one memory cell, but one selection circuit for 8 bits is sufficient. Can be reduced.

In each of the above embodiments, the input / output of data was performed by the 8-bit bus, but the effect of the present invention is that the bit number of the bus used for the serial access memory is independent of the bit number of the bus. Any number of bits will do.

[0031]

As described above, according to the serial access memory of the inventions according to claims 1, 2 and 3, the memory block is constituted by a plurality of memory cells each including one transistor and one capacitor. A write bit in which a plurality of memory blocks each having a plurality of connected bit lines and word lines and a plurality of first registers connected in a loop form, and a plurality of write bit address pointers corresponding to the memory blocks one-to-one are connected in a loop form. A read bit address pointer group in which a plurality of read bit address pointers each having a one-to-one correspondence with a memory block, which is composed of an address pointer group and a plurality of second registers connected in a loop shape, and a word of the corresponding memory block are connected. A plurality of third registers controlling memory cells via lines, Memory block, the same number of write word address pointers and the same number of read word address pointers as the memory block having a plurality of fourth registers for controlling memory cells via the word line of the corresponding memory block, The address being written by the word address pointer and the write bit address pointer and the address being read by the read word address pointer and the read bit address pointer are separated by at least one memory block address. Since it is configured, the write bit address pointer and the write word address pointer and the read bit address pointer and the read word address pointer can share the same bit line and the same word line. The by reducing able to improve the integration degree of the serial memory cells, there is an effect that the serial access memory having a large capacity can be easily obtained.

Further, according to the serial access memory of the second aspect of the present invention, the writing order to each memory cell of the memory block by the write bit address pointer and the write word address pointer, and the memory cell of this memory block The read order by the read bit address pointer and the read word address pointer can be the same, the order of input data and the order of output data can be the same, and the input data and the output data for the serial access memory are the same. There is an effect that can be.

Further, according to the serial access memory of the present invention as defined in claim 3, the write order to each memory cell of the memory block by the write bit address pointer and the write word address pointer, and the memory cell of this memory block In the reading order by the read bit address pointer and the read word address pointer, this can be performed by exchanging rows and columns of this memory block. For example, when storing image data in the memory block, the number of rows and columns of the memory block can be changed. In the case of the same, there is an effect that this image data can be rotated.

According to another aspect of the serial access memory of the present invention, a plurality of memory cells each including one transistor and one capacitor are provided, and a bit line for transmitting a signal to each of the memory cells and a first line. And a plurality of memory blocks each having a plurality of second word lines, and a common connection to the control electrodes of the plurality of transistors, the first and second word lines, the write bit address pointer, and the read bit address. Connected to a pointer, controlled by the write bit address pointer, the write word address pointer, the read bit address pointer, and the read word address pointer, and selected by the write bit address pointer and the write word address pointer. Bit line and the first Selection of turning on only the transistor of the memory cell at any one of the intersection of the read line address pointer and the intersection of the bit line and the second word line selected by the read bit address pointer and the read word address pointer A memory cell comprising one transistor and one capacitor, since the address for writing is separated from the address for reading by at least as many addresses as the number of registers of the write word address pointer or the read word address pointer. Can also perform the write operation and the read operation to the serial access memory at the same time, the number of transistors can be reduced and the occupied area of the memory cell can be reduced to improve the integration degree of the serial memory cell. , Large capacity serial access memo There is an effect that can be obtained easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial access memory according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a serial access memory according to another embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between a selection circuit and memory cells of the serial access memory shown in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional serial access memory.

5 is a circuit diagram of one memory cell unit forming the serial access memory shown in FIG.

[Explanation of symbols]

 1 memory block 2 write bit address pointer 3 selector 4 write word address pointer 5 read bit address pointer 6 sense amplifier group 7 read word address pointer 8 data input terminal 9 data output terminal 10, 12, 13, 15 register 11 switch 14 sense amplifier 16, 17 bit line 18 memory block 50 selection circuit

Claims (4)

[Claims] 1. A plurality of memory blocks each having a plurality of memory cells each including one transistor and one capacitor, each memory cell having a plurality of bit lines and word lines, and a plurality of memory blocks connected in a loop. The memory is composed of a plurality of write bit address pointers, each of which is composed of a plurality of first registers and connected in a loop with a plurality of write bit address pointers corresponding to the memory block, and a plurality of second registers, which are connected in a loop. A read bit address pointer group in which a plurality of read bit address pointers corresponding to the block one-to-one are connected in a loop, and a plurality of third registers for controlling the memory cells via the word lines of the corresponding memory block. The same number of write word address pointers as the memory blocks, Controlled by the same number of read word address pointers as the memory block, which has a plurality of fourth registers for controlling the memory cells via the word lines of the corresponding memory blocks, and the corresponding write bit address pointers, A plurality of selectors for supplying input data to the bit line selected by the write bit address pointer and the corresponding read bit address pointer are controlled and output from the bit line selected by the read bit address pointer. A plurality of sense amplifiers for detecting data, the write word address pointer and the address to which the write bit address pointer is writing, and the read word address pointer and the read bit address pointer to read The serial access memory is characterized in that the addresses performing the operation are separated from each other by at least the number of addresses corresponding to one of the memory blocks. 2. A first of the plurality of memory blocks
Memory block of the first memory block, the write bit address pointer corresponding to the first memory block is
Each time the loop constituted by the registers is cycled, the word line is sequentially selected by the write word address pointer corresponding to the first memory block to write data, and the write word address pointer is set to the first word block. The data write processing to the first memory block is completed when the loop constituted by the three registers is completed, and the memory block other than the first memory block and the write bit address pointer and the write word corresponding to the memory block In the second memory block of the plurality of memory blocks, the read bit address corresponding to the second memory block is transferred at the same time as the write processing to the first memory block is performed. The pointer consists of the loop composed of the second register Sequentially selecting the word lines by the read word address pointer corresponding to a memory block of the second data read is performed every time the cruiser, further the read word address pointer fourth
When the loop constituted by the register is completed, the read processing of the second memory block is completed and the read bit address pointer and the read word address pointer corresponding to the memory block other than the second memory block are used. Or move to processing, or in the first memory block of the plurality of memory blocks, the write word address pointer corresponding to the first memory block makes a round in the loop constituted by the third register. Each time, the write bit address pointer corresponding to the first memory block sequentially selects the bit line to write data, and the write bit address pointer goes through a loop constituted by the first register. When the processing of the first memory block is completed, The process shifts to a process by a memory block other than the first memory block among the plurality of memory blocks, and the write bit address pointer and the write word address pointer corresponding to the memory block, and a write process to the first memory block At the same time, in the second memory block of the plurality of memory blocks, each time the read word address pointer corresponding to the second memory block goes through the loop formed by the fourth register, the second word The bit line is sequentially selected by the read bit address pointer corresponding to the memory block to read the data, and the read bit address pointer is set to the second bit line.
Processing of the second memory block is completed when the loop constituted by the registers is completed, and a memory block other than the second memory block among the plurality of memory blocks and the corresponding read bit address pointer 2. The serial access memory according to claim 1, wherein processing shifts to processing by the read word address pointer. 3. A first of the plurality of memory blocks
Memory block of the first memory block, the write bit address pointer corresponding to the first memory block is
Each time the loop constituted by the register is cycled, the word line is sequentially selected by the write word address pointer corresponding to the first memory block to write data, and the write word address pointer is set to When one loop of a loop constituted by registers is completed, the data write processing to the first memory block is completed and the memory block other than the first memory block among the plurality of memory blocks and the write bit address corresponding thereto The processing shifts to processing by the pointer and the write word address pointer, and at the same time as the writing processing to the first memory block, the second memory block in the second memory block among the plurality of memory blocks corresponds to the second memory block. The read word address pointer The bit line is sequentially selected by the read bit address pointer every time the loop made up of two registers is made, and the second memory block is made when the read bit address pointer goes around the loop made up of the second register. Processing is terminated and the processing is shifted to processing by a memory block other than the second memory block among the plurality of memory blocks and the read bit address pointer and the read word address pointer corresponding thereto, or In the first memory block of the memory blocks of the first memory block, the write word address pointer corresponding to the first memory block is stored in the first memory block every time the write word address pointer makes a round in the loop formed by the third register. By the corresponding write bit address pointer, Line is sequentially selected, and when the write bit address pointer completes a loop of the first register, the processing of the first memory block is completed and the first of the plurality of memory blocks is selected. The process shifts to a process using a memory block other than the memory block and the write bit address pointer and the write word address pointer corresponding thereto, and at the same time as the writing process to the first memory block, In the second memory block, the second
Every time the read bit address pointer corresponding to the memory block makes a round in the loop formed by the second register, the read word address pointer corresponding to the second memory block sequentially selects the word line Is read out, and when the read word address pointer completes a loop of the fourth register, the read processing of the second memory block is ended and the second of the plurality of memory blocks is read.
2. The serial access memory according to claim 1, wherein the process shifts to a process using a memory block other than the memory block, the read bit address pointer corresponding thereto, and the read word address pointer. 4. A plurality of memory blocks each including a plurality of memory cells each including one transistor and one capacitor, each bit line transmitting a signal to the memory cell, and a plurality of first and second word lines. A write bit address pointer composed of a plurality of first registers connected in a loop, a read bit address pointer composed of a plurality of second registers connected in a loop, and the first word line of the memory block A write word address pointer having a plurality of third registers for controlling the memory cell via a memory cell, and a plurality of fourth registers controlling the memory cell via the second word line of the memory block. Controlled by the read word address pointer and the write bit address pointer, A plurality of switches for supplying input data to the bit line of the memory block selected by an address pointer; and a bit line of the memory block controlled by the read bit address pointer and selected by the read bit address pointer. A plurality of sense amplifiers for detecting the output data, and a common connection to the control electrodes of the plurality of transistors, and to the first and second word lines, the write bit address pointer, and the read bit address pointer. Connected, controlled by the write bit address pointer, the write word address pointer, the read bit address pointer, and the read word address pointer, and the write bit address pointer and the write word address pointer Any of the intersection of the bit line and the first word line selected by, and the intersection of the bit line and the second word line selected by the read bit address pointer and the read word address pointer. Selecting means for turning on only the transistor of the memory cell, the write word address pointer sequentially selecting the bit line by the write bit address pointer every time the write word address pointer goes through a loop constituted by the third register, Each time the read word address pointer makes one round in the loop constituted by the fourth register, the read bit address pointer sequentially selects the bit lines to read data, and the write bit address pointer and the write word address Address written by the pointer And the addresses read by the write bit address pointer and the write word address pointer are separated from each other by at least the same number of registers as the write word address pointer or the read word address pointer. Serial access memory.