JPH05268061A - Ecl logic circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption without sacrificing a switching speed by connecting a P-channel MOS transistor(TR) to a bipolar TR of an ECL logic circuit forming a current switching circuit. CONSTITUTION:A gate of a P-channel MOS TR M1 connects to a base of a bipolar TR Q1 of a current switching circuit 1, its drain connects to a collector of the TR Q1, its source connects to a power supply, and when an input signal S changes to an L level, the TR Q1 is turned off, the TR M1 is turned on, a current ID flows momentarily and a parasitic capacitance of the collector of the TR Q1 is rapidly charged. Thus, even when a load resistance R1 is increased to secure a sufficient logic amplitude when a switching current IE is low, the channel resistor is sufficiently low the moment when the TR M1 is turned on, and the time constant is reduced. Thus, a leading time of an output signal A of the collector of the TR Q1 is reduced, and the power consumption is suppressed without sacrificing the switching speed via a large load resistor.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to ECL logic circuits.
In particular, the present invention relates to an ECL logic circuit whose speed is increased.

[0002]

2. Description of the Related Art In a conventional ECL logic circuit, as shown in FIG.
A current switch circuit 4 composed of bipolar transistors Q1 and Q2 having load resistors R1 and R2, one end of which is connected to D, an output circuit 2 composed of an emitter follower of a bipolar transistor Q3 which outputs an output signal O, and a bipolar transistor Q1. The constant current circuit 3 is connected to the common emitter connection point of Q2 and supplies the emitter current IE from the power supply VS.

The input signal S is applied to the base of the bipolar transistor Q1 of the current switch circuit 4, and the reference voltage R is applied to the base of Q2.

Next, the operation of the conventional ECL logic circuit will be described.

In this conventional ECL logic circuit, switching is performed by alternately switching the emitter currents IE of the bipolar transistors Q1 and Q2 by the input signal S. When the input signal S changes from "H" to "L", the bipolar transistor Q1 is cut off, and the rise time trP of the output signal P at the collector is determined by the product of the load resistance R1 and the parasitic capacitance of the collector of Q1. Was decided.

On the other hand, low power consumption is required for high integration, and therefore there is a tendency to reduce the switching current of the ECL logic circuit, that is, the emitter current IE as much as possible. In this case, it is necessary to increase the resistance values of the load resistors R1 and R2 in order to secure the minimum necessary logic amplitude.

[0007]

DISCLOSURE OF THE INVENTION The above-mentioned conventional ECL
In the logic circuit, it is necessary to increase the value of the load resistance in order to reduce the power consumption required for high integration, which causes a drawback that the rise time of the output signal becomes long.

An object of the present invention is an EC capable of eliminating the above-mentioned drawbacks and reducing power consumption without sacrificing switching speed.
To provide an L logic circuit.

[0009]

SUMMARY OF THE INVENTION An ECL logic circuit of the present invention comprises a current switch circuit comprising first and second bipolar transistors having load resistors whose emitters are commonly connected and each collector has one end connected to a power supply. In the ECL logic circuit, the first and second gates are connected to the base of at least one of the first and second bipolar transistors, the drain is connected to the collector, and the source is connected to the power supply. The junction type of the bipolar transistor is used as a conductive type MOS transistor having a polarity opposite to that of the bipolar type.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the ECL logic circuit of the present invention.

As shown in FIG. 1, the ECL logic circuit of this embodiment includes bipolar transistors Q1, Q2, and Q1 having load resistors R1 and R2 whose emitters are commonly connected and whose collectors have one ends respectively connected to a power supply VD. A current switch circuit 1 including a P-channel type MOS transistor M1 in which a gate is connected to a base, a drain is connected to a power source VD, and a source is connected to each other; and an output circuit 2 including an emitter follower of a bipolar transistor Q3 which outputs an output signal O; It is connected to a common connection point of the emitters of the bipolar transistors Q1 and Q2, and from the power source VS to the emitter current I.
And a constant current circuit 3 for supplying E.

The input signal S is applied to the base of the bipolar transistor Q1 of the current switch circuit 1, and the reference voltage R is applied to the base of Q2.

Next, the operation of this embodiment will be described.

When the input signal S changes from "H" to "L", the bipolar transistor Q1 is turned off.
At the same time, the P-channel type MOS transistor M1 becomes conductive, and the current ID instantaneously flows. This current ID rapidly charges the parasitic capacitance of the collector of the bipolar transistor Q1.

According to the above operation principle, even if the value of the load resistor R1 is increased in order to secure a sufficient logic amplitude when the switching current IE is low, the channel is not turned on at the moment when the P-channel type MOS transistor M1 becomes conductive. Since the resistance is sufficiently low, the time constant can be reduced. Therefore, as compared with the conventional ECL logic circuit, the rise time trA of the output signal A at the collector of the bipolar transistor Q1 can be reduced, that is, the switching time can be shortened.

FIG. 2 is a waveform diagram showing an example of the simulation result of the operation of the ECL logic circuit of this embodiment in comparison with the conventional ECL logic circuit.

In FIG. 2, the rising time trP of the output signal P at the collector of the bipolar transistor Q1 of the conventional ECL logic circuit is 1.490 nS. On the other hand, the rise time trA of the output signal A at the same point of the ECL logic circuit of the present embodiment having the same load resistance is 0.945 nS, which is 36.6% shorter than the conventional case. Results have been obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, an input signal is applied to the bases of the two transistors forming the current switch circuit,
2 inputs and 2 outputs from each collector
Of course, it is also applicable to equip the collectors of both transistors of the output ECL logic circuit with P-channel type MOS transistors, respectively, without departing from the gist of the present invention.

[0020]

As described above, according to the ECL logic circuit of the present invention, the gate is connected to the base of the bipolar transistor of the current switch circuit, the drain is connected to the collector, the source is connected to the power supply, and the bipolar transistor of the current transistor is connected. By providing a conductive type MOS transistor with a polarity opposite to that of the junction type, the rise time of the output signal can be shortened even if the value of the load resistance is increased, so low power consumption is achieved without sacrificing switching speed. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an ECL logic circuit of the present invention.

FIG. 2 is a waveform diagram showing an example of a simulation result of the operation of the ECL logic circuit of the present embodiment in comparison with a conventional ECL logic circuit.

FIG. 3 is a circuit diagram showing an example of a conventional ECL logic circuit.

[Explanation of symbols]

 1,4 Current switch circuit 2 Output circuit 3 Constant current circuit M1 MOS transistor R1, R2 Load resistance Q1-Q3 Bipolar transistor

Claims (2)

[Claims] 1. An ECL logic circuit comprising a current switch circuit comprising first and second bipolar transistors having emitters connected in common and having collectors each having one end connected to a power supply and having load resistors. Of at least one of the bipolar transistors, the gate of which is connected to the base, the collector of which is connected to the drain of which the source is connected to the source of which the conductivity type is opposite to the junction type of the first and second bipolar transistors. An ECL logic circuit including the MOS transistor of. 2. The ECL logic circuit according to claim 1, wherein the junction type is NPN type and the conductivity type is P type.