JPH0528032A - Data alignment device - Google Patents

Abstract

PURPOSE:To provide the small micro processor by performing data alignment with the use of shift arithmetic device to be used for the arithmetic execution processing in a microprocessor transferring data with a smaller number of bits than the data bus width to an external memory. CONSTITUTION:The data alignment device is provided with a SHIFT 220 performing shift operation, a SOPR 221 holding the type of shift operation, an SB 222 holding the number of shift bits, a data type signal DTYP to be notified from an instruction decode unit, an ALBGEN 228 generating the number of align bits by an internal address IA to be notified from an effective address calculation unit, and an SBMPX 223 notifying the output of the SB 222 or the ALBGEN 228 selectively to the SHIFT 220 as the number of shift bits according to the information held in the SOPR 221.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data alignment (Al) when accessing an external memory of a microprocessor.
igne: The data width of the microprocessor that controls the data pins of the microprocessor according to the address and data bit width assigned to the external memory when transferring data that is less than the bit width of the unaligned data bus. Regarding the alignment device.

[0002]

2. Description of the Related Art In an information processing system using a microprocessor, the bit width of a data bus that transfers data between the microprocessor and an external memory that stores instruction codes and operand data affects the processing performance. give. Today, most high-performance microprocessors
It has a 32-bit wide data bus.

On the other hand, program processing does not always process data having the same width as the data bus width. ASCII characters are represented by 8 bits, and JI
The S-Kanji character is represented by 16 bits. Also, when dealing with numerical values, 8 bits or 16 bits are often sufficient. Therefore, in program processing, 8
It is usual that data of / 16/16/32 bit width is mixedly present. Therefore, even if the external memory device is 8
/ 16/16 / 32-bit operands are mixed.

Of course, like a floating point number, it may not be represented by 32 bits and may require a bit width of 64 bits or more, but it is not mentioned here.

When accessing the operand stored in the external memory device, the microprocessor notifies the address where the operand is stored via the address bus.

The external memory stores data having a minimum bit width, that is, 8-bit width data (byte data) in this case.
In order to be able to access the above, a structure of 8 bits is adopted.

FIG. 4 shows a 32-bit wide data bus D0-
An external memory 402 (denoted as MEM in the figure) having a D31
A microprocessor connected to the (referred to as CPU in the figure)
Shows the configuration of. The external memory 402 is composed of 8-bit unit memory banks M0 to M3 410 to 413. The memory bank M0 410 has a data bus D0-
D7, M1 411 is the data bus D8-D15, M2
412 is a data bus D16-D23, M3 413
Corresponds to 8 bits on each of data buses D24-D31. Each memory bank is a microprocessor 401
Is notified of a common 30-bit width address A31-A2. At the same time, each memory bank has an enable signal for indicating the validity of each memory bank, BE04 (-) for M0410, BE1 (-) for M1 411, and M2.
BE2 (-) for 412 and BE3 for M3 413
(-) Is notified from the microprocessor 401. The memory bank in which the enable signal is active will be accessed at the address specified by the address bus.

Enable signals BE0 (-) to BE3
By using (-), it is not only unnecessary to notify the lowest 2 bits of the 32-bit width address (hereinafter referred to as an internal address) internally generated by the microprocessor 401, but also the data Bus width (32 bits)
It is possible to access less than 8 / 16-bit data. Here, "(-)" indicates that the signal has negative logic.

FIG. 8 shows the relationship between memory banks and data bus terminals accessed according to internal addresses and data types.

Further, between the microprocessor 401 and the external memory 402, a memory control device 403 (M in the figure).
CON).

From the microprocessor 401 to the memory controller 403, status signals ST0-ST2 indicating the type of bus cycle (for example, for memory space or for I / O space), start of bus cycle. , And a status signal R / W (−) indicating the direction (read / write) of data transfer performed in the bus cycle are connected.
By these status signals and timing signals, the read timing signal RD for the external memory,
And a write timing signal WR.

At the same time, in order to guarantee the access time required to access the external memory 402, the ready signal R
EADY (-) is generated and notified to the microprocessor 401. While the ready signal READY (-) is inactive, the bus cycle started by the microprocessor 401 does not end and holds the current state.

A functional unit that controls an interface related to data transfer with the external memory 402 inside the microprocessor 401 is called a bus interface unit.

Next, the external memory 40 of the microprocessor 401 for each operand of 8/16/32 bits
The operation of accessing 2 will be described. (1) 8-bit operand: The use of the data bus differs in 8-bit units depending on the value of the internal address. When the bus cycle is issued from the microprocessor 401, if the least significant 2 bits of the internal address are 00b, D0
BE0 (-) signal to use -D7, BE1 (-) signal to use D8-D15 if 01b, D16-D23 to use BE for 10b
The BE3 (-) signal is activated so as to use the 2 (-) signal and D24-D31 for 11b, respectively. (2) 16-bit operand: The use of the data bus differs in units of 16 bits depending on the value of the internal address.
In the microprocessor 401, 16-bit data is restricted to be placed at an address where the least significant 1 bit of the internal address is 0b. Microprocessor 401
When the bus cycle is issued from the internal address, the least significant 2 bits of the internal address are 0Xb (“X” is Don't Cade
, Which means that the bits are D0-D1
BE0 (-) signal and BE1 to use 5
The BE2 (-) signal and the BE3 (-) signal are activated to use the (-) signal and D16-D31 for 1Xb, respectively. (3) 32-bit operand microprocessor 4
At 01, the 32-bit data is restricted to be placed at an address where the least significant 2 bits of the internal address are 00b. BE0 to use D0-D31 when a bus cycle is issued from the microprocessor 40
All of the (-) to BE3 (-) signals are active at the same time.

In the microprocessor 401, by limiting the memory allocation of 16-bit and 32-bit operands, one operand access can be completed in one bus cycle.

Although omitted in the drawing, the microprocessor 401 has a general-purpose register for storing operand data. In order to transfer data between the external memory 402 and general-purpose registers, the microprocessor 401
Has a LOAD command and a STORE command.
The LOAD instruction initiates a bus cycle and transfers an operand from external memory to a general register.

The STORE instruction activates a bus cycle and transfers an operand from a general purpose register to external memory 401.

In addition, arithmetic instructions such as arithmetic / logic / shift are performed on the data stored in the general-purpose register, and the arithmetic result is returned to the general-purpose register.

The general purpose register stores the 8/16/32 bit data transferred from the external memory 402.
Whether storing any type of data, the LSB
The position of (Least Significant Bit: least significant bit) is commonly set to 0 for the following reason.

The contents of the general-purpose register are transferred via an internal data bus to an arithmetic unit such as a binary arithmetic logic unit ALU or a shifter, which is omitted in the drawing, to perform a necessary arithmetic operation. At this time, if the LSB positions of the data having each data type are not aligned, the correct calculation cannot be performed.

For example, the least significant 2 bits of the internal address are 0
When the 8-bit data α arranged at the address 1b is taken into the microprocessor 401 from the data bus as it is, XXαX (X is Don't Care)
It means that it is 8-bit data) and α
The LSB of is located at bit 8 when treated as 32-bit data.

Similarly, the 16-bit data βγ arranged at the internal address 1Xb becomes βγXX,
The LSB will be located in bit 16.

In order to avoid the above-mentioned mismatch of LSB positions, each data is XX before execution of the operation instruction.
It is necessary to convert to the Xα and XXβγ formats.

Since the execution timing of the arithmetic instruction is indefinite, it is necessary to perform the above-mentioned LSB position conversion when the LOAD instruction is executed.

In the microprocessor 401, a functional unit that includes a general-purpose register, a binary arithmetic logic unit, a shifter, etc., and executes an instruction execution process is called an execution unit.

On the other hand, if the memory operand once fetched by the microprocessor 401 is always aligned in the LSB position regardless of the internal address to be stored, the LSB position will always be the same when writing to the external memory 402. It will be aligned to bit 0. An inverse translation of the LSB location is required according to the internal address and data type when executing the STORE instruction.

The function of converting the LSB position according to the internal address and the data type at the time of data transfer between the microprocessor 401 and the external memory 402 is called a data align function.

[0028]

Conventionally, the bus interface unit is in charge of the data align function in the microprocessor, and dedicated hardware is used. The reason why you need dedicated hardware is
1) To minimize the conversion time 2) Bus
This is because the interface unit and the execution unit operate independently of each other.

Regarding conventional data alignment, as shown in US Pat. No. 4,624,660, C
It is said to be the responsibility of the bus controller, which is arranged between the PU and the storage device and coordinates the work of the address bus and the data bus. In FIG. 1 between the central processing unit 12 and the storage unit 20
The data bus interface 18 controls the bus, and the address bus interface 16 controls the address bus. Data bus
Misaligned by the interface 18 (misal
(i.g., the central processing unit 12)
And the data aligned with the internal data buses IDB0 to IDB31 are transferred between them. Fig. 13, 15,
External data, as can be seen from the data bus interface 18 described in 8-bit units 19 and 20,
The buses D0 to D31 are arranged in 8-bit units (D0 to D7,
D8-D15, D16-D23, D24-D31) Arbitrary 8 bits (IDB0-IDB7, IDB8-IDB15, ID) of internal data bus IDB0-IDB31
B16-IDB23, IDB24-D31) is required. Specifically, FIG. As shown in 21, a bidirectional multiplexer for selectively connecting 4 bits of the internal data bus per 1 bit of the external data bus is used. The bus controller 14
1) Control for address bus interface 16 and data bus interface 18, 2) Judgment of aligned data transfer, 3) Activation of necessary bus cycle, 4) Control signal for storage device 20 Is issued.

As mentioned above, in order to realize the data align function, it is suggested that dedicated hardware for exchanging 8 bits each between the external data bus and the internal data bus is required.

Such dedicated hardware has the following drawbacks. (1) A logic circuit only for the data align function is required, which causes an increase in device scale. (2) In the case of realizing it in a semiconductor integrated circuit, mutual exchange of signal lines causes an increase in wiring area and reduces the efficiency of use of the number of effective transistors on the device. (3) By inserting a circuit between the internal data bus and the external data bus, the operation speed is reduced.

[0032]

In order to overcome the above-mentioned drawbacks, the device according to the present invention is a data aligner for a microprocessor for transferring data having a bit length smaller than the bit length of the data bus width to an external memory. In the device, an internal data bus for transferring data when executing an instruction, a shift arithmetic unit connected to the internal data bus, and a part of an address to an external memory to be accessed and a bit length of data should be aligned. It is characterized by having means for generating the number of bits.

That is, in the present invention, the data align function is realized by using the shifter in the execution unit used for the shift instruction, the floating point operation instruction, etc. as a common resource.

[0034]

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a schematic structure of a microprocessor 100 which can be connected to a 32-bit data bus and can access 8/16 / 32-bit data by utilizing the present invention.

The microprocessor 100 has an instruction fetch unit (hereinafter referred to as IU) 101, an instruction decode unit (hereinafter referred to as DU) 102, and an instruction execution unit (hereinafter referred to as EU) in order to perform pipeline processing. 103, effective address calculation unit (hereinafter AU
104) and a bus interface unit (hereinafter referred to as BU) 105.

The IU 101 stores the instruction code fetched from the outside in the fetish cycle activation control and the fetch cycle. A configuration including an instruction code cache is also conceivable. The instruction code has either a 16-bit length or a 32-bit length. It is assumed that each instruction code is placed from the halfword boundary of the memory (the least significant bit of the internal address is 0b).

The DU 102 decodes the instruction code stored in the IU 101, and generates a signal indicating the processing peculiar to each instruction. Typical signals include 1) type of instruction execution processing, 2) type of operand (memory / register number), 3) data type of operand, and 4) recognition of special instruction. The signal generated by the DU 102 is given as an operation instruction signal for each of the other units, although part of the signal is omitted in the drawing.

The EU 103 comprises 32 32-bit wide general-purpose registers, a 32-bit wide arithmetic logic unit ALU,
It includes a barrel shifter and the like, and executes an instruction execution process designated by the DU 102. The internal control may be based on a hardwired logic, a microprogram, or the like.

When the AU 104 detects that the DU 102 is an instruction including access to memory or I / O, it calculates an address for an operand. As the element used for the address calculation, the displacement value included in the instruction code or the content of the general-purpose register is used as the base value. The former is from IU101,
The latter is supplied by EU 103.

There are operand data of 8/16/32 bits, and 16-bit data starts from a half word boundary (the least significant bit of the internal address is 0b) and 32-bit data starts at a word boundary (the internal address has the least significant bit). It is assumed that the lower 2 bits are arranged from 00b).

BU 105 generates an external bus cycle based on address information, data information and activation request given from another unit. The data read from the outside in the bus cycle has an instruction code of IU10.
1, the operand data is supplied to the EU 103.

Each unit is internally connected by a bus structure as schematically shown in FIG.

Operands between BU 105 and IU 101
In order to transfer the address (via internal address bus IA0-IA31) and instruction code used in a bus cycle other than access, between IU101 and DU102, between AU104 and IU101, in order to transfer the instruction code.
And between AU104 and EU103 to transfer address elements used for address calculation (IA0-IA3
1), in order to bidirectionally transfer a read operand or a write operand between the EU 103 and the BU 105 (via internal data buses ID0-ID31),
In order to transfer an effective address between AU104 and BU105 (via IA0-IA31), EU103 and BU1
Between 05, it is connected (via IA0-IA31) to transfer the address used in any bus cycle.

In the drawing, the internal data buses ID0 to ID31 are shown as a single bus having a 32-bit width for simplification of description, but in reality, they are composed of a plurality of 32-bit buses.

The bus cycle activation request from the IU 101 is represented by the FREQ signal, the one from the DU 102 by the OPREQ signal, and the one from the EU 103 by the ACREQ signal. These request signals are actually composed of a plurality of signals for expressing the type of bus cycle and a plurality of signals such as signals for defining the timing.

BU 105 is associated with a bus cycle,
Address bus terminals A2-A3112 for outputting a 30-bit word address (32-bit unit address)
Data bus terminals D0-D31 122 for exchanging 1 and 32 bit data, and byte enable output terminals BE0 (-) to BE3 (indicating which 8-bit position of the data bus terminal is used to transfer valid data. -) 123
(BE0 (-) is D0-D7, BE1 (-) is D8-D
15, BE2 (-) corresponds to D16-D23, BE3 (-) corresponds to D24-D31), and a status terminal ST0 indicating the type of bus cycle (for example, memory space or I / O space). -ST21
24, a timing output terminal (BCYST (-) 125 indicating the start of a bus cycle, and a status output terminal R / W (-) 126 indicating the direction (read / write) of data transfer performed in the bus cycle.

The basic bus cycle consists of two states T1 and T1 synchronized with the reference clock signal CLK applied to the clock input terminal 128 of the microprocessor 100.
It consists of 2.

The state of the READY (-) input terminal 127 is sampled in the T2 state, and if inactive, the T2 state is repeated until it becomes active. At this time, if the state of the READY (-) input terminal 127 is active, the idle state Ti is entered and the bus cycle ends.

FIG. 2 is a drawing showing the details of the EU 103 and the configuration up to the data bus terminal 122.

EU103 is a microprogram ROM
A micromachine controlled by microinstructions stored in an (hereinafter abbreviated as MROM) 202 and stored at an address designated by a microprogram counter (hereinafter abbreviated as MPC) 201.

The MPC 201 sets the start address of a specific microprogram at the start of the instruction execution process based on the instruction decoding result of the DU 102, and 1) a branch field instruction is executed and branches 2) EU 10
3 or another unit requests waiting for execution of a microinstruction and is temporarily stopped, the value is incremented by 1 every other clock.

The micro instruction read from the MROM 202 is stored in the micro instruction register (hereinafter abbreviated as MR) 20.
Latched to 4.

In the data bus section (the lower part of the drawing) for actually executing the execution processing, 32 32-bit general-purpose registers (hereinafter abbreviated as GR) 210 and a 32-bit wide arithmetic logic unit (hereinafter abbreviated as ALU) are provided. 211, a 32-bit width shift operation device (hereinafter abbreviated as SHIFT) 220 and the like. Further, a configuration having a multiplier and a floating point arithmetic unit can be considered.

Each resource in the data path is coupled via three 32-bit buses s1_bus2_bus, r_bus. s1_bus and s2_bus are GR210
Read the contents of ALU211 or SHIFT22
0 is a data bus for transferring two operation data to 0, and the same or different GR2 at the same time.
10 contents can be transferred.

R_bus is ALU211 or SHIF
It is a data bus used for data transfer for reading the operation result performed in T220 and writing it back to GR210.

S1_bus is the operand in the BU 105 that stores the read operand issued from the data bus terminal 122 as a result of the read bus cycle issuance.
It is also coupled to a read register (hereinafter abbreviated as OPR) 213, and the contents of OPR 213 can be used as an operand to be operated instead of GR 210.

Similarly, r_bus is also coupled to an operand write register (hereinafter abbreviated as OPW) 214 in the BU 105 which stores a write operand output from the data bus terminal 122 at the time of issuing a write bus cycle. , GR210, the contents of OPR213 can be used as the write destination of the operation result.

A register resource read to s1_bus and a register resource to which data on s1_bus is written are designated by an s1_bus decoder (hereinafter abbreviated as S1DEC) 207. Similarly, for s2_bus, s2_bus decoder (hereinafter abbreviated as S2DEC)
208 and r_bus are designated by an r_bus decoder (hereinafter abbreviated as RDEC) 209. rtrn
A delay circuit (hereinafter abbreviated as MD) 206 is connected to the input of the RDEC 209 so that data transfer using r_bus by the field is enabled after one clock for s1trn and s2trn of the same microinstruction.

The microinstruction 203 read from the MROM 202 includes 1) s1trn field for specifying the first operand transfer using s1_bus, and 2) s2_.
s2t that specifies the second operand transfer using bus
rn field, 3) rtrn field that specifies result transfer using r_bus, 4) op field that generates signals related to branch, operation, and control field instructions, 5) opc field that specifies the role of the op field, 6) It is composed of a branch destination address of a branch instruction or a simm field for generating a constant used in the first / second operand.

The function represented by the opc and op fields is called a field instruction for convenience, and is classified into field instructions such as branch, operation, and control.

Each transfer field of s1trn, s2trn, and rtrn includes subfields for specifying register resources of a transfer source (source) and a transfer destination (destination). As described above, the contents of the register resource specified by the source subfield are read onto each data bus, and at the same time, the value on each data bus is written into the register resource specified by the destination subfield. To transfer.

The value of each field is s1_bu.
Decoder S1 corresponding to s, s2_bus, r_bus
Analyzed by DEC 207, S2 DEC 208, RDEC 209 to generate read and write signals for register resources on each data bus.

As shown in FIG. 9 which shows the classification of field instructions and the assignment of op fields by opc fields, the role of the op field is different for each field instruction. (1) The branch field instruction transfers the control of the micro instruction to the designated address (branch destination address) if the branch condition designated by "cccc" is the value (true or false) designated by "f". .

The branch destination addresses are "aaa" and si
It is specified by concatenating the values in the mm field, and MPC201
The new instruction sequence of micro instruction is set to MR
It is read from the OM 202.

"D" is the MROM until a new instruction sequence is read by executing the branch field instruction.
Specifies to enable / disable the execution of the microinstruction following the branch field instruction read from 202.
By enabling it, a "delayed branch" function that can execute a branch field instruction without invalidating the execution of microinstructions is realized. (2) The control field instruction generates a control signal designated by "nnnnnn". (3) The ALU operation field instruction specifies the operation in the ALU 211.

"Oooooo" is the type of operation (ex. Addition / subtraction / comparison / logical sum / logical product / exclusive logical sum / logical negation), and "tttt" is the data type of the operation (ex.
8/16/32 bits), "i" indicates the type of operation is "oo"
Direct operation specified by "oooo" or indirect operation specified based on the instruction decoding result of the DU 102 is specified.
"Ss" and "dd" specify two operand data used for the operation. Although not shown in the drawing, the target of calculation in the ALU 211 is s1_bus, s2_b.
Of the four temporary registers connected to us,
Two are used.

A specified by the ALU operation field instruction
The LU operation is held until the next ALU operation field instruction is executed, and the ALU 211 repeats the operation according to the latest designation. (4) The shifter operation field instruction is SHIFT22
Specifies the operation at 0. “OOO” indicates the type of operation (right logical shift / left logical shift / right arithmetic shift)
"W" is the number of bits to shift in EU103
U103 Specifies whether to obtain from outside.

Each field command is analyzed and controlled by a field command decoder (hereinafter abbreviated as MDEC) 205 which decodes the values of the opc and op fields.

The SHIFT 220 has the following auxiliary registers.

A shift operation register (hereinafter abbreviated as SOPR) 221 is a register that holds the type of shift operation performed by SHIFT 220, and latches "ooo" when a shifter operation field instruction is executed.

A shift bit number register (abbreviated as SB hereinafter) 222 is a register in which "w" holds the shift bit number, and "w" indicates the shift bit number in the EU 103 when the shifter operation field instruction is executed. The SHIFT 220 is notified when it is specified to obtain from the.

FIG. 3 shows the SHIFT 220 and the SHI.
6 is a drawing showing in more detail the configuration related to control of the FT 220.

The shifter operation is performed by an input register (hereinafter abbreviated as SHIFTI) 22 connected to the input of the SHIFT 220.
4 is shifted to the left or right by the number of bits of arbitrary length up to 32 bits held in 4, and output register (hereinafter referred to as SHIF
32 bits of data are obtained at 226. Barrel shifter body (hereinafter abbreviated as BSHIFT)
A shifter 225 shifts the 32-bit data stored in the SHIFTI 224 by 1) logical right shift (SHR), 2) logical left shift (SHL), 3) arithmetic right shift (SAR), and half clock period. BSHIFT22
5 types of shifter operation are 3-bit operation designation signal OP
The designation of R and the number of shift bits is added by a bit number designation signal BITS of 6 bits.

The data setting to SHIFTI 224 is s
By describing "SFTI" in the destination subfield of the 1trn field or the s2trn field (in this case, the S1DEC 207 generates the decode signal SHIFTIWSI or the S2DEC208
Generates a decode signal SHIFTIWS2), s1
_Bus or s2_bus.

To read the operation result from the SHIFTO 226, describe "SFTO" in the source subfield of the rtrn field (in this case, RDEC2
09 generates a decode signal SHIFTORR), S
The contents of HIFTO 226 are tristate buffer 2
It is read to rtrn via 27.

The OPR signal is an opr signal when the MSSHIFT signal is generated by the opc field decoder (hereinafter abbreviated as OPCDEC) 215 detecting that the shifter operation field instruction is designated in the opc field.
Supplied from SOPR 221 which latches the value of the field. The OPR signal is "o" of the shifter operation field instruction.
A portion corresponding to "oo" is supplied.

The portion corresponding to "w" of the shifter operation field instruction latched by the SOPR 221 is MPS.
An input of a multiplexer (hereinafter abbreviated as SBMPX) 223 is selected as the EL signal.

MPSEL signal is 0b (when the shift bit number is specified to be obtained in EU 103) B
Select the output SBB signal of SB222 to ITS and output 1
In the case of b (when the shift bit number is specified to be obtained by other than the EU 103), the output ALB signal of the align bit generation circuit (hereinafter abbreviated as ALBGEN) 228 is selectively output.

The input of SB222 is connected to s2_bus, and "SFTB" is described in the destination subfield of the s2trn field (in this case, S2DEC 208 generates the decode signal SBWS2), and the value of s2_bus (lower 6 bits) ) Is set.

As described above, in order to perform the shift operation once, 1) the setting of SHIFTI 220 (s1tr
n / s2trn field specification), 2) shifter operation type specification by OPR signal (shifter operation field instruction specification), 3) shift bit number specification by BITS signal, 4) operation result read (rtrn field specification) ), Each step is required.

The operation of SHIFT 220 will be described by taking as an example a microprocessor that processes each shift instruction of logical right shift / logical left shift / arithmetic right shift.

Each of the logical right shift instruction, the logical left shift instruction, and the arithmetic right shift instruction can be described by a one-line microinstruction as follows.

SFTI = DST; SFTB = BITS;
SHR / SHL / SAR (W); DST = SFTOf;
ENDM; “;” is a description for separating each field. From left, s1trn field, s2t
rn field, opc and op field, rtr
Corresponds to n fields. Rightmost field ("END
The meaning of M; ") will be described later.

Each field has the following meanings of operation designation from the left. SFTI = DST: s1 is the content of the register resource that designates the shifted data represented by DST.
Transfer to SHIFTI 224 via _bus. SFTB = BITS: s is the content of the register resource that specifies the number of shift bits represented by BITS
Transfer to SB 222 via 2_bus. SHR / SHL / SAR (W): SH as shifter operation
R, SHL or SAR is specified in the SOPR 221, and the value set in the SB 222 is used as the number of shift bits (the description of "(W)" makes the "w" portion 0b). DST / SFTOf: The output of SHIFTO 226 (shifter operation result) is DST via r_bus.
Transfer to the register resource represented by (the same as the resource storing the shifted data).

Since f is added to "SFTO", the shifter operation result is not shown in the drawing.
It is specified to change the status flag of (Processor Status Word). ENDM: Means that the microprogram ends with this microinstruction.

Using the timing chart shown in FIG.
The description of this microprogram will be described.

The row of "pipeline operation" indicates the order of the pipeline processing of the microprocessor 100. The microprocessor 100 has the following basic pipeline stages. The AL and WB stages perform processing in a half clock, and the others perform processing in one clock. IF (Instruction Fetch): An instruction code of 16/32 bit length is fetched from the IU 101. AL (Instruction Align): With the output of IU101,
Align the LSB positions of the 16 / 32-bit mixed instruction code. ID (Instruction Decode): The DU 102 decodes the instruction code and generates various signals. MA (micro instruction access): Based on the decoding result of the ID stage, the MPC 201 is initialized and the MROM
Access 202. MI (Micro instruction execution): The output of the MROM 202 is latched in the MR 204. It generates a simple control signal in the EU 103, sets a control register, and branches. EX (execution of instruction): Calculation and internal data transfer are executed by the EU 103. The first half clock is s1_b
Between each register resource using us, s2_bus /
Handles the data transfer to the computing device. In the latter half of the half clock, the calculation by the calculation device is performed. WB (result return): Data (result) is transferred from the arithmetic unit using r_bus to each register resource.

Further, the following pipeline stages are described in FIGS. 6 and 7 which will be described later, which will be described first. EA (effective address): AU104 is a memory
The operand address is calculated and notified to the BU 105. The operand address is obtained by adding the displacement value included in the instruction code to the value (base value) of the general-purpose register specified by the instruction code. The present stage starts from the latter half clock of the ID stage by detecting the LOAD and STORE instructions.

As can be seen from FIG. 5, the pipeline processing of the shift instruction is IF → AL → ID → MA → MI → EX.
→ It consists of WB stage.

SHR / SHL / SAR at MI stage
In the (W) field instruction, it is OPDEC2 that the micro instruction latched by the MR 204 is a shifter operation instruction.
When "15" is detected by 15, and the MSSHIFT signal is generated, "ooo" and "w" are latched in the SOPR 221. For BSHIFT 225, "o" of OPR221
The output OPR of the part where "oo" is latched is notified, and SH
R, SHL or SAR is specified.

The transfer field instruction described in the s1trn field is transferred by the S1DEC 207 to SHIFTW.
The S1 signal is generated, and the value of s1_bus in which the content of the register resource holding the shifted operand described in DST is output is latched in SHIFTI 224.

In the transfer field instruction described in the s2trn field, the SBWS2 signal is generated by the S2DEC 208, and the content of the register resource holding the shift bit number described in BITS is output s2_b.
The value of us is latched in SBB222.

The output MPSEL of the portion latching "w" held in the SOPR 221 becomes 0b because the shifter operation instruction describes "(W)", and SBMPX
The output SB of the SB 222 is output to the output BITS of 223 and is notified to the BSHIFT 225.

SH which is the operation input of BSHIFT 225
When the IFTI 224 and the BITS and OPR signals to be the control inputs are determined, the BSHIFT 225 is a half clock and SH
The shifter operation designated by the OPR signal is performed on the data held in the IFTI 224 by the number of bits designated by the BITS signal, and the result is latched in the SHIFTO 226.

The transfer field instruction described in the rtrn field is S by the RDEC 209 at the WB stage.
A HIFTOR signal is generated, the contents of SHIFTO 226 are read from the tri-state buffer 227 into r_bus, and the contents of the register resource holding the shifted operand described in DST are rewritten. At the same time, although omitted in the drawing, the circuit for analyzing the state of the shift result analyzes the overflow, the overflow, and the state of the code, and updates the contents of the PSW.

Next, regarding the LOAD instruction, the following microprogram described in one line for processing the LOAD instruction is taken as an example, and S
The operation of the HIFT 220 will be described.

SFTI = OPR; SAR (A); DST
= SFTO; ENDM; Each field has the following meanings of operation designation from the left. SFTI = OPR: Transfer the contents of the OPR 213 storing the read memory operand to the SHIFTI 224 via s1_bus. SAR (A): SO is used as shifter operation
Specified in PR221, ALBG as the number of shift bits
The value generated in EN 228 is used (the description of “(A)” makes the “w” part 1b). DST = SFTO: The output of the SHIFTO 226 (shifter operation result) is transferred to the register resource represented by DST via r_bus. ENDM: Means that the microprogram ends with this microinstruction.

Using the timing chart shown in FIG. 6,
The description of this microprogram will be described. As can be seen from the drawing, the pipeline processing of the LOAD instruction is
It has AL, ID, MA, MI, EX, and WB stages, and the EA stage and execution are waited for (E
X) It is characterized by having a stage.

The AU 104 operates the operand at the EA stage.
Address (32-bit internal address IA0-IA3
When 1) is calculated, a bus cycle (memory read) is activated for the BU 105. Bus cycle is T
1, T2 state, and the value of the data bus terminal 122 is latched in the OPR 213 at the end of the T2 state.

As shown in the drawing, two EX stages ("(EX)") are queued because the activated read bus cycle does not end. In addition, REA indicating that the bus cycle may be ended in the EX stage
The state of the DY (-) 127 terminal input (ready state) is monitored, and control is performed so as not to transition to the WB stace unless it is in the ready state.

In the MI stage, the SAR (A) field instruction detects that the micro instruction latched in the MR 204 is a shifter operation instruction by the OPDEC 215 and generates the MSSHIFT signal, so that "oo" and "w" are SOPR221. Latched on. BSHI
The FT 225 is notified of the output OPR of the portion where “ooo” of the OPR 221 is latched, and the SAR is designated.

The transfer field instruction described in the s1trn field is transferred by the S1DEC 207 to SHIFTW.
S1 signal is generated and the contents of OPR213 are s1_bus
Attempt to latch into SHIFTI 224 via. Although not shown in the drawing, when the BU 105 is notified that the read bus cycle has not ended, the EU 105
3 detects the description (“= OPR”) of the transfer field instruction that tries to access the OPR 213, and controls the execution of the micro instruction so as to wait for the execution of the EX stage.

The output MPSEL of the portion latching "w" held in the SOPR 221 becomes 1b because the shifter operation instruction describes "(A)", and SBMPX.
223 output BITS to ALBGEN 228 output A
LB is output and notified to BSHIFT 225.

SH which is the operation input of BSHIFT 225
When the IFTI 224 is determined by the end of the read bus cycle and the BITS and OPR signals to be the control inputs are determined, the BSHIFT 225 is a half clock and the SHIFT
SAR operation is performed on the data held in 224
S signal is output for the specified number of bits, and the result is SHIF
Latched to TO226.

The transfer field instruction described in the rtrn field is SH by the WB stage RDEC209.
The IFTORR signal is generated, the contents of SHIFTO 226 are read from the tri-state buffer 227 to r_bus, and the contents of the register resource to which the memory operand described by DST is to be transferred are rewritten.

The operation of ALBGEN 228 will be described below.

When the instruction decoding is completed in the ID stage, it is possible to determine whether the instruction to be executed hereafter uses the memory operand and the data type of the operand. DTYP0-DTY01 signals are IU10
2 indicates the data type of the detected operand, 00
b means 8 bits, 01b means 16 bits, and 1Xb means 32 bits.

On the other hand, when the calculation of the internal address is completed in the EA stage, the least significant 2 bits (IA0-IA1) of the internal address are calculated.
Is also determined and ALBGEN 228 is notified.

In order to realize the data align function (memory → general-purpose register) by using the SAR operation in the SHIFT220, the right shift for the number of bits shown in FIG. 6 (3) is performed according to the data type and the internal address. Just go.

The reason why the SAR is used instead of the SHL for the right shift is to sign-extend the transfer from the memory to the general-purpose register, and other microprocessors use the SHL for the zero-extension. It is also possible.

6-bit wide ALB (ALB (0) to AL
B (5)) can be calculated by the following simple logical expression: ALB (5) = 0b; ALB (4) = IA1 * DTYP1 ′; ALB (3) = IA0 * DTYP1 ′ * DTYP0 ′; ALB (2) = 0b; ALB (1) = 0b; ALB (0) = 0b; In this expression, the expressions "DTYP0 '" and "DTYP1" are logical inversions of DTYP0 and DTYP, respectively.

Next, regarding the STORE instruction, taking the following microprogram described in one line for processing this as an example,
The operation of SHIFT 220 will be described. SHIFT220
In order to realize the data align function (general-purpose register → memory) by using the SAR operation, the left shift for the number of bits shown in FIG. 10 may be performed according to the data type and the internal address.

SFTI = SRC; SHL (A); OPW
= SFTO; ENDM; Each field has the following action specification from the left. SFTI = SRC: The contents of the register resource represented by SRC are transferred to SHIFTI 224 via s1 bus.
Transfer to. SHL (A): SHL is SO as shifter operation
Specified in PR221, ALBG as the number of shift bits
The value generated in EN 228 is used (the description of “(A)” makes the “w” part 1b). OPW = SFTO: The output of the SHIFTO 226 (shifter operation result) is transferred to the OPW 214 via r_bus. ENDM: Means that the microprogram ends with this microinstruction.

Using the timing chart shown in FIG. 7,
The description of this microprogram will be described. As can be seen from the drawing, the pipeline processing of the STORE instruction is
The feature is that it has an EA stage as well as an AL → ID → MA → MI → EX → WB stage.

The AU 104 operates as an operand at the EA stage.
Address (32-bit internal address IA0-IA3
Immediately after calculating 1), the bus
Cycle (memory write) is not activated. Processing is W
When proceeding to the B stage, the write bus cycle consisting of the states T1 and T2 is activated, and the contents of OPW 214 are output to the data bus terminal 122.

In the MI stage, in the SHL (A) field instruction, the OPEEDC 215 detects that the micro instruction latched by the MR 204 is a shifter operation instruction and generates an MSSHIFT signal, so that "oo" and "w" are SOPR221. Latched on. BSHI
The FT 225 is notified of the output OPR of the portion of the OPR 221 where "ooo" is latched, and SHL is designated.

The transfer field command described in the s1trn field is transferred to the SHIFTW by the S1DEC 207.
S1 signal is generated and the contents of the register resource represented by SRC which is to be transferred as a memory operand is s1
Latch to SHIFTI 224 via bus.

The output MPSEL of the portion latching "w" held in the SOPR 221 becomes 1b because the shifter operation instruction describes "(A)", and SBMPX.
223 output BITS to ALBGEN 228 output A
LB is output and notified to BSHIFT 225.

SH which is the operation input of BSHIFT 225
When the IFTI 224 and the BITS and OPR signals to be the control inputs are determined, the BSHIFT 225 is a half clock and SH
The data held in the IFTI 224 is subjected to SHL calculation by the number of bits designated by the BITS signal, and the result is latched in the SHIFTO 226.

The transfer field instruction described in the rtrn field is S by the RDEC 209 at the WB stage.
A HIFTORR signal is generated, the contents of SHIFTO 226 are read from tristate buffer 227 into r_bus, and transferred to OPW 214.

Here, the operation of ALBGEN 228 is the same as that shown in FIG. 10 like the LOAD instruction.

[0123]

As described above, by using the shifter for executing the shift instruction, the data align function required for the LOAD instruction and the STORE instruction can be easily realized.

The function of the shifter used for the shift instruction and the function of the shifter required to realize the data align function can be shared by almost the same hardware. Therefore, by using the present invention, it is possible to realize a microprocessor that does not require dedicated hardware for the data align function.

In the present invention, the functions necessary only for realizing the data align function are 1) a function for calculating the number of shift bits to be notified to the shifter, and 2) the shift
Only the shifter operation function using the number of bits
It can be easily understood that the overhead for realizing the align function is small.

Further, since the normal data path for the normal instruction execution processing is used, it is possible to avoid the reduction of the operation speed for the data align processing.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of a microprocessor using the present invention.

FIG. 2 is a diagram showing a configuration of an instruction execution unit in FIG.

FIG. 3 is a diagram showing a configuration of a shifter in FIG. 2 and its peripherals.

FIG. 4 is a diagram showing a connection between a conventional microprocessor and an external memory.

FIG. 5 is a diagram showing an operation timing of a shift instruction in the embodiment.

FIG. 6 is a diagram showing an operation timing of a LOAD instruction in the embodiment.

FIG. 7 is a diagram showing an operation timing of a STORE instruction in the embodiment.

FIG. 8 is a diagram showing an access operation of the memory bank in FIG.

FIG. 9 is a diagram showing a format of a field instruction in the embodiment.

FIG. 10 is a diagram showing the logic of the align bit generation circuit in the embodiment.

Claims (3)

[Claims] 1. An internal data bus for transferring data when an instruction is executed in a data aligning device of a microprocessor for transferring data having a bit length smaller than a bit length of a data bus width to an external memory, the internal data bus. A shift arithmetic unit connected to the data bus, and means for generating the number of bits to be aligned according to a part of the address to the external memory to be accessed and the bit length of the data are generated by the bit number generating means. A data aligning device, wherein the data transferred via the data bus is shifted by the shift operation device according to the number of bits. 2. The data aligning apparatus according to claim 1, further comprising a means for storing a microprogram, and a microprogram control means, and the microprogram stored in the storage means is executed by the control means to execute an instruction. And a data aligning device for controlling the shift operation. 3. The data aligning device according to claim 2, further comprising at least three sets of internal data buses, and performing independent three sets of data transfer at the same time.