JPH05282198A - Dma transfer system - Google Patents

Abstract

PURPOSE:To guarantee the accurate execution of direct memory access (DMA) transfer operation setting up a high speed memory in a shared memory space as a transferred destination or a transferring source when a part of the memory space for the high speed memory and a low speed memory is shared. CONSTITUTION:A central processing unit(CPU) 1 is provided with the high speed memory 1c in order to attain rapid processing and the memory space of the memory 1c is allocated as a partial memory space in the memory space of low speed memories 30b, 31b to guarantee the continuity of the memory space. In the case of starting the high speed memory 1c by a DMA controller at the time of DMA transfer in which the transferred destination/transferring source is the memory 1c, only the memory 1c is started by respective memory control circuits 1b, 30a, 31a and the start of the low speed memories 30b, 31b having the same memory space as that allocated to the memory 1c is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct Mem) in an information processing apparatus having a high speed memory and a low speed memory.
The ory access) transfer method can be applied to, for example, a private branch exchange.

[0002]

2. Description of the Related Art As a conventional information processing apparatus in which a central processing unit, a main storage unit, a file control unit, etc. are connected to a common processor bus, there is a high speed memory and a low speed memory in which memories having different access times are mixed. .. For example, by storing the most frequently accessed programs and data in a high-speed memory provided in the central processing unit and storing general programs and data in a low-speed memory in the main storage device, There is an information processing device that realizes high-speed processing.

Conventionally, the structure of the memory space in this type of information processing apparatus has been such that the memory space of the high speed memory and the memory space of the low speed memory in the main storage device are divided. By dividing the memory space of the memories having different speeds as described above, various DMA transfers can be performed without requiring a complicated circuit for adjusting the memory space and without imposing various restrictions. It was That is,
The types of DMA transfer include transfer between an external input / output device such as a file controller and a high speed memory, transfer between an external input / output device and a low speed memory, transfer between a high speed memory and a low speed memory,
There is transfer in the high-speed memory space, but any DMA
Regarding the transfer, since the memory space of the memories having different speeds was divided, the DMA transfer could be easily performed by a simple circuit.

[0004]

By the way, an information processing apparatus has been proposed in which the continuity of the memory space is guaranteed so that the microprocessor in the central processing unit can access the high speed memory and the low speed memory similarly. .. In such a device, the memory space of the high-speed memory can be changed to the low-speed memory without classifying (for example, banking) the main recording device composed of a plurality of boards and without changing the software structure. There is a device which is allocated as a part of the memory space in the memory space of the main recording device to which it belongs. In this case, as shown in FIG. 2, an address (for example, 00
000000-0003FFFF) becomes equal to the address of the memory space of the high speed memory, and the memory space having the same address of the low speed memory is not actually used. This is actually done when the memory space of the main memory is much larger than the memory space of the high speed memory.

Therefore, in such a device, the memory space having the same address is addressed when the high speed memory is accessed. However,
When trying to access the high-speed memory, it cannot be guaranteed that the high-speed memory operates normally because the low-speed memory portion of the memory space having the same address exists.

When the microprocessor in the central processing unit accesses the high speed memory, by controlling the state of the low speed memory through various control signals, the above-mentioned inconvenience can be avoided. When trying to access the memory (during DMA transfer), the above-mentioned inconvenience occurred.

In consideration of such inconvenience, the capacity of the high speed memory or the like may be limited.

The present invention has been made in consideration of the above points, and when a part of the memory space of the high speed memory and the memory space of the low speed memory in the main memory exists in the same memory space, It is intended to provide a DMA transfer method capable of guaranteeing normal operability of an access operation at the time of DMA transfer including a high-speed memory existing in the above in a transfer destination or a transfer source.

[0009]

In order to solve such a problem, according to the present invention, a high-speed memory, a low-speed memory in which the memory space of this high-speed memory is the same as a part of its own memory space, and a DMA controller are provided. In a DMA transfer method in which at least one of a transfer destination and a transfer source is a high-speed memory in an information processing apparatus including at least
The following circuits are provided.

That is, a memory control circuit for a high-speed memory that outputs a memory cancel signal when the DMA controller determines that an access operation has started for a memory space shared by a high-speed memory and a low-speed memory, and a high-speed memory For a low-speed memory that suppresses activation to the low-speed memory when a memory cancel signal is given even if the DMA controller determines that the access operation has started for the memory space shared by the memory and the low-speed memory Memory control circuit.

[0011]

When the high-speed memory and the low-speed memory that makes the memory space of the high-speed memory the same as a part of its own memory space are provided, the high-speed memory can be used for the memory space shared by both memories. Is assumed to be valid. No problems occur when the microprocessor accesses the shared space. The present invention defines the case where the DMA controller accesses the shared space.

In the present invention, the memory control circuit for the high speed memory sends the memory cancel signal to the low speed by judging that the DMA controller has started the access operation to the memory space shared by the high speed memory and the low speed memory. Output to the memory control circuit for memory. Even if the DMA controller determines that the access operation has started for the memory space shared by the high-speed memory and the low-speed memory, the memory control circuit for the low-speed memory operates at a low speed because the memory cancel signal is given. Suppress startup to memory.

In this way, it is possible to accurately execute the DMA transfer in which at least one of the transfer destination and the transfer source is a high speed memory.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. Here, FIG. 1 is an explanatory view of this embodiment, FIG. 1 (A) is a block diagram showing the configuration, and FIG. 1 (B1).
(B4) is a timing chart of each part during the DMA transfer operation.

As shown in FIG. 1A, the information processing apparatus employing the DMA transfer system according to this embodiment has a central processing unit 1, a file control unit 2 and a main storage unit 30 composed of a plurality of boards. , 31, ... Are processor buses (composed of a data bus, an address bus, and a control bus) 4
And a memory cancel signal line 5 which will be described later.

For example, the high-speed memory 1c for storing the most frequently accessed programs and data is provided in the central processing unit 1 in which the microprocessor 1a is provided together with the high-speed memory control circuit 1b which is the control circuit thereof. ing. On the other hand, the low-speed memories 30b, 31b, ... In which general programs, data, etc. are stored are distributed to a plurality of main storage devices 30, 31, ... Together with the low-speed memory control circuits 30a, 31a ,. Are provided.

Also in this embodiment, the memory space of the high speed memory 1c is allocated as a part of the memory space of the low speed memories 30b, 31b, ... (See FIG. 2). That is, the memory area having an address equal to the address of the high speed memory 1c is the low speed memory 30b, 31b, ...
Always exists.

The file controller 2 includes a high speed memory 1c.
And a file device 2c for storing files to be loaded into the low speed memories 30b, 31b, ..., For example, processed files transferred from the high speed memory 1c and the low speed memories 30b, 31b ,. A file control circuit 2b for controlling the file device 2c is also provided. The file controller 2 is provided with a DMA controller 2a so as to execute the above-mentioned data transfer at high speed. In the case of this embodiment, the DMA controller 2a transfers data between the file device 2c and the high speed memory 1c, and the file device 2c and the low speed memory 30b, 3b.
Not only the data transfer with 1b, ...
Controls data transfer in the memory spaces b, 31b, ..., Data transfer in the memory space of the high speed memory 1c, and data transfer between the high speed memory 1c and the low speed memories 30b, 31b ,. ing.

Thus, in addition to the data transfer under the control of the microprocessor 1a, the data transfer under the control of the DMA controller 2a is also possible. Therefore, in this embodiment, although not shown, the microprocessor 1a and A bus arbitration circuit that determines which of the DMA controllers 2a is given the bus use right is provided. That is, the right to use the processor bus 4 is acquired by either the microprocessor 1a or the DMA controller 2a,
The microprocessor 1a and the DMA controller 2a never access the processor bus 4 at the same time.

Further, the high speed memory control circuit 1b and the low speed memory control circuits 30a, 31a, ... Are respectively provided with memory cancel control units 1b1, 30a1, 31a1 ,. The memory spaces of the low speed memories 30b, 31b, ... Having the same address are prevented from being accessed. The memory cancel signal line 5 is provided as a signal line for the memory cancel signal transmitted and received at this time.
Are connected to the respective memory control circuits 1b, 30a, 31a, ....

Next, the operation of the information processing apparatus having the above configuration, particularly the operation involving the access to the high speed memory 1c will be described.

In the case of this embodiment, both the microprocessor 1a and the DMA controller 2a are connected to the high speed memory 1c.
The memory space of the low speed memories 30b, 31b, ... Having the same address as the memory space of the memory space is not executed. That is, the access to the address will be explained as an access to the high speed memory 1c.

First, the operation when the microprocessor 1a occupies the right to use the processor bus 4 to access the high speed memory 1c will be described. In this case, the microprocessor 1a suppresses the strobe signals of various buses existing on the processor bus 4, and the low speed memories 30b and 31 existing in the same memory space as the high speed memory 1c.
b .... is suppressed. Thus, high speed memory 1c
, It is possible to prevent the memory space of the low speed memories 30b, 31b, ... Of the same address as that from accessing.

Next, the operation when the DMA controller 2a occupies the right to use the processor bus 4 and when at least one of the transfer destination and the transfer source is the high-speed memory 1c will be described with reference to FIGS. Description will be made also using the timing chart shown in B4).

The DMA controller 2a is the high speed memory 1
In order to access c, first, the high speed memory 1c
The address signal ADD of the memory space in which is present is output to the processor bus 4 (see FIG. 1B1). At this time,
The high-speed memory control circuit 1b expands this address signal ADD, recognizes that the high-speed memory 1c under its control is selected, and validates the selection signal SEL indicating that the high-speed memory 1c has been selected. (See FIG. 1B3). At this time, the low-speed memory control circuits 30a, 31a,
Similarly, the address signal ADD is expanded, and when the address signal ADD is applicable, it is recognized that the low-speed memory 30b or 31b under its control is selected, and the control is similarly performed. A selection signal (not shown) in the circuit is validated.

The DMA controller 2a surely determines the address signal ADD after the elapse of a predetermined time (a time sufficiently longer than the time for converting the selection signal SEL to valid) from the time when the address signal ADD is transmitted. Is output to the processor bus 4 (see FIG. 1B2).

The high speed memory control circuit 1b receives the selection signal SE.
When it is determined that L is valid and the strobe signal STB is valid, the high speed memory 1c is activated and
Low-speed memory 30b or 31 existing in the same memory space
The memory cancel signal MC is output to the memory cancel signal line 5 in order to suppress the activation of b ...
(See (B4)).

On the other hand, in the low-speed memory control circuit 30a or 31a, ... Having the low-speed memory 30b or 31b, ... In the memory space designated by the address signal ADD, the selection signal inside the self-control circuit is valid and the strobe signal STB is When it is determined that it is valid, the low-speed memory 30b or 3
1b, ... Start preparation for starting, but at this time, since the memory cancel signal MC from the memory cancel signal line 5 becomes valid, starting to the low speed memory 30b or 31b ,.

In this way, the DMA controller 2a
Only the high-speed memory 1c can be activated when activating the DMA transfer by. In the case of this embodiment,
The DMA controller 2a not only transfers data between the file device 2c and the high-speed memory 1c, transfers data between the file device 2c and the low-speed memories 30b, 31b, ..., but also within the memory space of the low-speed memories 30b, 31b ,. The data transfer, the data transfer within the memory space of the high speed memory 1c, and the data transfer between the high speed memory 1c and the low speed memories 30b, 31b, ... Are also controlled.
The operations shown in (B1) to (B4) are performed by the file device 2c.
Between the high speed memory 1c and the high speed memory 1c, in the memory space of the high speed memory 1c, and between the high speed memory 1c and the low speed memories 30b, 31b ,.

High-speed memory 1 activated as described above
c is deactivated as follows. The DMA controller 2a receives the strobe signal STB of the processor bus 4 when the access operation to the high speed memory 1c is completed.
Disable. The high-speed memory control circuit 1b recognizes that the strobe signal STB has become invalid, and the high-speed memory 1b
At the same time as ending the activation of c, the memory cancel signal MC of the memory cancel signal line 5 is invalidated. The DMA controller 2a uses the processor bus 4 when a sufficient period has elapsed since the strobe signal STB was invalidated.
Of the address signal ADD is uncertain, and the high speed memory control circuit 1b invalidates the selection signal SEL at this time.

Therefore, according to the above-described embodiment, in the device having the continuity of the memory space of the high-speed memory and the low-speed memory in the main memory, that is, in the device in which a part of the memory space is shared, the transfer destination or the transfer source is It is possible to accurately execute a DMA transfer, at least one of which is a high-speed memory.

The continuity of the memory space between the high-speed memory and the low-speed memory in the main storage device becomes significant only after the correct operation of the DMA transfer can be guaranteed. That is, high-speed processing can be realized without being allocated to the memory space of the high-speed memory or the capacity of the memory chip, without classifying a plurality of main storage devices, and without changing the software structure. You can

The file control device in the above embodiment also means an input / output control device and the like.

Although not directly related to the present invention, an operation similar to the operation characteristic of the present invention may be performed in the following cases. Even if the memory write protection area for the main memory is allocated and the write operation occurs in this write protected area, the memory cancel signal as described above is enabled to suppress the memory write operation to the main memory. Alternatively, the contents of the low speed memory in the main storage device may be protected.

[0035]

As described above, according to the present invention, DM with a memory space shared by a high speed memory and a low speed memory is used.
Since only the high speed memory is activated at the time of the A transfer and the activation of the low speed memory is suppressed, the normal operability of the access operation at the time of the DMA transfer including the high speed memory as the transfer destination and / or the transfer source can be guaranteed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a DMA transfer system according to an embodiment, FIG. 1 (A) is a block diagram of an apparatus adopting the embodiment system, and FIGS. 1 (B1) to (B4) are timing charts of respective parts thereof. ..

FIG. 2 is an explanatory diagram of memory space allocation as a premise of the present invention.

[Explanation of symbols]

1 ... Central processing unit, 1a ... Microprocessor, 1b ...
High-speed memory control circuit, 1c ... High-speed memory, 2 ... File control device, 2a ... DMA controller, 2b ... File control circuit, 2c ... File device, 4 ... Processor bus,
5 ... Memory cancel signal line, 30, 31 ... Main storage device, 30a, 31a ... Low speed memory control circuit, 30b, 3
1b ... low speed memory.

Claims (1)

[Claims] 1. A transfer destination or a transfer source in an information processing apparatus comprising at least a high-speed memory, a low-speed memory in which the memory space of this high-speed memory is made part of its own memory space, and a DMA controller. In a DMA transfer method in which at least one is a high-speed memory, for a high-speed memory, the DMA controller judges that an access operation has started for the memory space shared by the high-speed memory and the low-speed memory and outputs a memory cancel signal. Even if the DMA controller determines that the access operation has started to the memory space shared by the memory control circuit of the above and the high speed memory and the low speed memory, the low speed memory is changed to the low speed memory when the above memory cancel signal is given. And a memory control circuit for a low-speed memory that suppresses the activation of the DMA Transmission system.