JPH0528406B2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a digital signal processing device.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of the digital signal processing device. In FIG. 2, 201 is a read-only memory program storage device (hereinafter referred to as program ROM), 202 is a read-only memory data storage device (hereinafter referred to as data ROM), and 203 is a random access memory device. - A memory data storage device (hereinafter referred to as RAM) 204 is an address counter of the program ROM 201, which is configured to sequentially count up by 1 if no next address designation command is input. 205 and 206 are address counter 2
04 save register, 207 multiplier, 208,
209 is an input register to the multiplier that stores data input to the multiplier 207; 210 is the multiplier 20;
This is an output register of a multiplier that stores the output of No. 7, that is, the multiplication result. 211 is a computing unit, 212, 2
Reference numeral 13 denotes a register that stores the calculation results of the calculation unit 211. A single-precision data bus 214 transfers data for executing various instructions. 21
5 is input data to the arithmetic unit 211, the arithmetic unit 211
Output data from, multiplication result storage register 210
A double-precision data bus for transferring data from Single precision data bus 214 and double precision data bus 215 are connected at connection point 216. 2
17 is a data register which is an interface section for parallel data input/output, 218 is a serial input register, and 219 is a serial output register.

In digital signal processing, the sum of products of data occupies a large weight. Therefore, in order to prevent deterioration of calculation accuracy, the data bus 215 has a bit length that allows the multiplication results to be transferred to the arithmetic unit 211 without being truncated. The bit length of the data bus 214 is the same as that of the data ROM 202 and RAM 203. For example, data ROM20
2. Set the bit length of RAM 203 to 16 bits (code 1).
bit, data 15 bits), data bus 2
14 is 16 bits. Also, 16-bit data
Multiplying 16 bits of data yields 31 bits of data (1 bit of code, 30 bits of data), so the bit length of data bus 215 is 31 bits. Further, the bit length of the arithmetic unit 211 is also 31 bits. In the format of data in a digital signal processing device, the most significant bit indicates a sign, and a decimal point usually exists between the most significant bit and the next lower bit. Therefore, at the connection point 216,
Data bus 214 is connected to the upper 16 bits of data bus 215. Also, a data register 217, which is an input/output interface with the outside,
The bit length of the serial input register 218 and the serial output register 219 is 16 bits, which is the same as that of the data bus 214, but the bit length of the actual input/output data can be changed programmably. This bit length is the data register 2
For parallel data handled by 17, the host
CPU bit length, serial input register 218,
Regarding serial data handled by serial output register 219, A/D, D/A converter and
It largely depends on the bit length of PCM and Codec.

Here, when transferring the data in the calculation result storage register 212 to another register, it is natural that the data bus 2
14, the lower 15 bits are truncated. Therefore, in order to prevent the error from increasing due to the truncation of the lower 15 bits, a rounding instruction is provided. Conventionally, the rounding instruction causes the arithmetic unit 211 to perform a rounding operation on the value one bit below the upper 16 bits. was.

[Problem that the invention seeks to solve]

The conventional rounding operation described above targets the numerical value one bit below the upper 16 bits in the arithmetic unit 211 in order to prevent data truncation errors caused by passing from the data bus 215 to the data bus 214 in FIG. , has the following drawbacks.

For example, if the upper 8 bits of the calculation result are to be output serially or in parallel, conventional rounding calculations are meaningless. Therefore, the program must be programmed so that the arithmetic unit 211 rounds the value one bit below the upper eight bits.

First, as an initial setting, go to an address in RAM.
Store the data 0080H. Rounding is then performed in the following steps.

Save the current RAM address pointer value to an empty register.

Transfer the address where 0080H is stored in the RAM address pointer.

The arithmetic unit performs addition of the target data and the data pointed to by the RAM address pointer.

The address saved in the empty register is restored to the RAM address pointer.

Although this is only an increase of 4 steps in one rounding process, there is a large amount of useless processing in the entire program. In other words, if there are limitations on processing time, program ROM, or RAM capacity, the performance of the system will deteriorate.

[Means for solving problems]

A digital signal processing device of the present invention includes a program storage device that stores a program including control instructions, an instruction decoder that converts the control instructions outputted from the program storage device into microcode and outputs the microcode, and a program storage device that stores a program including control instructions. , a multiplier, a first data bus with a single-precision word length, and a double-precision word that can directly handle the double-precision data from the multiplier in and around the arithmetic unit. In a digital signal processing device that adopts a long data bus and is equipped with a second data bus connected to the lower side of the first data bus, if the value one bit below the last bit to be left is 0, The last bit and the number series before it are used as the approximate number series, and if the number one bit below the last bit to be kept is 1, add 1 to the last bit and approximate the result. The present invention is characterized in that the arithmetic unit executes a rounding operation to an arbitrary bit length by performing an operation on arbitrary bits to convert the value into a numeric series.

[Example] Next, the present invention will be described with reference to the drawings.

FIG. 1 shows the periphery of the arithmetic unit and the periphery of external input/output. 1 is a 31-bit arithmetic unit. 2 is a rounding bit specification register that specifies the rounding bit, and its value is set by the microcode.
The bit length of register 2 depends on how many bits of valid data are required, but input/output data of 16 bits or less is usually 4 bits, 8 bits, 12 bits,
Since it is limited to 16 bits, 2 bits is sufficient.

The rounding bit operation using the value of register 2 is as follows. When the value of register 2 is 00B, arithmetic unit 1 performs a rounding operation on the value one bit below the upper 16 bits. At hardware reset, it becomes 00B. In other words, approximation is performed so that the number of effective bits is 16 bits. Register value is 01B
In this case, rounding is performed on the value one bit below the upper 12 bits. In other words, an approximation is made such that the number of effective bits is 12 bits. The register value is
When it is 10B, rounding is performed on the value one bit below the upper eight bits. When the register value is 11B, rounding is performed on the value 1 bit below the upper 4 bits. 3 is a 31-bit data bus. 4
is a 16-bit data bus. The 31-bit data bus 3 and the 16-bit data bus 4 are connected at a connection point 5. 6 is a data register which is an interface section for parallel data input/output, 7 is a serial input register, and 8 is a serial output register. Registers 9 and 10 are 31-bit registers for storing the operation results of the arithmetic unit 1.

Now PCM as serial interface
Codec (8bit) is connected, and the calculation result storage register 9 contains 0011 0111 1111 0011 0011 1111
The data 1111 110 B is stored, and if the upper 8 bits are to be output serially, it will be as follows. First, the microprogram sets the rounding bit specification register 2 to 10B. Next, a rounding operation is performed so that the number of effective bits becomes 8 bits. After the rounding operation, the result is 0011 1000 1111
0011 0011 1111 1111 110B and is stored in the calculation result storage register 9 again. The signal is then input to a 16-bit data bus 4 via a 31-bit data bus 3. Here the data is 0011 1000 1111 0011
B, and is input to the serial output register 8 as is. Here, only the upper 8 bits, i.e.
0011 1000 B is serially output.

Also, in the calculation result storage register 9, 0011 0111 0111
The data 0011 0011 1111 1111 110B is stored, and when the upper 8 bits are serially output, the result is as follows. First, the microprogram sets the rounding bit specification register 2 to 10B. If it has already been set, this part can be omitted. Next, a rounding operation is performed so that the number of effective bits becomes 8 bits. However, even after rounding, the result does not change: 0011 0111 1111 0011
0011 1111 1111 110B, and is stored in the calculation result storage register 9 again. The signal is then input to a 16-bit data bus 4 via a 31-bit data bus 3. Here, the data is 0011 0111 0111 0011B. Then, it is input to the serial output register 8 as is. Here, only the upper 8 bits, i.e.
0011 0111 B is serially output.

〔Effect of the invention〕

As explained above, by providing a 2-bit rounding bit specification register, the present invention makes it possible to perform rounding operations for 4-bit, 8-bit, 12-bit, and 16-bit valid data in one step. Compared to the corresponding processing, the number of steps can be reduced to 1/4.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention.
FIG. 2 is a block diagram of a conventional example. 1... Arithmetic unit, 2... Rounding bit specification register, 3... 31-bit data bus, 4... 16-bit data bus, 5... Connection point between data bus 3 and data bus 4, 6... Data・Register, 7...
Serial input register, 8... serial output register, 9, 10... output registers of the arithmetic unit. 201...Program ROM, 202...Data ROM, 203...RAM, 204...Program ROM address counter, 205,2
06...Address counter save register, 2
07... Multiplier, 208, 209... Input register to multiplier, 210... Multiplier output register, 211... Arithmetic unit, 212, 213... Arithmetic unit output register, 214... Single precision data Bus, 215...Double precision data bus, 216...Connection point between data bus 214 and data bus 215, 2
17...Data register, 218...Serial input register, 219...Serial output register.

Claims (1)

[Claims] 1. A program storage device that stores a program including control instructions, an instruction decoder that converts the control instructions output from the program storage device into microcode and outputs it, and executes a predetermined operation based on the microcode. an arithmetic unit, a multiplier, a first data bus with a single-precision word length, and a double-precision word length that can directly handle double-precision data from the multiplier in the arithmetic unit and its surroundings; In a digital signal processing device equipped with a second data bus connected to the lower side of the data bus, if the value one bit below the last bit to be retained is 0, the last bit and the values before it are If a certain number series is used as an approximate number series, and the number one bit below the last bit to be kept is 1, add 1 to the last bit and make the result the approximate value number series. A digital signal processing device characterized in that the arithmetic unit executes a rounding operation to an arbitrary bit length by performing a rounding operation on an arbitrary bit.