JPH05289931A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the load of a processor by falsely completing data transfer only by allowing a processor to set up a transferring address and a transferred address in the case of transferring data from an optional area in a memory to another optional area in an information processor having a processor and the memory. CONSTITUTION:The information processor is provided with a means 11b for storing an unconverted address at the time of converting an address outputted from the processor based upon an instruction outputted from the processor, a means 11d for storing a converted address by address conversion, a means 11g for comparing the stored unconverted address with the address outputted from the processor, and a means 11f for switching between the stored converted address and the address outputted from the processor based upon a compared result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a processor and a memory, and in particular, information processing in which data is frequently transferred from an arbitrary area in the memory to a large area or a large amount of data is transferred. Regarding the device.

[0002]

2. Description of the Related Art In a conventional information processing apparatus, when moving data from an arbitrary area in a memory to an arbitrary area, a processor simply reads data from a transfer source area and writes the data in a transfer destination area. I was out.

[0003]

In the conventional information processing apparatus, when data is transferred from any area in the memory to any area as described in the above-mentioned prior art, the processor individually transfers the transfer source area. Since the data was read from and written in the transfer destination area, the load on the processor was significantly increased when the data transfer amount was large or when data transfer frequently occurred.

An object of the present invention is to reduce the load on the processor when the data transfer frequently occurs in the information processing apparatus having the processor and the memory or when the data transfer amount is large.

[0005]

According to the information processing apparatus of the present invention, when transferring data from an arbitrary area in a memory to an arbitrary area, conversion is performed when converting an address output by the processor according to an instruction from the processor. A means for storing the previous address, a means for storing the converted address when converting the address output by the processor according to an instruction from the processor, and a comparison between the stored address before conversion and the address output by the processor And a means for switching the stored converted address and the address output by the processor according to the address comparison result.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will now be described with reference to the drawings.

FIG. 2 is an overall block diagram of a system having a processor and a memory, which is provided with the address converting means of the present invention.

This is a system having five addresses on the address bus (2), and the memory map of this system is shown in FIG.

The memory (13) of FIG. 2 has a capacity of 16 bytes as shown in FIG. 3, and the lower four addresses (A3, A).
2, A1, A0) indicates the address. This memory is 4
Assume that we have an independent buffer of bytes and we define buffer A, buffer B, buffer C and buffer D. Here, a case where the work of transferring the data from the buffer B to the buffer C is simulated using the present invention will be described.

In FIG. 2, the processor (12) is shown in FIG.
By writing the address of the transfer destination buffer C in the pre-conversion register of the address '10000' shown in FIG. 3 and writing the address of the transfer source buffer B in the post-conversion register of the address '10001' shown in FIG. The address (2a) output from the processor (12) shown in 2 becomes a converted address (2b) when passing through the address conversion unit (11), and it is made to appear as if data was pseudo transferred by this address conversion.

The details of the address conversion unit (11) are shown in FIG.
Shown in.

In order to transfer the data in the buffer B shown in FIG. 3 to the buffer C in a pseudo manner, the address '10000' is used.
The processor (12) shown in FIG. 2 writes the address of the buffer C shown in FIG. In FIG. 1, the address decoding unit (11a) determines the accessed address, determines the write signal (3a) from the control bus (3) when the pre-conversion register at the address '10000' is accessed. , In the case of a write operation, the write signal (1
1c) and data (1) from the data bus (1)
a, 1b) is written. Similarly, in the case of write access to the post-conversion register of address '10001' shown in FIG. 3, a write signal (11e) to the post-conversion register (11d) shown in FIG. 1 is generated, and the address of buffer B is written. . Here, the highest address (A
4) is used for decoding whether or not it is a memory, and the least significant 2 bits (A1, A0) indicate the relative address of each of buffer A, buffer B, buffer C, and buffer D, so buffer A, buffer B , A3 and A2 indicating the addresses of the buffer C and the buffer D are to be converted.

By doing so, the address bus (2) for accessing the memory (13) from the processor (12) shown in FIG. 2 thereafter is converted in the conversion unit (11f) of FIG. Specifically, the processor (1
2) accesses the buffer C shown in FIG.
, The input address line (2a3) is'
1 ', (2a2) becomes'0', which coincides with the pre-conversion register (11b) storing the address of the buffer C, so that the comparison unit (11g) generates a coincidence signal (11h). Therefore, (11f3b) in the conversion unit (11f) operates on the input address line (2a3) of the third bit, and (11f3b)
Since f3a) is prohibited, the contents of the post-conversion register (11d) storing the address of the buffer B are output (2b).
3) is performed, the second bit input address line (2a2) is operated by (11f2b) in the conversion unit (11f),
2a) is prohibited, so the contents of the converted register (11d) storing the address of buffer B are output (2b2).
To be done.

By doing so, as shown in the address conversion example of FIG. 4, the input address bus "010XX" is "0".
01XX ', and the address (2a) output from the processor (12) shown in FIG. 2 points to the buffer C shown in FIG. 3, but the converted address (2b) shown in FIG.
Buffer B shown in FIG.
2 to the buffer C, the processor (12) shown in FIG. 2 does not need to individually transfer the data in the buffer B shown in FIG. 3 to the buffer C, and the processor (1
The load of 2) will be greatly reduced.

[0015]

As described above, according to the present invention, when data is transferred from any area in the memory to any area,
Since the data transfer is completed in a pseudo manner only by the processor setting the transfer source address and the transfer destination address, the load on the processor is greatly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an address conversion unit of the present invention.

FIG. 2 is an overall block diagram of the system of the present invention.

FIG. 3 is a memory map of the system of FIG.

FIG. 4 is an example of address conversion in FIG.

[Explanation of symbols]

(1) Data bus (1a, 1b) Data line (2) Address bus (2a) Address bus before conversion (2a4) Address line before conversion of 4th bit (2a3) Address line before conversion of 3rd bit (2a2) 2nd bit pre-conversion address line (2a1) 1st bit pre-conversion address line (2a0) 0th bit pre-conversion address line (2b) Post-conversion address bus (2b4) 4th bit post-conversion address line ( 2b3) Address line after conversion of 3rd bit (2b2) Address line after conversion of 2nd bit (2b1) Address line after conversion of 1st bit (2a0) Address line after conversion of 3rd bit (3) Control bus (3a ) Write signal line (11) Address conversion unit (11a) Address decoding unit (11b) Pre-conversion register (11c) Pre-conversion register write (11d) Register after conversion (11e) Register write signal after conversion (11f) Address converter (11f3a, 11f3b) Address converter for the third bit (11f2a, 11f2b) Address converter for the second bit (11g) Address comparison Part (11h) Address match signal line (12) Processor (13) Memory

Claims (1)

[Claims] 1. An information processing apparatus having a processor and a memory, which stores an address before conversion when converting an address output by the processor according to an instruction from the processor, In response to the instruction, means for storing the converted address when converting the address output by the processor, means for comparing the stored address before conversion with the address output by the processor, and An information processing apparatus comprising: means for switching between the stored converted address and the address output by the processor, depending on the result of the address comparison.