JPH05291948A - Phase locked loop system - Google Patents
Phase locked loop systemInfo
- Publication number
- JPH05291948A JPH05291948A JP4114015A JP11401592A JPH05291948A JP H05291948 A JPH05291948 A JP H05291948A JP 4114015 A JP4114015 A JP 4114015A JP 11401592 A JP11401592 A JP 11401592A JP H05291948 A JPH05291948 A JP H05291948A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- controlled oscillator
- voltage controlled
- phase
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、直交振幅変調された信
号の受信回路等に使用される位相同期ル−プ方式で、周
波数引込み範囲を拡張した位相同期ル−プ方式に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization loop system used in a receiving circuit for quadrature amplitude modulated signals and the like, and more particularly to a phase synchronization loop system having an expanded frequency pulling range.
【０００２】[0002]
【従来技術】従来この種の分野の技術としては、柳沢
健、ＰＬＬ応用回路、第７版、１９８９年、６月１０
日、総合電子出版社、Ｐ５〜Ｐ７、「２．１．１ＰＬＬ
の基本動作」に開示されたものがある。図２は従来の位
相同期ル−プ方式の構成を示す基本ブロック図である。
同図に示すように従来の位相同期ル−プ方式は、入力端
子１、位相比較器（ＰＣ）２、ル−プ・フィルタ３、電
圧制御発振器（ＶＣＯ）４で構成される。2. Description of the Related Art Conventionally, as a technique of this kind of field, Ken Yanagisawa, PLL application circuit, 7th edition, 1989, June 10
Sun, Sogo Denshi Publishing, P5-P7, "2.1.1 PLL
The basic operation of ". FIG. 2 is a basic block diagram showing the configuration of a conventional phase synchronization loop system.
As shown in the figure, the conventional phase-locked loop system is composed of an input terminal 1, a phase comparator (PC) 2, a loop filter 3, and a voltage controlled oscillator (VCO) 4.
【０００３】図２に従って位相同期ル−プの動作を説明
する。入力端子１に入力信号が無い場合、電圧制御発振
器（ＶＣＯ）４は或る周波数で自走発振している。入力
端子１に信号が入力されると、位相比較器（ＰＣ）２で
は、入力端子１の入力信号周波数と電圧制御発振器（Ｖ
ＣＯ）４の信号周波数の周波数及び位相差に対応する信
号を発生する。この信号は次のル−プ・フィルタ３に入
り高調波成分が除去され、低周波成分だけが電圧制御発
振器（ＶＣＯ）４の入力に入り、電圧制御発振器（ＶＣ
Ｏ）４の発振周波数を変化させる。The operation of the phase synchronization loop will be described with reference to FIG. When there is no input signal at the input terminal 1, the voltage controlled oscillator (VCO) 4 is self-oscillating at a certain frequency. When a signal is input to the input terminal 1, in the phase comparator (PC) 2, the input signal frequency of the input terminal 1 and the voltage controlled oscillator (V
A signal corresponding to the frequency and phase difference of the signal frequency of CO) 4 is generated. This signal enters the next loop filter 3 where harmonic components are removed, and only low frequency components enter the input of the voltage controlled oscillator (VCO) 4 and the voltage controlled oscillator (VC
O) Change the oscillation frequency of 4.
【０００４】電圧制御発振器（ＶＣＯ）４は、その周波
数が周波数引込み範囲内であれば、位相比較器２の出力
直流成分が小さくなるような周波数を発振するように働
くため、その発振周波数は次第に入力端子１に入力され
ている信号周波数に接近し、最後には入力端子１に入力
されている信号の周波数と位相に同期する。The voltage controlled oscillator (VCO) 4 operates so as to oscillate a frequency such that the output DC component of the phase comparator 2 becomes small if the frequency is within the frequency pull-in range, so that the oscillation frequency gradually increases. It approaches the frequency of the signal input to the input terminal 1, and finally synchronizes with the frequency and phase of the signal input to the input terminal 1.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、以上説
明した位相同期ル−プ方式の周波数引込み範囲は、位相
同期ル−プのル−プ利得、ル−プ・フィルタ３の特性及
び電圧制御発振器（ＶＣＯ）４の特性等により決まる
が、安定した周波数を得るため電圧制御発振器（ＶＣ
Ｏ）４に水晶発振子を使用したものでは、一般的に可能
な周波数の変化幅は５／１０4程度であり、位相同期ル
−プの周波数引込み範囲も同様に５／１０4程度とな
る。水晶発振器の周波数が５ＭＨｚの場合、位相同期ル
−プの可能な周波数の変化幅は２．５ＫＨｚとなり、周
波数引込み範囲が狭いという問題点があった。However, the frequency pull-in range of the phase locked loop system described above is the loop gain of the phase locked loop, the characteristics of the loop filter 3 and the voltage controlled oscillator ( Although it depends on the characteristics of the VCO 4 etc., a voltage controlled oscillator (VC
In the case where a crystal oscillator is used for (O) 4, the range of frequency change that is generally possible is about 5/10 4 , and the frequency pull-in range of the phase-locked loop is also about 5/10 4. .. When the frequency of the crystal oscillator is 5 MHz, the changeable range of the frequency of the phase-locked loop is 2.5 KHz, and there is a problem that the frequency pull-in range is narrow.
【０００６】本発明は上述の点に鑑みてなされたもの
で、以上述べたように、安定した周波数を得るため電圧
発振器（ＶＣＯ）に水晶振動子を使用した従来の位相同
期ル−プ方式では、周波数引込み範囲が狭いという欠点
を除去した優れた位相同期ル−プ方式を提供することを
目的とする。The present invention has been made in view of the above points, and as described above, in the conventional phase-locked loop system using the crystal oscillator in the voltage oscillator (VCO) in order to obtain a stable frequency. It is an object of the present invention to provide an excellent phase synchronization loop system that eliminates the drawback that the frequency pull-in range is narrow.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
本発明は、図１に示すように従来の位相比較器（ＰＣ）
２、ル−プ・フィルタ３、電圧発振器（ＶＯＣ）４の位
相同期ル−プ方式に乗算器５、固定発振器６、ロ−パス
フィルタ（ＬＰＦ）７及びレベル変換器８を追加したも
のである。発振源として電圧制御発振器（ＶＣＯ）４と
固定発振器６を持ち、その差の周波数信号を入力信号と
位相比較する手段を採った。In order to solve the above problems, the present invention provides a conventional phase comparator (PC) as shown in FIG.
2, a loop filter 3, a voltage oscillator (VOC) 4, and a phase-locked loop system in which a multiplier 5, a fixed oscillator 6, a low-pass filter (LPF) 7 and a level converter 8 are added. .. As a source of oscillation, a voltage controlled oscillator (VCO) 4 and a fixed oscillator 6 are provided, and a means for phase comparing the frequency signal of the difference with the input signal is adopted.
【０００８】[0008]
【作用】本発明では、発振源として電圧制御発振器（Ｖ
ＣＯ）と固定発振器を持ち、その差の周波数信号を入力
信号と位相比較しているが、電圧制御発振器（ＶＣＯ）
の発振周波数と、固定発振器の発振周波数の差をとって
も、位相同期ル−プの周波数引込み周波数幅は変わら
ず、従って前記の差の周波数が低ければ低いほど、差の
周波数に対する位相同期ル−プの周波数引込み周波数幅
の割合は大きくなり、電圧制御発振器（ＶＣＯ）の発振
周波数に対する、電圧制御発振器（ＶＣＯ）と固定発振
器の発振周波数の差の比率だけ位相同期ル−プの周波数
引込み範囲が拡大するため、従来より格段に広い周波数
引込み範囲を持った位相同期ル−プ方式が実現できる。In the present invention, the voltage controlled oscillator (V
CO) and a fixed oscillator, and the frequency signal of the difference is compared in phase with the input signal, but a voltage controlled oscillator (VCO)
The frequency pull-in frequency width of the phase-locked loop does not change even if the difference between the oscillation frequency of the fixed oscillator and the oscillation frequency of the fixed oscillator is taken. Therefore, the lower the frequency of the difference, the phase-locked loop for the frequency of the difference. The ratio of the frequency pull-in frequency width is increased, and the frequency pull-in range of the phase-locked loop is expanded by the ratio of the difference between the oscillation frequency of the voltage-controlled oscillator (VCO) and the oscillation frequency of the fixed oscillator. Therefore, it is possible to realize a phase-locked loop system having a frequency pull-in range that is much wider than in the past.
【０００９】[0009]
【実施例】以下本発明の一実施例を図面に基づいて詳細
に説明する。図１は本発明の位相同期ル−プ方式の実施
例を示すブロック図である。本装置は、入力端子１、位
相比較器（ＰＣ）２、ル−プ・フィルタ３、電圧制御発
振器（ＶＣＯ）４、乗算器５、固定発振器６、ロ−パス
フィルタ（ＬＰＦ）７、レベル変換器８、出力端子９で
構成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the phase synchronization loop system of the present invention. This device includes an input terminal 1, a phase comparator (PC) 2, a loop filter 3, a voltage controlled oscillator (VCO) 4, a multiplier 5, a fixed oscillator 6, a low pass filter (LPF) 7, and a level conversion. It is composed of a container 8 and an output terminal 9.
【００１０】入力端子１は位相比較器（ＰＣ）２の片方
の信号入力と接続され、その出力はル−プ・フィルタ３
の入力と接続され、ル−プ・フィルタ３の出力は電圧制
御発振器（ＶＣＯ）４の入力と接続され、その出力は乗
算器５の片方の入力と接続される。又、固定発振器６の
出力は乗算器５のもう一方と接続され、乗算器５の出力
はロ−パスフィルタ７の入力と接続される。更にロ−パ
スフィルタ７の出力はレベル変換器８の入力と接続さ
れ、その出力は出力端子９及び位相比較器（ＰＣ）２の
一方の入力と接続される。The input terminal 1 is connected to one of the signal inputs of a phase comparator (PC) 2 and its output is a loop filter 3
, The output of the loop filter 3 is connected to the input of the voltage controlled oscillator (VCO) 4, and its output is connected to one input of the multiplier 5. The output of the fixed oscillator 6 is connected to the other side of the multiplier 5, and the output of the multiplier 5 is connected to the input of the low pass filter 7. Further, the output of the low-pass filter 7 is connected to the input of the level converter 8, and the output thereof is connected to the output terminal 9 and one input of the phase comparator (PC) 2.
【００１１】図１に示す構成の位相同期ループ方式にお
いて、始めに入力端子１に信号が無い場合、電圧制御発
振器（ＶＣＯ）４は或る周波数で自走発振している。
又、固定発振器６も常に一定周波数の発振をしており、
乗算器５ではこの二つの信号の乗算が行われ、その二つ
の信号周波数の和の周波数成分と、差の周波数成分が出
力される。ロ−パスフィルタ７では、乗算器出力の周波
数成分の内、低い周波数成分である差の周波数成分のみ
が通過し、レベル変換器８に入力される。In the phase-locked loop system having the configuration shown in FIG. 1, when there is no signal at the input terminal 1 at first, the voltage controlled oscillator (VCO) 4 oscillates at a certain frequency.
Further, the fixed oscillator 6 also always oscillates at a constant frequency,
The multiplier 5 multiplies the two signals, and outputs the frequency component of the sum of the two signal frequencies and the frequency component of the difference. In the low-pass filter 7, of the frequency components of the multiplier output, only the difference frequency component, which is a low frequency component, passes and is input to the level converter 8.
【００１２】レベル変換器８では信号をクリップし一定
振幅の信号に変換する。本実施例では電圧制御発振器
（ＶＣＯ）４の自走発振周波数は２０ＭＨｚ、固定発振
器６の発振周波数は１５ＭＨｚとしてあり、その差の５
ＭＨｚの周波数信号が位相比較器２の片方の入力に加わ
っている。The level converter 8 clips the signal and converts it into a signal having a constant amplitude. In this embodiment, the free-running oscillation frequency of the voltage controlled oscillator (VCO) 4 is 20 MHz and the oscillation frequency of the fixed oscillator 6 is 15 MHz, which is 5
A frequency signal of MHz is applied to one input of the phase comparator 2.
【００１３】次に入力端子１に信号が入力された場合、
位相比較器（ＰＣ）２では入力端子１の入力信号周波数
と、レベル変換器８からの５ＭＨｚの信号の周波数及び
位相差に対応する信号を発生する。この信号は次のル−
プ・フィルタ３に入り高周波成分が除去され、低周波成
分だけが電圧制御発振器（ＶＣＯ）４の入力に入り、電
圧制御発振器（ＶＣＯ）４の発振周波数を変化させる。Next, when a signal is input to the input terminal 1,
The phase comparator (PC) 2 generates a signal corresponding to the input signal frequency of the input terminal 1 and the frequency and phase difference of the 5 MHz signal from the level converter 8. This signal is
The high frequency component is removed from the input filter 3 and only the low frequency component enters the input of the voltage controlled oscillator (VCO) 4 to change the oscillation frequency of the voltage controlled oscillator (VCO) 4.
【００１４】電圧制御発振器（ＶＣＯ）４は、位相比較
器（ＰＣ）２の出力の直流成分が小さくなるような周波
数を発振するように働くため、電圧制御発振器（ＶＣ
Ｏ）４の発振周波数は、電圧制御発振器（ＶＣＯ）４の
発振周波数−固定発振器６の発振周波数＝入力端子１の
信号周波数に近づいていき、最後には差の信号は入力端
子１の信号に同期する。この差の周波数信号が出力とな
る。The voltage controlled oscillator (VCO) 4 operates so as to oscillate at a frequency such that the DC component of the output of the phase comparator (PC) 2 becomes small.
The oscillation frequency of (O) 4 approaches the oscillation frequency of the voltage controlled oscillator (VCO) 4−the oscillation frequency of the fixed oscillator 6 = the signal frequency of the input terminal 1, and finally the difference signal becomes the signal of the input terminal 1. Synchronize. The frequency signal of this difference becomes the output.
【００１５】以上説明した本実施例の場合、電圧制御発
振器（ＶＣＯ）４の可能な周波数変化幅を５／１０4と
して、発振周波数が２０ＭＨｚとするとその周波数変化
幅は１０ＫＨｚと成る。本発明では電圧制御発振器（Ｖ
ＣＯ）４の周波数と、固定発振器６の周波数の差の周波
数信号を使用しているが、電圧制御発振器（ＶＣＯ）４
の周波数変化幅は乗算器出力においても変わりないた
め、乗算器５の出力周波数は、この二周波数の差の５Ｍ
Ｈｚになり、可能な変化幅が１０ＫＨｚとなる。従っ
て、その割合は２／１０3となりこれが位相同期ル−プ
の周波数引込み範囲になるので、従来の位相同期ル−プ
の周波数引込み範囲５／１０4に比べて周波数引込み範
囲が４倍に広がったことになる。In the case of the present embodiment described above, when the possible frequency variation width of the voltage controlled oscillator (VCO) 4 is 5/10 4 and the oscillation frequency is 20 MHz, the frequency variation width is 10 KHz. In the present invention, the voltage controlled oscillator (V
The frequency signal of the difference between the frequency of the CO) 4 and the frequency of the fixed oscillator 6 is used.
Since the width of frequency change of is not changed even in the output of the multiplier, the output frequency of the multiplier 5 is 5M which is the difference between these two frequencies.
Hz, the possible range of change is 10 KHz. Therefore, the ratio becomes 2/10 3 , which is the frequency pull-in range of the phase-locked loop, and the frequency pull-in range is expanded four times as compared with the frequency pull-in range 5/10 4 of the conventional phase-locked loop. It will be.
【００１６】[0016]
【発明の効果】以上、詳細に説明したように本発明によ
れば、下記のような効果が期待される。発振源として電
圧制御発振器（ＶＣＯ）と固定発振器を持ち、その差の
周波数信号を入力信号と位相比較しているが、電圧制御
発振器（ＶＣＯ）の発振周波数と、固定発振器の発振周
波数の差をとっても位相同期ル−プの周波数引込み周波
数幅は変わらず、従って前記の差の周波数が低ければ低
いほど、差の周波数に対する位相同期ル−プの周波数引
込み周波数幅の割合は大きくなり、電圧制御発振器ＶＣ
Ｏ）の発振周波数に対する電圧制御発振器（ＶＣＯ）と
固定発振器の発振周波数の差の比率だけ位相同期ル−プ
の周波数引込み範囲が拡大するため、従来より格段に広
い周波数引込み範囲を持った位相同期ル−プ方式となる
という優れた効果が得られる。As described in detail above, according to the present invention, the following effects are expected. It has a voltage controlled oscillator (VCO) as an oscillation source and a fixed oscillator, and the frequency signal of the difference is compared in phase with the input signal. The difference between the oscillation frequency of the voltage controlled oscillator (VCO) and the oscillation frequency of the fixed oscillator is The frequency pull-in frequency width of the phase-locked loop does not change. Therefore, the lower the difference frequency is, the larger the ratio of the frequency pull-in frequency width of the phase-locked loop to the difference frequency becomes, and the voltage controlled oscillator. VC
The frequency pull-in range of the phase-locked loop is expanded by the ratio of the difference between the oscillation frequency of the voltage controlled oscillator (VCO) and the fixed oscillator with respect to the oscillation frequency of (O). An excellent effect of being a loop system can be obtained.
【図１】本発明の位相同期ル−プ方式の構成を示すブロ
ック図である。FIG. 1 is a block diagram showing a configuration of a phase synchronization loop system of the present invention.
【図２】従来の位相同期ル−プ方式の基本構成を示すブ
ロック図である。FIG. 2 is a block diagram showing a basic configuration of a conventional phase synchronization loop system.
１ 入力端子 ２ 位相比較器（ＰＣ） ３ ル−プ・フィルタ ４ 電圧制御発振器（ＶＣＯ） ５ 乗算器 ６ 固定発振器 ７ ロ−パスフィルタ ８ レベル変換器 ９ 出力端子 1 Input Terminal 2 Phase Comparator (PC) 3 Loop Filter 4 Voltage Controlled Oscillator (VCO) 5 Multiplier 6 Fixed Oscillator 7 Low Pass Filter 8 Level Converter 9 Output Terminal
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 7928−5Ｋ Ｈ０４Ｌ 7/02 Ｂ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 7928-5K H04L 7/02 B
Claims (1)
発振器で構成され、入力信号と前記電圧制御発振器の出
力を前記位相比較器で比較し、その出力信号を前記ル−
プフィルタを通して前記電圧制御発振器に入力し制御し
ている位相同期ル−プ方式において、 一定周波数の出力信号を出力する固定発振器と、前記電
圧制御発振器の出力信号と前記固定発振器の出力信号の
差を出力信号として生じさせる手段とを設け、入力信号
と前記出力の差信号を前記位相比較器で位相比較し、そ
の出力信号で前記電圧制御発振器を制御することを特徴
とする位相同期ル−プ方式。1. A phase comparator, a loop filter and a voltage controlled oscillator, wherein an input signal and an output of the voltage controlled oscillator are compared by the phase comparator, and the output signal is compared with the loop signal.
In the phase-locked loop system in which the voltage-controlled oscillator is input to and controlled by a fixed filter, a fixed oscillator that outputs an output signal of a constant frequency, and a difference between the output signal of the voltage-controlled oscillator and the output signal of the fixed oscillator Means for generating an output signal, comparing the phase difference between the input signal and the output signal by the phase comparator, and controlling the voltage controlled oscillator by the output signal. ..
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4114015A JPH05291948A (en) | 1992-04-07 | 1992-04-07 | Phase locked loop system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4114015A JPH05291948A (en) | 1992-04-07 | 1992-04-07 | Phase locked loop system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05291948A true JPH05291948A (en) | 1993-11-05 |
Family
ID=14626921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4114015A Pending JPH05291948A (en) | 1992-04-07 | 1992-04-07 | Phase locked loop system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05291948A (en) |
-
1992
- 1992-04-07 JP JP4114015A patent/JPH05291948A/en active Pending
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