JPH0529491A - Circuit board for mounting semiconductor - Google Patents
Circuit board for mounting semiconductorInfo
- Publication number
- JPH0529491A JPH0529491A JP20615091A JP20615091A JPH0529491A JP H0529491 A JPH0529491 A JP H0529491A JP 20615091 A JP20615091 A JP 20615091A JP 20615091 A JP20615091 A JP 20615091A JP H0529491 A JPH0529491 A JP H0529491A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- circuit board
- foil
- semiconductor
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000011733 molybdenum Substances 0.000 claims abstract description 11
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 11
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 15
- 230000035939 shock Effects 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000005336 cracking Methods 0.000 abstract description 2
- 239000011888 foil Substances 0.000 description 34
- 229910052782 aluminium Inorganic materials 0.000 description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 239000010949 copper Substances 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- -1 aluminum-molybdenum-copper Chemical compound 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 7
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000002952 polymeric resin Substances 0.000 description 4
- 229920003002 synthetic resin Polymers 0.000 description 4
- 239000010953 base metal Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、電気機器、通信機およ
び自動車等に用いられる半導体搭載用回路基板に関し、
特にシリコンチップとの高い接合信頼性を有する半導体
搭載用回路基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor-mounted circuit board used in electric equipment, communication equipment, automobiles, etc.
In particular, the present invention relates to a semiconductor-mounting circuit board having a high bonding reliability with a silicon chip.
【0002】[0002]
【従来の技術】従来、電気機器、通信機および自動車等
の高密度実装用半導体搭載用回路基板として、金属基板
に絶縁層を介してアルミニウム−銅クラッド箔を順に積
層してなる積層物上のアルミニウム−銅クラッド箔をエ
ッチングして配線回路を形成した半導体搭載用回路基板
が用いられている(特公平1−15153)。2. Description of the Related Art Conventionally, as a circuit board for mounting semiconductors for high density mounting of electric equipment, communication equipment, automobiles, etc., on a laminate formed by sequentially laminating aluminum-copper clad foil on a metal substrate via an insulating layer. A semiconductor-mounting circuit board in which a wiring circuit is formed by etching an aluminum-copper clad foil is used (Japanese Patent Publication No. 1-15153).
【0003】[0003]
【発明が解決しようとする課題】しかしながら、高密度
実装化が進むにつれて、電気機器、自動車等の民生機器
等の環境条件の厳しい用途では、使用している間、シリ
コンチップ、その他の素子の発熱や外部からの熱移動に
より、この回路基板の温度が上昇する。このため、シリ
コンチップと回路箔との熱膨張率の差による熱歪や電源
のオンオフによる熱衝撃のためにシリコンチップを固定
している半田が割れるという問題があった。However, as high-density mounting progresses, the heat generated in the silicon chip and other elements during use is increased in applications such as electric equipment, consumer equipment such as automobiles, etc. where environmental conditions are severe. The temperature of the circuit board rises due to heat transfer from the outside or outside. Therefore, there is a problem that the solder fixing the silicon chip is cracked due to thermal strain due to the difference in coefficient of thermal expansion between the silicon chip and the circuit foil and thermal shock due to turning the power supply on and off.
【0004】本発明はかかる問題点に鑑みてなされたも
のであり、シリコンチップと回路箔との熱膨張率の違い
による熱歪の発生を抑え半田割れを防止し、シリコンチ
ップとの高い接合信頼性を有す半導体搭載用回路基板を
提供することを目的とするものである。The present invention has been made in view of the above problems, and suppresses thermal strain due to a difference in thermal expansion coefficient between a silicon chip and a circuit foil to prevent solder cracking and high reliability of bonding with a silicon chip. It is an object of the present invention to provide a semiconductor mounting circuit board having properties.
【0005】[0005]
【課題を解決するための手段】すなわち、本発明の半導
体搭載用回路基板は、金属基板に絶縁層を介して複数の
異種金属層からなる導電層を積層してなる半導体搭載用
基板において、該導電層の内部にモリブデン層を有する
ことを特徴とする半導体搭載用回路基板である。That is, a semiconductor-mounting circuit board of the present invention is a semiconductor-mounting board in which a conductive layer composed of a plurality of dissimilar metal layers is laminated on a metal substrate via an insulating layer. A circuit board for mounting semiconductor, comprising a molybdenum layer inside a conductive layer.
【0006】[0006]
【作用】本発明の半導体搭載用回路基板は配線回路を形
成する導電層が複数の異種金属層で形成さ0ていて、そ
の内部にシリコンの熱膨張率に近い、モリブデン層を介
在させるので、シリコンチップに近い熱膨張率を有する
配線回路をつくることが出来るので、周囲温度が上昇し
ても熱歪の発生が無く、シリコンチップを固定している
半田割れの発生を防止することができる。In the semiconductor mounting circuit board of the present invention, the conductive layer forming the wiring circuit is formed of a plurality of different metal layers, and the molybdenum layer having a thermal expansion coefficient close to that of silicon is interposed therein. Since it is possible to form a wiring circuit having a coefficient of thermal expansion close to that of a silicon chip, thermal distortion does not occur even when the ambient temperature rises, and it is possible to prevent the occurrence of solder cracks that fix the silicon chip.
【0007】以下、図面により本発明を詳細に説明す
る。図1、図2は、本発明の半導体の搭載用回路基板の
基板に用いられる積層物の断面図である。図3は実施例
で、図4は従来技術を示したものである。図1は、金属
基板1に絶縁層2を介してアルミニウム箔とモリブデン
箔と銅箔のクラッド箔からなる複数の金属箔からなる導
電箔3の、アルミニウム箔4を上面として積層したもの
である。ここで、モリブデン層は銅箔間に積層したもの
の例を示した。また、図2は絶縁層2に、積層するアル
ミニウム箔とモリブデン箔と銅箔とのクラッド箔3の銅
箔5を上面とした回路基板の断面図を示したものであ
り、複数の金属層からなる導電層3を有する。これらの
異種金属層は少なくとも2種以上のものからなり、この
金属層一部は必ずしも箔でなくともよく、例えばメッキ
や蒸着による金属層でもよい。また、図3は本発明の半
導体搭載用回路基板に半導体を実装した半導体搭載回路
の断面図である。The present invention will be described in detail below with reference to the drawings. 1 and 2 are cross-sectional views of a laminate used for a substrate of a semiconductor mounting circuit board of the present invention. FIG. 3 shows an embodiment, and FIG. 4 shows a prior art. In FIG. 1, an aluminum foil 4 is laminated on a metal substrate 1 via an insulating layer 2 with an aluminum foil 4 as an upper surface of a conductive foil 3 made of a plurality of metal foils composed of aluminum foil, molybdenum foil, and clad foil of copper foil. Here, an example of the molybdenum layer laminated between copper foils is shown. FIG. 2 shows a cross-sectional view of the circuit board with the copper foil 5 of the clad foil 3 of the aluminum foil, the molybdenum foil, and the copper foil to be laminated on the insulating layer 2 as the upper surface. The conductive layer 3 is formed. These dissimilar metal layers are composed of at least two kinds, and a part of this metal layer does not necessarily have to be a foil, and may be, for example, a metal layer formed by plating or vapor deposition. Further, FIG. 3 is a cross-sectional view of a semiconductor mounting circuit in which a semiconductor is mounted on the semiconductor mounting circuit board of the present invention.
【0008】本発明の半導体搭載用回路基板に用いるベ
ース金属基板1としては、良伝導性を持つアルミニウム
およびアルミニウム合金、銅および銅合金、鉄、並びに
ステンレス等が使用可能である。また、ベース金属基板
1の厚みとしては、特に制限はないが0.5mm 〜3.0mm が
一般に用いられる。As the base metal substrate 1 used in the semiconductor-mounting circuit board of the present invention, aluminum and aluminum alloys having good conductivity, copper and copper alloys, iron, stainless steel and the like can be used. The thickness of the base metal substrate 1 is not particularly limited, but 0.5 mm to 3.0 mm is generally used.
【0009】また、本発明に使用される絶縁層2として
は、各種セラミックス、無機フィラーを含有した高分子
樹脂絶縁層、ガラス繊維を含有する高分子樹脂層および
耐熱性高分子樹脂絶縁層が用いられる。また、その絶縁
層2の肉厚は、絶縁不良を生じない程度で有れば特に制
限はなく、20μm以上が一般に使用される。絶縁層2に
用いる無機粉体としてはアルミナ、シリカ、ベリリヤ、
ボロンナイトライド、マグネシア、窒化珪素、窒化アル
ミニウムおよび炭化珪素等が用いられ、高分子樹脂とし
ては、エポキシ樹脂、フェノール樹脂、ポリイミド樹脂
および各種エンジニアプラスチックが使用できる。As the insulating layer 2 used in the present invention, various ceramics, a polymer resin insulating layer containing an inorganic filler, a polymer resin layer containing a glass fiber and a heat resistant polymer resin insulating layer are used. Be done. The thickness of the insulating layer 2 is not particularly limited as long as it does not cause insulation failure, and 20 μm or more is generally used. As the inorganic powder used for the insulating layer 2, alumina, silica, beryllia,
Boron nitride, magnesia, silicon nitride, aluminum nitride, silicon carbide and the like are used, and as the polymer resin, epoxy resin, phenol resin, polyimide resin and various engineered plastics can be used.
【0010】本発明に用いられるアルミニウム−モリブ
デン−銅クラッド箔3のアルミニウムの材質としては、
純アルミニウムおよびアルミニウム合金でもかまわな
い。また、アルミニウム、モリブデン、銅の接合方法と
しては、圧延法でもメッキ法でも差し支えない。また、
メッキ法の場合は、アルミニウムと銅との接合強度を上
げるために、アルミニウムと銅の間に亜鉛、錫およびニ
ッケル等をメッキすることもできる。The aluminum material of the aluminum-molybdenum-copper clad foil 3 used in the present invention is as follows:
Pure aluminum and aluminum alloys may be used. The aluminum, molybdenum, and copper may be joined by rolling or plating. Also,
In the case of the plating method, zinc, tin, nickel or the like may be plated between aluminum and copper in order to increase the bonding strength between aluminum and copper.
【0011】また、本発明のアルミニウム−モリブデン
−銅クラッド箔3は、厚みを特定するものではないが、
例えば大電流用途では、35μm〜1,000 μmが好まし
く、制御用の小電流では、9 μm〜70μmの箔厚が望ま
しい。The thickness of the aluminum-molybdenum-copper clad foil 3 of the present invention is not specified, but
For example, 35 μm to 1,000 μm is preferable for high current use, and 9 μm to 70 μm is preferable for small current for control.
【0012】本発明で使用されるアルミニウム−モリブ
デン−銅クラッド箔3のモリブデン層の積層箇所はアル
ミニウムと銅との間でも、アルミニウム−銅クラッド箔
と銅との間でも、アルミニウムとアルミニウム−銅クラ
ッド箔との間でもかまわない。また、アルミニウム−モ
リブデン−銅クラッド箔と絶縁層の接着面はアルミニウ
ム面でも銅面でもかまわない。The molybdenum layer of aluminum-molybdenum-copper clad foil 3 used in the present invention may be laminated between aluminum and copper, between aluminum-copper clad foil and copper, or between aluminum and aluminum-copper clad. It doesn't matter between it and the foil. Moreover, the aluminum-molybdenum-copper clad foil and the insulating layer may be bonded to each other by an aluminum surface or a copper surface.
【0013】[0013]
【実施例】本発明の実施例について図を用いて具体的に
説明する。Embodiments of the present invention will be specifically described with reference to the drawings.
【0014】〔実施例1〕図3には、厚さ3.0mm のアル
ミニウム基板1上に絶縁接着剤を100 μmの厚みで塗布
し、アルミニウム40μm−銅150 μm−モリブデン10μ
m−銅150 μmの前記クラッド箔3をアルミニウム箔面
を上面として張り合わせた回路基板を用い、半導体等を
実装した半導体搭載回路の断面図である。上記回路基板
にスクリーン印刷法でレジストを塗布し、アルミニウム
−モリブデン−銅クラッド箔3の両者に対しエッチング
可能な塩化第二鉄等でエッチングして配線回路を形成さ
せる。レジストを取り除いた後、アルミニウムパッドが
必要な部分に再びレジスト塗布し、アルカリエッチング
等の選択的にアルミニウムを溶かすエッチング液を用い
て不必要なアルミニウム部分を取り除き、銅箔部を露出
させる。レジストを取り除いた後、該銅回路5上に半田
9を介して半導体やチップ抵抗素子を搭載した後、半導
体8とアルミニウム回路4とをアルミニウムリード線7
により超音波振動法で固着したものである。Example 1 In FIG. 3, an insulating adhesive is applied to an aluminum substrate 1 having a thickness of 3.0 mm to a thickness of 100 μm, and aluminum 40 μm-copper 150 μm-molybdenum 10 μm.
FIG. 4 is a cross-sectional view of a semiconductor-mounted circuit in which a semiconductor or the like is mounted using a circuit board in which the clad foil 3 of m-copper 150 μm is laminated with the aluminum foil surface as an upper surface. A resist is applied to the circuit board by a screen printing method, and both of the aluminum-molybdenum-copper clad foil 3 are etched with ferric chloride or the like that can be etched to form a wiring circuit. After removing the resist, the resist is again applied to the portion where the aluminum pad is required, and the unnecessary aluminum portion is removed by using an etching solution such as alkali etching that selectively dissolves aluminum to expose the copper foil portion. After removing the resist, a semiconductor or a chip resistance element is mounted on the copper circuit 5 via solder 9, and then the semiconductor 8 and the aluminum circuit 4 are connected to the aluminum lead wire 7.
By the ultrasonic vibration method.
【0015】この様にして作製した半導体搭載基板を、
ヒートショック試験機(タバイ製)「TSRー63」を
用い-50 ℃*30min=+150℃*30minの条件にて耐熱衝撃テ
ストを行った。熱衝撃により半田割れが生じたものは電
気抵抗が大きくなる。このシリコンチップと、チップと
接合している導電箔との電気抵抗を調べた結果を図5に
示す。1200回の熱衝撃テスト後もほとんど抵抗値の増加
が見られなかった。The semiconductor mounting substrate thus manufactured is
Using a heat shock tester (Tabay) "TSR-63", a thermal shock test was conducted under the conditions of -50 ° C * 30min = + 150 ° C * 30min. If the solder cracks are caused by thermal shock, the electrical resistance increases. FIG. 5 shows the result of examining the electric resistance between this silicon chip and the conductive foil bonded to the chip. Almost no increase in resistance value was observed after 1200 thermal shock tests.
【0016】〔比較例1〕図4は、厚さ3.0mm のアルミ
ニウム基板1上に絶縁接着剤を100 μmの厚みで塗布
し、アルミニウム40μm−銅300 μmのアルミニウム−
銅クラッド箔(4、5)をアルミニウム面を上面とし張
り合わせた回路基板に、実施例1と同様な方法により回
路を形成し、半導体を搭載したものである。該半導体搭
載基板を実施例1と同じ方法で耐熱衝撃試験を行った結
果を図5に示す。Comparative Example 1 FIG. 4 shows that an insulating adhesive is applied to an aluminum substrate 1 having a thickness of 3.0 mm to a thickness of 100 μm and aluminum 40 μm-copper 300 μm aluminum-
A circuit is formed by laminating copper clad foils (4, 5) with an aluminum surface as an upper surface, and a semiconductor is mounted by forming a circuit by the same method as in the first embodiment. FIG. 5 shows the result of a thermal shock test conducted on the semiconductor mounting substrate in the same manner as in Example 1.
【0017】[0017]
【発明の効果】アルミニウム−モリブデン−銅クラッド
箔を用いる事により、シリコンチップとの高い接合信頼
性を有する半導体搭載用回路基板を作製する事が可能と
なった。By using the aluminum-molybdenum-copper clad foil, it has become possible to manufacture a circuit board for mounting semiconductors having a high bonding reliability with a silicon chip.
【図1】本発明の半導体搭載用回路基板でアルミニウム
−モリブデン−銅クラッド箔のアルミニウム箔を上面と
した断面図である。FIG. 1 is a cross-sectional view of an aluminum-molybdenum-copper clad foil with an aluminum foil as an upper surface in a semiconductor-mounting circuit board of the present invention.
【図2】本発明の半導体搭載用回路基板でアルミニウム
−モリブデン−銅クラッド箔の銅箔を上面とした断面図
である。FIG. 2 is a cross-sectional view of a semiconductor-mounting circuit board according to the present invention with a copper foil of an aluminum-molybdenum-copper clad foil as an upper surface.
【図3】本発明の半導体搭載用回路基板に半導体等を実
装した半導体搭載回路の断面図である。FIG. 3 is a cross-sectional view of a semiconductor mounting circuit in which a semiconductor or the like is mounted on the semiconductor mounting circuit board of the present invention.
【図4】本発明の比較例として用いた半導体搭載用回路
基板に半導体等を実装した半導体搭載回路の断面図であ
る。FIG. 4 is a cross-sectional view of a semiconductor mounting circuit in which a semiconductor or the like is mounted on a semiconductor mounting circuit board used as a comparative example of the present invention.
【図5】耐熱衝撃試験によるシリコンチップと接合導電
箔との電気抵抗の経時変化を示したものである。FIG. 5 is a graph showing a change with time in electric resistance between a silicon chip and a bonded conductive foil in a thermal shock test.
1.ベース金属基板 2.絶縁層 3.アルミニウム−モリブデン−銅クラッド箔 4.アルミニウム箔 5.銅箔 6.モリブデン箔 7.リード線 8.シリコンチップ 9.半田 1. Base metal substrate 2. Insulation layer 3. Aluminum-molybdenum-copper clad foil 4. Aluminum foil 5. Copper foil 6. Molybdenum foil 7. Lead wire 8. Silicon chip 9. solder
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/38 C 7011−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05K 3/38 C 7011-4E
Claims (1)
属層からなる導電層を積層してなる半導体搭載用基板に
おいて、該導電層の内部にモリブデン層を有することを
特徴とする半導体搭載用回路基板。Claim: What is claimed is: 1. A semiconductor mounting substrate comprising a metal substrate and a conductive layer composed of a plurality of dissimilar metal layers laminated on an insulating layer with a molybdenum layer inside the conductive layer. A semiconductor mounting circuit board characterized by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20615091A JPH0529491A (en) | 1991-07-24 | 1991-07-24 | Circuit board for mounting semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20615091A JPH0529491A (en) | 1991-07-24 | 1991-07-24 | Circuit board for mounting semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0529491A true JPH0529491A (en) | 1993-02-05 |
Family
ID=16518628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20615091A Pending JPH0529491A (en) | 1991-07-24 | 1991-07-24 | Circuit board for mounting semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529491A (en) |
-
1991
- 1991-07-24 JP JP20615091A patent/JPH0529491A/en active Pending
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