JPH0529572A - Stack-trench structure DRAM cell with vertical transistor - Google Patents

Abstract

(57) [Abstract] [Purpose] 64 with excellent reliability and stable operation characteristics
Stack-trench structure DR having vertical transistors applicable to M or higher density DRAM
Provide an AM cell. A DRAM cell includes a storage electrode 9 formed in the form of a stack trench on an oxide film 5 formed along an inner sidewall of a trench formed in a P-type silicon substrate 1.
Capacitor dielectric 11 formed on the surface of storage electrode 9
And a storage capacitor composed of a plate 12 formed in contact with the capacitor dielectric 11 and filling the inside of the trench, and a storage electrode 9 on one side of the upper end portion of the storage electrode 9.
Source 13, which is connected to the gate oxide film 14, a gate oxide film 14 formed along the inner sidewall of the upper end of the trench, and a word line 15 which is a gate electrode formed on the gate oxide film 14.
And the drain 1 formed on the silicon surface between the trenches
And a transfer transistor having a vertical structure including.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a highly integrated semiconductor DRAM.
(Dynamic Random Access Me
More specifically, the present invention relates to a stacked-trench structure DRAM cell having a vertical transistor which is highly reliable and has stable operation characteristics, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to realize a highly integrated DRAM, DR
The structure of the AM cell has undergone many changes from an initial planar structure to a trench or stack structure recently.
The storage capacitor is miniaturized as much as possible within the allowable process range.
It is a known fact that the progress toward maximizing the capacity of the (actor) is already made.

Most of the cell structures announced so far are transfer transistors (Transfer Trs).
The cell area required for the 64M DRAM cannot be satisfied because the anisotropy) is located horizontally on the substrate and the storage capacitor is located beside the transfer transistor.

In order to solve the above-mentioned problems, as shown in FIG. 1, a transfer transistor is vertically arranged and a storage capacitor is arranged below the transfer transistor.
A cell with a Trench Transistor) was developed. The CTT structure cell has P ⁺
The dielectric film 2 is formed in the trench formed in the silicon substrate 201.
02, a capacitor having a capacitor plate 203 is formed, and a lateral contact 204 is further formed on the trench. 205 is a gate oxide film, 206 is a bit line made of a buried n ⁺ layer, 2
Reference numeral 07 is a word line, and 208 is a field oxide film.

However, depending on the cell having the CTT structure as described above, LOCOS (Local) may be used to separate the bit lines.
However, since the 1 Oxidation of Silicon) method is used, there is a drawback that the separation area from adjacent cells cannot be reduced.

Recently, the SGT (Surround) shown in FIG.
ding Gate Transistor) was announced. In the cell having the SGT structure, a capacitor having a dielectric film 302 and a capacitor plate 303 is formed in a trench provided in a P-type silicon substrate 301, and an n ⁻ diffusion region 304 is formed on the outer periphery of the capacitor. Further, a gate oxide film 305 is formed on the n ⁻ diffusion region 304, and an n ⁺ layer 306 is formed on the silicon pillar. Adjacent cells are separated by a P ^- separation region 307. 308 is a word line, 309 is a bit line, 31
Reference numeral 0 is a CVD oxide film. In the SGT structure cell, a vertical transfer transistor is located above the silicon pillar, and a storage capacitor having a high capacitance structure is located below the silicon pillar. The capacitors are all formed. The SGT structure cell is
Although it satisfies the cell area required for 64M DRAM,
Since the storage capacitor has a high capacitance structure,
Not only is the SER (soft error rate) induced in the α-particles large, but because of the high capacitance, it is necessary to dope around the silicon pillars with a high concentration. There is a problem that the transfer transistor may be floated with respect to the substrate depending on the layer.

[0007]

SUMMARY OF THE INVENTION Therefore, the present invention provides a stack-trench structure DRAM cell having a vertical transistor applicable to a DRAM having an integration degree of 64M or higher, which is highly reliable and has stable operation characteristics. Its purpose is to provide.

[0008]

In order to achieve the above object, the present invention is directed to stacking on an oxide film formed along an inner sidewall of a trench except for an upper end portion of a trench formed in a P-type silicon substrate. A storage electrode formed in the form of a trench, a capacitor dielectric formed on the surface of the storage electrode, and a plate formed in contact with the capacitor dielectric and filling the inside of the trench except the upper end of the trench. A storage capacitor, a source connected to the storage electrode on one side of the upper end of the storage electrode, a gate oxide film formed along the inner sidewall of the upper end of the trench to the upper end of the trench, and the gate oxide. A vertical structure including a word line, which is a gate electrode formed on the film, and a drain formed on the silicon surface between the trenches. Characterized in that it contains a lance fur transistor.

[0009]

The present invention uses a stack-trench type capacitor to provide a low soft error rate and excellent reliability, and locally doping only a part of the silicon pillar to connect the transfer transistor and the storage capacitor. By doing so, the phenomenon in which the transistor floats on the silicon substrate is reduced, and stable operation characteristics are realized.

[0010]

The present invention will be described in detail below with reference to the accompanying drawings.

3 to 12 are views showing a manufacturing process of an embodiment of the present invention.

In FIG. 3, an oxide film 2 having a thickness of about 250 Å is formed on the upper surface of a P-type silicon substrate 1, and a thickness of about 1,0 is formed thereon.
A trench formed after depositing a 00Å silicon nitride film 3 is shown. After depositing the oxide film 4 on the silicon nitride film 3 by the CVD (Chemical Vapor Deposition) method to a thickness of about 1,000Å, the CVD oxide film is densified in an H ₂ / O ₂ atmosphere at 925 ° C. Then, a mask layer for trench etching was formed. Then, using the trench mask layer, the oxide film 4, the silicon nitride film 3, and the oxide film 2 were sequentially etched by the RIE (reactive ion etching) method. Further, a trench having a depth of 0.3 to 1.2 μm was etched to form a transfer transistor, and then an oxide film 5a was grown in the trench (see FIG. 3).

FIG. 4 shows a secondary trench formed in the substrate 1. Silicon nitride was deposited in the trench in the portion where the device was formed to form the silicon nitride sidewall spacer 6. After etching the secondary trench having a depth of about 3 to 5 μm,
An oxide film 5 having a thickness of about 2,000Å was grown in an H ₂ / O ₂ atmosphere at 0 ° C.

The silicon oxide film at the bottom of the trench was etched by RIE and boron was implanted (or BN was used as a source) to form an isolation 7 with an adjacent cell. A thick photoresist 8 was applied, and the silicon oxide film was partially wet-etched for contact between the charge storage electrode and the transistor (see FIG. 5).

Polysilicon 9a was deposited, doped with POCl ₃ and coated with photo-lensist 10 and then etched by an etch-back process. The charge storage electrode 9 was formed by such a process (see FIGS. 6 to 7).

FIG. 8 shows a process of forming a capacitor dielectric. After removing the photoresist 10 in the trench and removing the polysilicon layer 9 at the bottom of the trench by RIE, a capacitor dielectric 11 having an ONO (oxide / nitride / oxide) structure is formed in the trench with 100 ℓ of SiO 2.
It was formed to a thickness equivalent to ₂ . Through the heat treatment process, the n ⁺ diffusion layer 13 was formed by diffusing into the P-type silicon substrate 1 through the window where the sidewall oxide film 5 was removed. The n ⁺ diffusion layer 13 serves as a source, and the charge storage electrode 9 and the transfer transistor are connected. Polysilicon is deposited to a thickness of about 3,000 Å and doped with POCl ₃ , and then polysilicon with a thickness of 2 μm or more is deposited.
Doped with Cl ₃ . Next, the polysilicon layer 12 was formed by overetching the polysilicon up to the portion where the device is formed by an etch back process.

FIG. 9 shows a step of forming a word line. After removing the silicon nitride side wall spacers 6, the silicon nitride film 3 and the oxide film 2 on the upper surface of the element formation portion by wet etching, TCA (trichloroethane) is added in a small amount at 1,000 ° C. in an O ₂ atmosphere. Gate oxide film 14
Was grown to a thickness of about 100 to 200Å. Next, polysilicon was deposited to a thickness of about 3,000 Å, doped with POCl ₃ , and etched to that thickness by RIE. The word line 15 which is also used as the gate electrode is formed by the steps described above.

Then, As ions were implanted at an acceleration voltage of 60 keV and a dose of 5 × 10 ¹⁵ / cm ² and heat-treated at 950 ° C. for 30 minutes to form the drain 16. Further LTO
A (low temperature oxide film) 18 was deposited to a thickness of about 7,000 Å, and a bit line 17 was formed on the LTO.

FIG. 10 is a cross-sectional view of a DRAM cell manufactured according to the above steps.

FIG. 11 is a sectional view of a completed DRAM cell having a stack-trench structure, in which 1 is a silicon substrate,
Reference numeral 7 is a P ⁺ diffusion layer, 9 is a charge storage electrode, 11 is a capacitor dielectric, 13 is a source n ⁺ diffusion layer, 15 is a word line also used as a gate, 16 is a drain, 1
Reference numerals 7 denote bit lines, respectively.

FIG. 12 shows a layout pattern of a DRAM cell having a stack-trench structure, 20 is a word line, 21 is a bit line, 22 is a contact portion of the bit line,
Reference numeral 23 is a trench, and 24 is a lateral contact portion.

In the stack-trench structure DRAM cell having the vertical transistor of the present invention, a trench is formed in the silicon substrate 1 to form a stack type capacitor structure around the silicon pillar, and silicon nitride is formed on the upper portion of the silicon pillar. A vertical transfer transistor is formed by using a sidewall spacer 6, and a storage capacitor and a transfer transistor are located below and above a silicon pillar, respectively, and a locally doped n ⁺ diffusion is performed. By connecting with the layer 13 while being separated from the adjacent cell by a trench, it is applicable to a DRAM cell having an integration degree of 64M or more, as well as having stable operation characteristics.

13 to 22 show a manufacturing process of another embodiment of the present invention.

As shown in FIG. 13, a P-type silicon substrate 1
After forming an oxide film 102 with a thickness of about 250 Å on 01, a silicon nitride film 103 is deposited to a thickness of about 1,000 Å, and an oxide film 1 with a thickness of about 800 Å is formed thereon by a CVD method.
04 was deposited. 3 in an H ₂ / O ₂ atmosphere at 925 ° C.
0 minute CVD oxide densification (dens
and a masking layer for trench etching was formed. Using this masking layer, the oxide film 104, the silicon nitride film 103, and the oxide film 102 in the portion where the trench is to be formed are sequentially etched by the RIE method (see FIG. 13).

In FIG. 14, trenches are etched to a depth of 5 to 10 μm, and then, in an H ₂ / O ₂ atmosphere at 950 ° C.
The state where the oxide film 105 of about 000 to 2,000 Å is grown is shown.

In FIG. 15, after the oxide film 105 at the bottom of the trench is etched by the RIE method, boron is implanted to separate it from the adjacent cell or P ^{+ is} doped with BN as a source to form the P ⁺ diffusion layer 106. The state where adjacent cells are separated by forming is shown.

FIG. 16 shows that after the photoresist 107 is sufficiently applied, this is used to limit only the portion where the storage electrode and the transistor are connected, and the oxide film 105a on the wall surface is limited.
Shows a state in which is partially defined.

After the oxide film 105a on the wall surface is etched, polysilicon is deposited to a thickness of about 1000Å and POCl _{3 is} added.
Doped in. Next, etching is performed by the RIE method to n ⁺
1 for charge storage of sidewall spacers doped with
08 was formed (see FIG. 17).

Next, description will be made with reference to FIG. A capacitor dielectric film 109 having an ONO (oxide / nitride / oxide) structure is formed on the surface of the charge storage electrode 108 by 100 Å Si.
It was formed to have a thickness equivalent to that of O ₂ . Portion oxide film 105a is removed in the wall by a heat treatment process, i.e. by diffusing the n ⁺ P-type silicon substrate 101 through the window n ⁺
A diffusion layer 112 was formed so that the storage electrode was connected to the source of the transistor. Next, polysilicon is deposited to a thickness of about 3,000 Å and doped with POCl ₃ , and then polysilicon with a thickness of 2 μm or more is deposited on the POC.
l ₃ doped and polysilicon 1 inside the trench
Fully filled with 10.

Next, description will be made with reference to FIG. After etching back the polysilicon 110 and leaving the polysilicon 110 which is the plate of the capacitor only inside the trunch, the polysilicon is oxidized in an atmosphere of H ₂ / O ₂ at about 900 ° C. and the thickness of about 200 Å An oxide film was formed. Next, a CVD oxide film 111 was deposited to a thickness of about 1 μm, and a portion where an epitaxial layer was grown was limited and dry etching was performed by the RIE method.

Referring to FIG. 20, a silicon single crystal 113 was grown to a thickness of about 1 μm in the portion excluding the trench by using the SEG (selective epitaxial growth) technique. After lapping, arsenic ions were implanted and heat-treated at about 950 ° C. to form the drain 114 of the vertical structure transfer transistor.

As shown in FIG. 21, a silicon single crystal 113 is formed.
CVD oxide film 11 on all parts except where
After removing all 1 by wet etching, the gate oxide film 115 was grown to a thickness of about 100 to 200 Å at 1,000 ° C. in an O ₂ atmosphere containing a small amount of TCA.

As shown in FIG. 22, polysilicon is deposited on the upper surface of the gate oxide film 115 to a thickness of about 3,000 Å,
After doping with POCl ₃ , the word line 116 was formed by etching to the thickness by RIE. After depositing the low temperature oxide film 117 to a thickness of about 7,000 Å, form a bit line 118 with a metal of Al on it
The RAM cell is completed.

FIG. 23 is a sectional view of a DRAM cell having a stack-trench structure completed by the above method, and FIG. 24 shows a layout pattern of a DRAM cell having a stack-trench structure using the SEG technique. It is a thing. In FIG. 24, 120 is a word line, 121 is a bit line, 122 is a contact portion of the bit line,
Reference numerals 123 respectively indicate trenches.

Stack using the SEG technology of the present invention
A DRAM cell having a trench structure has a good SGTDR by using a stack-trench type capacitor.
The soft error is lower than that of the AM cell and the reliability is excellent. By locally doping only a part of the silicon pillar to connect the transfer transistor and the storage capacitor, the transfer transistor can be connected to the P-type silicon substrate. It is possible to reduce the floating phenomenon and to provide stable operation characteristics.

[0036]

As described above, according to the present invention, it is possible to realize a DRAM having a stack trench structure which is highly reliable, has stable operation characteristics, and can be applied to a DRAM of 64 M or more.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a cell having a conventional CTT structure.

FIG. 2 is a cross-sectional view of a cell having a conventional SGT structure.

FIG. 3 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing process of an embodiment of a DRAM cell according to the present invention.

FIG. 11 is a cross-sectional view of an embodiment of a DRAM cell having a stack-trench structure completed according to the present invention.

FIG. 12 is a schematic view showing a layout pattern of an embodiment of a DRAM cell having a stack-trench structure completed according to the present invention.

FIG. 13 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 17 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 18 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 20 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 21 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 22 is a cross-sectional view showing the manufacturing process of another embodiment of the DRAM cell according to the present invention.

FIG. 23 is a sectional view of another embodiment of the DRAM cell according to the present invention.

FIG. 24 is a schematic diagram showing a layout pattern of another embodiment of the DRAM cell according to the present invention.

[Explanation of symbols]

1,101 Silicon substrate 5,105 Oxide film 9,108 Charge storage electrode 11,109 Capacitor dielectric 13,112 n ⁺ Diffusion layer (source) 14,115 Oxide film 15,116 Word line (gate) 16,114 Drain

Continued front page    (72) Inventor Lee Guiyu Hong             Gajyon-dong, Yousung-gu, Daejeon, South Korea               236-1 (72) Inventor Kim Daeyoung             Sambuk, Taiping-dong, Jung-gu, Daejeon, South Korea             Apartment 27-37

Claims (10)

[Claims] 1. A storage electrode formed in the form of a stack trench on an oxide film formed along an inner sidewall of a trench except an upper end portion of a trench formed in a P-type silicon substrate, and a surface of the storage electrode. A storage capacitor formed of a plate formed to fill the inside of the trench except the upper end of the trench and a capacitor dielectric formed on the upper surface of the storage electrode; A source connected to a storage electrode, a gate oxide film formed along the inner side wall of the trench upper end to the trench upper end, and a word line that is a gate electrode formed on the gate oxide film,
A stack-trench structure DRAM cell having a vertical transistor including a vertical transfer transistor including the trench and a drain formed on a silicon surface between the trenches. 2. The capacitor dielectric has an S of 100 Å.
_2. The stack-trench structure DRAM cell according to claim 1, wherein the DRAM cell is formed of an ONO (oxide film / nitride / oxide) structure having a thickness equivalent to that of iO ₂ . 3. The storage electrode is polysilicon deposited,
The stack-trench structure DRAM cell according to claim 1, wherein the DRAM cell is formed by doping with POCl ₃ . 4. The source of the transistor comprises an n ⁺ diffusion layer formed so that n-type impurities in the storage electrode are diffused through a window formed by removing a sidewall oxide film on the upper surface of the storage electrode. 4. The method according to claim 1, wherein
Of the stack-trench structure according to any one of 1.
AM cell. 5. The plate is deposited with polysilicon,
The stack according to claim 1, wherein the stack is formed by doping with POCl _3.
DRAM cell with a trench structure. 6. The gate oxide film has a thickness of 100 to 80.
6. The stack-trench structure DRAM cell according to claim 1, wherein the DRAM cell is 0Å. 7. The stack-trench structure according to claim 1, further comprising a P ⁺ diffusion layer formed at the bottom of the trench to separate it from an adjacent cell. DRAM cell. 8. The stack-trench structure DRAM cell according to claim 1, wherein the drain comprises an n ⁺ diffusion layer formed by ion-implanting As ions. 9. The drain according to claim 1, wherein the drain is formed on a surface of a silicon single crystal, and the silicon single crystal is grown on a portion excluding the trench region by a selective epitaxial growth method. The stack-trench structure DRAM cell according to any one of items. 10. The stack according to claim 9, wherein the silicon single crystal has a thickness of about 1 μm.
DRAM cell with a trench structure.