JPH053022B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention is built into a microcomputer, etc.
It relates to a serial interface circuit that performs serial data input/output with an external device (another computer or peripheral device) under the control of a CPU. [Prior Art] FIG. 3 is a block diagram showing the configuration of a conventional example of this type of serial interface circuit, FIG. 4 is a timing chart of this conventional example, and FIGS. FIG. 3 is a diagram showing a connection form between built-in single-chip microcomputers. The shift register 38 consists of eight D-type flip-flops 3 to 10, and when receiving data, it synchronizes serial data input from the outside via the input terminal SI and the input buffer 1 with the driving clock signal φ ₁ (output of the NOR gate 17). After receiving the 8-bit data, it is sent to the internal bus 20 according to instructions from the CPU (not shown). Also, when sending data,
It receives parallel data sent via internal bus 20, sequentially transfers it as serial data in synchronization with clock signal _φ1 , and outputs it from output terminal SO via data latch 36 and output buffer 2. The clock counter 18 counts the number of pulses of the driving clock signal _φ1 of the shift register 38 during data transmission/reception, and outputs an interrupt signal f at the eighth count.
Outputs and resets the count value. The flip-flop 19 is set by the start signal g input from the CPU at the time of transmission, and is set by the interrupt signal f.
It is reset by The output buffer 14 is turned on when transmitting and outputs the inverted clock signal ₁ , and is turned off when receiving. nand gate 15
is the internal clock signal CK ₁ and flip-flop 1.
It inputs the Q output of CK 9 and outputs an inverted clock signal ₁ of the internal clock signal CK ₁ via the output buffer 14 during transmission. The NOR gate 17 receives the external clock signal a that has arrived from the outside via the clock terminal during reception, and receives the inverted clock signal output from the output buffer 14 during transmission.
It inputs CK ₁ and outputs the drive clock signal φ ₁ for the shift register in both cases. When the flip-flop 19 is reset by the interrupt signal f, the NOR gate 17 inputs a signal obtained by inverting its Q output by the inverter 16, holds the output at a low level, and stops outputting the drive clock signal _φ1 . The output control circuit 11 and the clock control circuit 12 are
The output buffer 2 and output buffer 14 are turned on and off according to instructions from the CPU, respectively. The input terminal SI, the output terminal SO, and the clock terminal are all connected to the internal bus, and their logic levels can always be read by the CPU. Next, the operation of this serial interface circuit will be explained. (1) When receiving data First, the output control circuit 11 and clock control circuit 12 receive data sent via the internal bus 20.
Output buffer 2, 1 according to instructions from CPU
4 are respectively turned off. Next, a high level start signal g is input to the set terminal S of the flip-flop 19, and the flip-flop 19
Q output becomes high level. In this state, the external clock signal a is input to the clock terminal, and the 8-bit input data c is input to the input terminal SI. Then, the drive clock signal φ ₁ is output from the NOR gate 17, and the D-type flip-flops 3 to 10 receive the external clock signal a.
rising edge (falling edge of clock signal _φ1 )
The D input is latched in synchronization with the clock signal _φ1 , and when the clock signal φ1 is at low level, this data is held, and the Q output is transferred to the next stage at the falling edge of the external clock signal a (the rising edge of the clock signal _φ1 ). The data c is outputted to flip-flops 4 to 10 and data latch 13, respectively, and data c is sequentially transferred. The clock counter 18 counts the number of rising and falling edges of the clock signal _φ1 , and resets the flip-flop 19 at the eighth falling edge. Then, the Q output of the flip-flop 19 is inverted and becomes a low level, and the driving clock signal _φ1 from the NOR gate 17 is stopped, thereby stopping the data transfer of the shift register. On the other hand, the interrupt signal f output from the clock counter 18 is sent to the CPU, and when the CPU confirms the interrupt signal f, it reads the data of each D-type flip-flop 3 to 10 via the internal bus 20. Further, the level of external clock signal a from the clock terminal is fixed at high level. (2) At the time of data transmission First, transmission data sent via the internal bus 20 is set in each flip-flop 3-10 in parallel. Next, the output control circuit 11,
The clock control circuit 12 turns on the output buffers 2 and 14 according to instructions from the CPU, and a high-level start signal g is input to the set terminal S of the flip-flop 19. Then, the internal clock signal _CK1 is outputted from the clock terminal via the output buffer 14 to the outside, and is also input to the NOR gate 17, from which the drive clock signal _φ1 is outputted.
The D-type flip-flops 3 to 10 shift data in accordance with the drive clock signal φ ₁ synchronized with the rise of the internal clock signal CK ₁ , as in the case of the external clock a described above, and the data latch 36 shifts data according to the output of the D-type flip-flop 10. is the falling edge of the internal clock a of the clock terminal (the rising edge of the driving clock signal _φ1 )
This output data e is outputted via the output terminal SO. The clock counter 18 closes the flip-flop 19 at the eighth falling edge of the clock signal _φ1 , as in the case of reception.
and stops the transfer of the shift register 38. On the other hand, the interrupt signal f is sent to the CPU,
Completion of data transfer is confirmed. Further, the level of the clock terminal is fixed at high level. This serial interface circuit consists of two single-chip microcomputers 31a,
It is also possible to simultaneously transmit and receive data between three or more single-chip microcomputers 31c, 31d, . . . 31 (Fig. 5a).
It is also possible to transmit and receive data during the period e via the serial bus 32 (FIG. 5b).
In the case of FIG. 5a, the output buffers 2 of the two single-chip microcomputers 31a and 31b are both conductive and transmit and receive data between them at the same time, and in the case of FIG. Of the plurality of single-chip microcomputers 31c to 31e, one
The output buffers 2 of one computer are turned on and transmit data, and the output buffers 2 of the other ICs are turned off and only receive data. [Problems to be Solved by the Invention] For example, in the conventional serial interface circuit described above, after transmitting 8-bit data, 1-bit data (ACK: acknowledgment signal) indicating whether or not the data was correctly received is sent to the receiving side. When an acknowledgment signal needs to be input from the receiver, it is necessary to output the pulse necessary to send an acknowledge signal to the receiving side, but since the total number of pulses to be transferred at one time is determined by a clock counter, this pulse is As a countermeasure to this problem, it is possible to control the total number of clocks by using a programmable clock counter, but this has the disadvantage that the configuration of the clock counter becomes complicated and the number of elements increases. . [Means for Solving the Problems] When transmitting data, the serial interface circuit of the present invention sequentially receives serial data sent from an external device through a data input terminal in synchronization with a drive clock signal, and transmits the data. A shift register that transfers the transmission data input from the data bus onto the bus and serially outputs the transmission data input from the data bus in synchronization with a driving clock signal during data transmission, and transmits it to an external device via a data output terminal; A drive clock that generates a drive clock signal for the shift register by using an external clock signal sent from the external device or an internal clock signal generated inside a microcomputer or the like having a built-in serial interface circuit. A signal generation circuit receives the internal clock signal and a signal sent separately via a bus line under the control of the CPU, selectively outputs one of the inputs under the control of the control signal, and outputs one of the inputs separately under the control of the control signal. It has a latch circuit that can transmit its output to an external device via a terminal. [Operation] In this way, by providing the second flip-flop and outputting the clock signal requesting the acknowledge signal from the CPU via the internal bus after data transmission from the shift register is completed, the acknowledge signal from the receiving side can be received. can. [Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the structure of one embodiment of the serial interface circuit of the present invention, and FIG. 2 is a circuit diagram showing the specific circuit structure of the clock output flip-flop 22 of this embodiment. The serial interface circuit of this embodiment is different from the NAND gate 1 in the conventional example shown in FIG.
5, internal clock CK ₁ , internal bus 20
Let the signals h from the CPU that have passed through I ₁ and I ₂ respectively,
A clock output flip-flop 22 is provided which selectively outputs each input CK ₁ and h according to a control signal φ ₂ inputted separately from the CPU and a control signal φ ₃ which is the Q output of the flip-flop 19. Clock output flip-flop 22 consists of inverters 23, 24, AND gates 25-28, and NOR gates 29, 30, as shown in FIG. This clock output flip-flop 22 is
When the control signal φ ₃ is “1” and the control signal φ ₂ is “0”, the outputs of the AND gates 26 and 27 are fixed to “0”, while the inputs I ₁ and I from the AND gates 25 and 28 are The inverted signals of ₁ are outputted and latched by the latches made up of NOR gates 29 and 30, and a Q output having the same phase as the input _I1 is obtained. When the control signals φ ₃ and φ ₂ are both “0”, the outputs of the AND gates 25 to 28 do not change, and the previous state is maintained. Also, the control signal φ ₃ is “0”, the control signal φ ₂
When is "1", the outputs of AND gates 25 and 28 are fixed to "0", and the outputs of AND gates 26 and 27 are fixed to "0".
The inverted signals of inputs I ₂ and I ₂ are output from
It is latched by a latch circuit consisting of NOR gates 29 and 30, and a Q output having the same phase as the input _I2 is obtained. Table 1 is a logic table for the clock output flip-flop 22 described above.

〔Effect of the invention〕

As explained above, the present invention provides a clock output flip-flop (second flip-flop) with a simple configuration, and outputs a control pulse via the internal bus and the clock output flip-flop after data transmission from the shift register is completed. This has the effect of receiving an acknowledgment signal from the receiving side.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the serial interface circuit of the present invention, FIG. 2 is a circuit diagram showing the specific circuit configuration of the clock output flip-flop 22 of this embodiment, and FIG. Figure 4 is a block diagram of a conventional example of the Ace circuit, and Figure 4 is a timing chart showing the operation of the conventional example.
Figures a and b are diagrams showing how single-chip microcomputers each having a built-in serial interface circuit are connected to each other. 1...Input buffer, 2, 14...Output buffer, 3-10...D-type flip-flop, 11...
...Output control circuit, 12...Clock control circuit, 1
3... Data latch, 16, 23, 24... Inverter, 17, 29, 30... Noah gate, 18
...Clock counter, 19...Flip-flop, 20...Internal bus, 22...Clock output flip-flop, 25-28...And gate,
38...Shift register, SI...Input terminal, SO
...clock terminal, ...clock terminal, CK ₁
...Internal clock signal, φ...Clock signal,
φ ₂ , φ ₃ ...control signals. a...Clock signal input to the clock terminal, c...Input data to the input terminal SI, e...Output data to the output terminal SO, f
...Interrupt signal, g...Start signal, h...Input signal from internal bus, i...Output data of D-type flip-flop 10.

Claims (1)

[Claims] 1 Built into a microcomputer, etc., a CPU
A serial interface circuit that inputs and outputs serial data to and from an external device under the control of A shift register that sequentially receives and transfers data onto a data bus, and when transmitting data, serially outputs transmission data input from the data bus in synchronization with a driving clock signal, and transmits it to an external device via a data output terminal. The driving clock for the shift register is then controlled by using an external clock signal sent from the external device via the clock terminal or an internal clock signal generated inside a microcomputer or the like having a built-in serial interface circuit. A drive clock signal generation circuit that generates a signal receives the internal clock signal and a signal separately sent via a bus line under the control of the CPU, and selectively selects one of the inputs under the control of a control signal. and a latch circuit capable of outputting an output to an external device via the clock terminal and transmitting the output to an external device.