JPH05303445A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In a one-chip microcomputer, it is possible to program the circuit block that goes into the standby state in the standby mode in the product state, and only the desired circuit block goes into the standby state according to the user's application. The optimum setting is made possible to minimize the power consumption. A plurality of circuit blocks (12, 13, 14), a clock generation circuit (11) for generating system clock signals (φ1, φ2) for supplying to the plurality of circuit blocks, a clock generation circuit and a plurality of circuit blocks. A clock control circuit which is inserted corresponding to each system clock supply path between at least two circuit blocks of the circuit blocks and controls enable / disable of supply of the system clock signal according to a standby control signal programmable by a user. 16 and 17 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to, for example, a one-chip microcomputer (one-chip microcomputer).

[0002]

2. Description of the Related Art A conventional one-chip microcomputer has a standby function of stopping supply of a system clock to a predetermined circuit block determined by a hard wafer in a standby state. This standby function cannot meet the demands of many users because the circuit block to be in the standby state is fixed on the hard wafer. For example, as a standby function of a one-chip microcomputer that incorporates a timer circuit unit and a serial circuit unit, one user requests that only the timer circuit unit be put in the standby state in addition to the CPU unit, and another user needs the CPU unit and others. May request to put only the serial circuit unit into the standby state. In this case, normally, the manufacturer provides products (two types in this example) that match the specifications of each user, but each user has to put up with a product in which neither the timer circuit unit nor the serial circuit unit is in the standby state. Sometimes used. Figure 5
FIG. 7 is a block diagram showing an example of a conventional one-chip microcomputer.

In this one-chip microcomputer, 51 is a clock generation circuit, 52 is a CPU (central processing unit),
Reference numeral 53 is a timer circuit section, and 54 is a serial circuit section connected to a serial port. Reference numeral 55 denotes a resonator connected to the clock generation circuit, which is externally attached to the one-chip microcomputer. The clock generation circuit 51 generates two-phase system clock signals φ1a and φ2a and two-phase system clock signals φ1b and φ2b.

In this one-chip microcomputer, the clock signals φ1a and φ2a are supplied to the CPU section 52 and the serial circuit section 54, respectively, and the clock signals φ1b and φ2b are supplied to the timer circuit section 53 during normal operation. And
In the standby mode, the CPU section 52 and the serial circuit section 54 are in the standby state because the supply of the clocks φ1a and φ2a is stopped, but the timer circuit section 53 is in the standby state because the clock signals φ1b and φ2b are supplied. Don't FIG. 6 is a block diagram showing another example of a conventional one-chip microcomputer.

This one-chip microcomputer differs from the one-chip microcomputer shown in FIG. 5 in the following points. That is, during normal operation, the clock signals φ1a and φ2a are supplied to the CPU unit 52 and the timer circuit unit 53, respectively, and the clock signals φ1b and φ2b are supplied to the serial circuit unit 54. Then, in the standby mode, the CPU section 52 and the timer circuit section 53 are in the standby state because the supply of the clocks φ1a and φ2a is stopped, but the serial circuit section 5
The clock signal 4 is supplied with the clock signals φ1b and φ2b, so that it does not enter the standby state.

[0006]

As described above, the standby function of the conventional one-chip microcomputer cannot meet the demands of many users because the circuit block to be in the standby state is fixed on the hard wafer. There was a problem.

The present invention has been made to solve the above problems, and it becomes possible to selectively control a circuit block which is in a standby state in a standby mode in a product state, and it is possible to select a desired circuit block according to a user's application. It is an object of the present invention to provide a semiconductor integrated circuit that can be optimally set so that only a circuit block is in a standby state and that power consumption can be minimized.

[0008]

A semiconductor integrated circuit according to the present invention includes a plurality of circuit blocks, a clock generation circuit for generating a system clock signal to be supplied to the plurality of circuit blocks, and the clock generation circuit. And corresponding at least two circuit blocks among the plurality of circuit blocks are inserted corresponding to the respective system clock supply paths, and the system clock signal is effectively supplied according to a user programmable standby control signal. / A clock control circuit for controlling invalidation.

[0009]

In the normal operation in the product state, each clock control circuit passes the system clock signal, so that the system clock signal is supplied to each corresponding circuit block.

On the other hand, in order to set only some circuit blocks to the standby state in the standby mode in the product state, a programmable standby control signal by the user is given to some clock control circuits. The clock control circuit may be controlled so that the supply of the clock signal to the part of the circuit blocks becomes invalid. In this case, the remaining circuit blocks do not enter the standby state.

As a result, it is possible to make an optimum setting so that only the desired circuit block enters the standby state according to the user's application, and it is possible to minimize power consumption.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a block configuration of a one-chip microcomputer according to one embodiment of the present invention.

In this one-chip microcomputer, the clock generation circuit 11 has a two-phase system clock signal φ 1,
φ2 is generated, and the system clock signal is supplied to a plurality of circuit blocks via the system clock supply path.
In this example, the plurality of circuit blocks are the CPU unit 1
2, a timer circuit unit 13, and a serial circuit unit 14 connected to the serial port. The resonator 15 connected to the clock generation circuit 11 is externally attached to the one-chip microcomputer.

Further, a clock control circuit is inserted corresponding to each system clock supply path between the clock generation circuit 11 and at least two circuit blocks (macro cells) of a plurality of circuit blocks. .. In this example, the first clock control circuit 16 is inserted in the system clock supply path between the clock generation circuit 11 and the timer circuit unit 13, and the system between the clock generation circuit 11 and the serial circuit unit 14 is inserted. The second clock control circuit 17 is inserted in the clock supply path.

These clock control circuits 16 and 17
Controls the enable / disable of the supply of the system clock signals .phi.1 and .phi.2 in response to a user programmable standby control signal SC.

In the one-chip microcomputer of FIG. 1, during normal operation in the product state, the clock control circuits 16 and 17 control the supply of the system clock signals φ1 and φ2 to the effective state, so that the CPU section 12, The system clock signals φ1 and φ2 are supplied to the timer circuit unit 13 and the serial circuit unit 14, respectively.

On the other hand, in the standby mode in the product state, in order to set only the timer circuit section 13 in the standby state, a standby control signal (macrocell stop signal) is given to the first clock control circuit 16. , System clock signals φ 1, φ for the timer circuit unit 13
The first clock control circuit 16 may be controlled so that the supply of 2 is invalid. In this case, since the system clock signals φ1 and φ2 are supplied to the serial circuit section 14, the serial circuit section 14 does not enter the standby state.

Further, in order to set only the serial circuit section 14 to the standby state in the standby mode, a user programmable control signal is applied to the second clock control circuit 17 so that the system for the serial circuit section 14 can be controlled. The second clock control circuit 17 may be controlled so that the supply of the clock signals φ1 and φ2 becomes invalid. In this case, the timer circuit unit 13 does not enter the standby state because the system clock signals φ1 and φ2 are supplied.

Further, in the standby mode, in order to set the timer circuit unit 13 and the serial circuit unit 14 to the standby states, a user programmable control signal is supplied to each clock control circuit 16 and 17. System clock signal φ for each of the timer circuit unit 13 and the serial circuit unit 14
The clock control circuits 16 and 17 may be controlled so that the supply of 1 and φ2 becomes invalid.

That is, according to the one-chip microcomputer of the above embodiment, during the normal operation in the product state, the clock control circuits 16 and 17 cause the system clock signal φ 1 to the corresponding timer circuit section 13 and serial circuit section 14 respectively.
, Φ2 is in the valid state, the timer circuit section 13 and the serial circuit section 14 are in the operating state. On the other hand, in order to set only some of the circuit blocks 13 or 14 to the standby state when in the standby mode in the product state, the user programmable control signal is set to some of the clock control circuits 16 or 1.
7 to control the clock control circuit 16 or 17 so that the supply of the clock signals .phi.1 and .phi.2 to the partial circuit block 13 or 14 becomes invalid. In this case, the remaining circuit blocks do not enter the standby state.

As a result, the optimum setting can be made so that only the desired circuit block is in the standby state according to the user's application, and the power consumption can be minimized. FIG. 2 shows each clock control circuit 16 in FIG.
17 is a circuit diagram representatively showing one of 17 examples. FIG.

In this clock control circuit, in the standby mode, the two-phase system clocks φ1 and φ2 supplied to the corresponding circuit block are inactive level "L".
So that the system clocks φ1 and φ2 for the timer circuit unit 13 (or the serial circuit unit 14) are masked by the standby control signal SC.
Is configured to disable the supply of.

That is, the system clocks φ1 and φ2 supplied from the clock generation circuit 11 are input to the respective one input terminals of the two AND gates 21 and 22, respectively,
The standby control signal is inverted by the inverter circuit 23, and the inverted control signal is applied to the two AND gates 21,
It is input to the other input terminal of 22 and the respective outputs of the two AND gates 21 and 22 are supplied to the timer circuit section 13 (or the serial circuit section 14).

In this clock control circuit, when the standby control signal is in the inactive state ("L" level), the output signal of the inverter circuit 23 becomes "H" level, and the system clocks φ1 and φ2 pass. On the contrary,
When the standby control signal is in the active state (“H” level), the output signal of the inverter circuit 23 becomes “L” level, each output of the two AND gates 21 and 22 becomes “L” level, and the timer The circuit unit 13 (or the serial circuit unit 14) enters the standby state. FIG. 3 is a circuit diagram representatively showing another example of each of the clock control circuits 16 and 17 in FIG.

In the standby mode, the clock control circuit sets the standby control data to a predetermined logic level and latches it in synchronization with the clocks φ1 and φ2 to generate the standby control signal SC.
The timer circuit section 13 is masked by the standby control signal SC so that the outputs of the two-phase clocks φ1 and φ2 supplied to the circuit block corresponding to the clock control circuit have complementary logic levels. The supply of the system clocks φ1 and φ2 to (or the serial circuit unit 14) is disabled.

That is, the system clocks φ1 and φ2 supplied from the clock generation circuit 11 correspond to the first clocks, respectively.
Is input to one of the input terminals of the AND gate 31 and the OR gate 32. The write control signal and the clock .phi.1 input are ANDed by the second AND gate 34 to generate the latch control signal. In the master flip-flop circuit 33, standby control data input from the internal data bus of the one-chip microcomputer is input to the data input terminal D, the latch control signal is input to the latch control input terminal LE, and the data output terminal thereof is output. Q output is slave
The data is input to the data input terminal D of the flip-flop circuit 35. In this slave flip-flop circuit 35, the clock φ 2 input is input to the latch control input terminal LE, and the output of the data output terminal Q thereof becomes the standby control signal SC. The standby control signal SC is directly input to the other input terminal of the OR gate 32 and is inverted by the inverter circuit 36 to be input to the first AND gate 31.
Input to the other input terminal of. Then, the outputs of the first AND gate 31 and the OR gate 32 are supplied to the timer circuit unit 13 (or the serial circuit unit 14). FIG. 4 is a timing waveform diagram showing an operation example of the clock control circuit of FIG. Next, an operation example of the clock control circuit of FIG. 3 will be described.

At the start of the standby mode, the write control signal becomes active level "H". If the clock φ1 input becomes active level "H" while the write control signal is at "H" level, the output (latch control signal) of the second AND gate 34 becomes active level "H". At this time, if the standby control data is set to the active level "H", the above "H" level is latched by the master flip-flop circuit 33, and thereafter, when the clock φ2 input becomes the active level "H", The output data (“H” level) of the master flip-flop circuit 33 is latched by the slave flip-flop circuit 35, and the output data Q (standby control signal SC) of the slave flip-flop circuit 35 becomes the active level “H”. ..

At the end of the standby mode, the write control signal and the clock φ1 input become active level "H", and the output of the second AND gate 34 (latch control signal).
Becomes the active level "H". At this time, if the standby control data is set to the inactive level "L", the "L" level is latched by the master flip-flop circuit 33, and thereafter, when the clock φ2 input becomes the active level "H". , Master flip-flop circuit 3
3 is latched by the slave flip-flop circuit 35, and the output data (standby control signal SC) of the slave flip-flop circuit 35 becomes the inactive level "L".

[0029]

As described above, according to the present invention, it becomes possible to selectively control the circuit blocks that are in the standby state in the standby mode in the product state, and only the desired circuit block can be selected according to the user's application. It is possible to realize a semiconductor integrated circuit that can be optimized so as to be in a standby state and can minimize power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a one-chip microcomputer according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a clock control circuit in FIG.

FIG. 3 is a circuit diagram showing another example of the clock control circuit in FIG.

4 is a timing waveform chart showing an operation example of the clock control circuit of FIG.

FIG. 5 is a block diagram showing an example of a conventional one-chip microcomputer.

FIG. 6 is a block diagram showing another example of a conventional one-chip microcomputer.

[Explanation of symbols]

11 ... Clock generation circuit, 12 ... CPU section, 13 ... Timer circuit section, 14 ... Serial circuit section, 16 ... First clock control circuit, 17 ... Second clock control circuit, 21,
22, 31, 34 ... AND gate, 23, 36 ... Inverter circuit, 32 ... OR gate, 33, 35 ... Flip-flop circuit, .phi.1, .phi.2 ... Two-phase system clock signal.

Claims (5)

[Claims] 1. A plurality of circuit blocks, a clock generation circuit for generating a system clock signal to be supplied to the plurality of circuit blocks, and at least two of the clock generation circuit and the plurality of circuit blocks. And a clock control circuit that is inserted corresponding to each system clock supply path between the two circuit blocks and that controls enable / disable of supply of the system clock signal according to a standby control signal programmable by a user. A semiconductor integrated circuit characterized by the above. 2. The semiconductor integrated circuit according to claim 1, wherein the plurality of circuit blocks include a central processing unit section, a timer circuit section, and a serial circuit section, which correspond to the timer circuit section and the serial circuit section, respectively. The semiconductor integrated circuit, wherein the clock control circuit is inserted in a system clock supply path for the system. 3. The semiconductor integrated circuit according to claim 1, wherein the standby control signal is in a standby mode.
A semiconductor integrated circuit generated by latching standby control data in synchronization with the system clock. 4. The semiconductor integrated circuit according to claim 1, wherein, in the clock control circuit, a two-phase system clock input to a corresponding circuit block is in an inactive level in a standby mode. A semiconductor integrated circuit characterized by masking so that 5. The semiconductor integrated circuit according to claim 1, wherein the clock control circuit is configured so that two-phase system clock inputs to corresponding circuit blocks have complementary logic levels. A semiconductor integrated circuit characterized by being masked.