JPH05304248A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05304248A JPH05304248A JP3324874A JP32487491A JPH05304248A JP H05304248 A JPH05304248 A JP H05304248A JP 3324874 A JP3324874 A JP 3324874A JP 32487491 A JP32487491 A JP 32487491A JP H05304248 A JPH05304248 A JP H05304248A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- metal
- semiconductor device
- metal insulating
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
(57)【要約】
【目的】パワートランジスタモジュールなどの電力用半
導体装置を対象に、高い放熱性，ノイズ耐量を確保しつ
つ、金属絶縁基板の所要面積を縮減して装置全体の小形
化が図れるように構成した半導体装置を提供する。
【構成】樹脂ケース５に金属絶縁基板１, 該金属絶縁基
板にマウントした半導体チップ（パワートランジスタ）
２, 制御回路部品３, および外部導出端子４を組み込ん
でなる半導体装置において、樹脂ケース内の中段位置に
半導体チップの実装域を欠如して金属絶縁基板の上面域
を覆う中仕切壁５ａを設け、この中仕切壁の上面側に半
導体チップと隔離して外部導出端子, 制御回路部品，お
よびその配線導体を配置するとともに、半導体チップは
金属箔１ｃがパターンニングを施してない金属絶縁基板
の上に放熱用金属板を介してマウントする。
(57) [Abstract] [Purpose] For power semiconductor devices such as power transistor modules, while ensuring high heat dissipation and noise immunity, the required area of the metal insulating substrate can be reduced to reduce the size of the entire device. A semiconductor device configured as described above is provided. [Structure] Metal insulating substrate 1 in resin case 5, semiconductor chip (power transistor) mounted on the metal insulating substrate
2. In a semiconductor device in which the control circuit component 3 and the external lead-out terminal 4 are incorporated, a middle partition wall 5a is provided at a middle position in the resin case to cover the upper surface area of the metal insulating substrate by lacking the mounting area of the semiconductor chip. , The external lead-out terminal, control circuit components, and their wiring conductors are arranged on the upper surface side of this partition wall separately from the semiconductor chip, and the semiconductor chip is on the metal insulating substrate on which the metal foil 1c is not patterned. Mount through a metal plate for heat dissipation.
Description
【０００１】[0001]
【産業上の利用分野】本発明はパワートランジスタモジ
ュールなどを対象とした半導体装置の構成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device structure for a power transistor module or the like.
【０００２】[0002]
【従来の技術】半導体装置の回路基板として、昨今では
製品コスト，加工性，量産性，放熱性などの面から、金
属絶縁基板を採用する例が普及する傾向にある。次に、
パワートランジスタモジュールを例に、金属絶縁基板を
採用した半導体装置の従来構造を図３に示す。図におい
て、１は金属ベース１ａ，良伝熱性の絶縁層１ｂ，金属
箔１ｃを一体化し、かつ金属箔１ｃに回路パターンを形
成した金属絶縁基板、２はパワートランジスタ（ベアチ
ップ）、３は制御回路用の各種部品、４は外部導出端
子、５は樹脂ケースである。ここで、パワートランジス
タ２は放熱用金属板６を介して金属絶縁基板１の金属箔
１ｃにマウントされ、他の部品３，外部導出端子４はそ
れぞれ金属絶縁基板１の回路パターンに振り分け実装し
て半田接合されており、かつパワートランジスタ２との
間がワイヤ７を介して内部接続（ワイヤボンディング）
されている。なお、ベアチップのパワートランジスタ２
はケース５の内部にゲル状充填材を充填するか、あるい
はチップに封止樹脂を，コーティング，ポッティングす
るなどして樹脂封止される。2. Description of the Related Art Recently, as a circuit board for a semiconductor device, an example of using a metal insulating board has become widespread in terms of product cost, workability, mass productivity, and heat dissipation. next,
FIG. 3 shows a conventional structure of a semiconductor device using a metal insulating substrate, taking a power transistor module as an example. In the figure, 1 is a metal insulating substrate in which a metal base 1a, a good heat transfer insulating layer 1b, and a metal foil 1c are integrated, and a circuit pattern is formed on the metal foil 1c, 2 is a power transistor (bare chip), 3 is a control circuit Various parts for use, 4 is an external lead terminal, and 5 is a resin case. Here, the power transistor 2 is mounted on the metal foil 1c of the metal insulating substrate 1 via the metal plate 6 for heat dissipation, and the other components 3 and the external lead-out terminals 4 are separately mounted on the circuit pattern of the metal insulating substrate 1 and mounted. Soldered and internally connected to the power transistor 2 via wire 7 (wire bonding)
Has been done. The bare chip power transistor 2
Is sealed with resin by filling the inside of the case 5 with a gel-like filler or coating or potting the chip with sealing resin.
【０００３】[0003]
【発明が解決しようとする課題】ところで、前記したパ
ワートランジスタモジュールなどの電力用半導体装置
は、その容量がますます増加する傾向にある一方で、半
導体装置を小形化することが設計上での大きな課題とな
っている。かかる点、図３のように全ての回路部品を一
枚の金属絶縁基板上に直接実装した構造では、次のよう
な理由で装置の小形化には限界がある。By the way, while the power semiconductor devices such as the above-mentioned power transistor module tend to have an increasing capacity, it is important to reduce the size of the semiconductor device in terms of design. It has become a challenge. In this respect, in the structure in which all the circuit components are directly mounted on one metal insulating substrate as shown in FIG. 3, there is a limit to downsizing the device for the following reason.
【０００４】（１）金属絶縁基板１の金属箔１ｃをパタ
ーンニングして導体パターンを形成したものでは、互い
に分離した導体パターンの相互間に印加電圧に見合った
絶縁沿面距離を確保する必要がある。特に主回路と制御
回路との間には使用時に大きな電圧差が加わることか
ら、パワートランジスタ２をマウントした導体パターン
と制御回路のチップ部品３を実装した導体パターンとの
間には大きな沿面距離が必要となり、この結果として金
属絶縁基板の所要面積がそれだけ増大して装置全体が大
形化する。(1) In the case where the conductor pattern is formed by patterning the metal foil 1c of the metal insulating substrate 1, it is necessary to secure an insulation creepage distance corresponding to the applied voltage between the conductor patterns separated from each other. .. In particular, since a large voltage difference is applied between the main circuit and the control circuit during use, a large creepage distance exists between the conductor pattern on which the power transistor 2 is mounted and the conductor pattern on which the chip part 3 of the control circuit is mounted. This is necessary, and as a result, the required area of the metal insulating substrate is increased correspondingly and the size of the entire device is increased.
【０００５】（２）また、パワートランジスタ２の通電
に伴う発熱は金属板６，金属絶縁基板１を伝熱してヒー
トシンクに放熱されるわけであるが、前記のように金属
絶縁基板１の金属箔１ｃをパターンニングしてそのパタ
ーンの一部に実装した構造では、パワートランジスタ２
から金属絶縁基板１の金属ベース１ａに至る伝熱路が狭
い範囲に制限されるため十分な放熱性が得られない。そ
こで十分な放熱性を確保するには、金属絶縁基板として
大面積のものを使用することが必要になる。(2) Further, the heat generated by energizing the power transistor 2 is transferred to the heat sink through the metal plate 6 and the metal insulating substrate 1, but as described above, the metal foil of the metal insulating substrate 1 is used. In the structure in which 1c is patterned and mounted on a part of the pattern, the power transistor 2
Since the heat transfer path from the metal base 1a to the metal base 1a of the metal insulating substrate 1 is limited to a narrow range, sufficient heat dissipation cannot be obtained. Therefore, in order to secure sufficient heat dissipation, it is necessary to use a large-sized metal insulating substrate.
【０００６】（３）さらに、同じ金属絶縁基板に主回路
部品，制御回路部品などを並べて実装した構造では、特
に制御回路に対するノイズ耐量が低下する。すなわち、
主回路にパルス状ノイズが侵入すると、金属絶縁基板１
の絶縁層（誘電体）１ｂ，金属箔１ｃの導体パターンを
経由して制御回路部品にノイズ電流が流れる。しかも絶
縁層１ｂは伝熱性を考慮して極薄いのでノイズ電流が大
きくなり、半導体装置が誤動作するおそれがある。(3) Further, in a structure in which main circuit components, control circuit components, etc. are mounted side by side on the same metal insulating substrate, noise immunity particularly to the control circuit is lowered. That is,
When pulse noise enters the main circuit, the metal insulating substrate 1
A noise current flows through the control circuit component via the insulating layer (dielectric) 1b and the conductor pattern of the metal foil 1c. Moreover, since the insulating layer 1b is extremely thin in consideration of the heat conductivity, the noise current becomes large and the semiconductor device may malfunction.
【０００７】本発明は上記の点にかんがみなされたもの
であり、その目的は電力用半導体装置を対象に、高い放
熱性，ノイズ耐量を確保しつつ、金属絶縁基板の所要面
積を縮減して装置全体の小形化が図れるように構成した
半導体装置を提供することにある。The present invention has been made in view of the above points, and an object thereof is to reduce the required area of a metal insulating substrate for a power semiconductor device while ensuring high heat dissipation and noise immunity. An object of the present invention is to provide a semiconductor device configured so as to be downsized as a whole.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に、本発明の半導体装置は、外囲器である樹脂ケース内
の中段位置に半導体チップの実装域を欠如して金属絶縁
基板の上面域を覆う中仕切壁を設け、該中仕切壁の上面
側に外部導出端子, 制御回路部品およびその配線導体を
配置して構成するものとする。In order to achieve the above object, the semiconductor device of the present invention has an upper surface of a metal insulating substrate which lacks a mounting area of a semiconductor chip at a middle position in a resin case which is an envelope. A partition wall covering the area is provided, and the external lead-out terminal, the control circuit component and its wiring conductor are arranged on the upper surface side of the partition wall.
【０００９】また、前記構成の実施態様として、次のよ
うな構成がある。 （１）外部導出端子, 制御回路部品の配線導体をあらか
じめケースの中仕切壁にインサートして一体成形する。 （２）金属絶縁基板の全面域に金属箔を被着させたま
ま、この上に放熱用金属板を介して半導体チップをマウ
ントする。さらに、前記の放熱用金属板は金属絶縁基板
の金属箔の略全面域を覆って伝熱的に接合する。Further, as an embodiment of the above configuration, there is the following configuration. (1) Insert the external lead-out terminal and the wiring conductor of the control circuit component into the partition wall of the case in advance and integrally mold them. (2) With the metal foil adhered to the entire surface of the metal insulating substrate, the semiconductor chip is mounted on the metal foil via the heat radiating metal plate. Further, the heat-dissipating metal plate covers almost the entire area of the metal foil of the metal insulating substrate and is thermally conductively bonded.
【００１０】[0010]
【作用】上記の構成によれば、金属絶縁基板には半導体
チップ（パワーチップ）のみがマウントされ、他の制御
回路部品およびその配線導体，外部導出端子などは全て
金属絶縁基板と隔離し、樹脂ケースの中仕切壁にインサ
ートするなどして配備されている。これにより、まず、
主回路部品である半導体チップと他の回路部品との間の
絶縁耐量はケースの中仕切壁により十分に確保されるの
で、金属絶縁基板上で必要な絶縁沿面距離を確保するな
どの必要がなく、装置全体としての実装密度を高められ
る。また、半導体チップ（パワーチップ）の通電に伴う
発生熱は他の実装部品の配置に阻害されることなく、放
熱用金属板を通じて熱流束が金属絶縁基板の全面域に拡
散して伝熱するので高い放熱性が確保される。加えて、
制御回路のチップ部品などは主回路部品である半導体チ
ップとケースの中仕切壁を隔てて隔離されているので金
属絶縁基板に全ての部品を実装した構成のものと比べて
外来ノイズに対する高い耐量が確保できる。According to the above construction, only the semiconductor chip (power chip) is mounted on the metal insulating substrate, and other control circuit components, their wiring conductors, external lead terminals, etc. are all separated from the metal insulating substrate, and It is deployed by inserting it into the partition wall of the case. With this, first,
Insulation resistance between the semiconductor chip, which is the main circuit component, and other circuit components is sufficiently secured by the partition wall of the case, so there is no need to secure the necessary insulation creepage distance on the metal insulating substrate. The packaging density of the entire device can be increased. In addition, the heat generated by the energization of the semiconductor chip (power chip) is not hindered by the arrangement of other mounting components, and the heat flux diffuses and transfers heat to the entire area of the metal insulating substrate through the metal plate for heat dissipation. High heat dissipation is secured. in addition,
Since the chip parts of the control circuit are isolated by separating the semiconductor chip, which is the main circuit part, from the partition wall of the case, it has a higher resistance to external noise than the structure in which all parts are mounted on the metal insulating board. Can be secured.
【００１１】[0011]
【実施例】以下本発明の実施例を図面に基づいて説明す
る。なお、図中で図３に対応する同一部材には同じ符号
が付してある。 実施例１：図１において、まず樹脂ケース５に組み込ん
だ金属絶縁基板１は、絶縁層１ｂの全面に金属箔１ｃが
形成されたままで、パターンニングされてない状態（通
称「べた」パターン状態と言う）のものが使用され、こ
の金属絶縁基板１の所定位置にパワートランジスタ２が
放熱用金属板（例えば銅板）６を介してマウントされて
いる。一方、樹脂ケース５の内部の中段位置にはパワー
トランジスタ２の実装域を欠如して金属絶縁基板１の上
面域を覆うように中仕切壁５ａを備えており、この中仕
切壁５ａの上面側に制御回路部品３を接続する配線導体
８および外部導出端子４が設置され、かつ制御回路部品
３が配線導体８の上に半田付けされている。なお、外部
導出端子４，配線導体８はケース５をモールド成形する
際にインサートして一体形成するものとする。Embodiments of the present invention will be described below with reference to the drawings. In the figure, the same members corresponding to those in FIG. 3 are designated by the same reference numerals. Example 1 In FIG. 1, first, the metal insulating substrate 1 assembled in the resin case 5 is in a state where the metal foil 1c is still formed on the entire surface of the insulating layer 1b and is not patterned (commonly referred to as a "solid" pattern state). The power transistor 2 is mounted at a predetermined position on the metal insulating substrate 1 via a heat radiating metal plate (for example, a copper plate) 6. On the other hand, an intermediate partition wall 5a is provided in the middle position inside the resin case 5 so as to cover the upper surface area of the metal insulating substrate 1 by lacking the mounting area of the power transistor 2, and the upper surface side of this intermediate partition wall 5a. A wiring conductor 8 for connecting the control circuit component 3 and the external lead-out terminal 4 are installed on the control circuit component 3, and the control circuit component 3 is soldered on the wiring conductor 8. The external lead-out terminal 4 and the wiring conductor 8 are integrally formed by inserting when the case 5 is molded.
【００１２】かかる構成によれば、主回路，制御回路部
品の相互間に必要な絶縁耐量はケース５の中仕切壁５ａ
自身で確保されるので、それだけ高実装密度が可能とな
る。また、パワートランジスタ２での通電に伴う発生熱
は他の部品に邪魔されることなく、金属板６を通じて熱
流束が金属絶縁基板１の全面域に拡散するように伝熱
し、その金属ベース１ａより外部のヒートシンクなどに
放熱する。したがって、小面積の金属絶縁基板でも大電
力容量のパワートランジスタ２に対する高い放熱性を確
保しつつ、しかも装置全体をより小形に構成できる。な
お、制御回路部品３などの通電に伴う発生熱は極僅かで
あり、ケース５の中仕切壁５ａに設置しても実用面で何
等支障はない。また、制御回路部品３などはパワートラ
ンジスタ２，金属絶縁基板１と隔離して中仕切板５ａに
配置されているので、図３の構成と比べて外来ノイズに
対し高いノイズ耐量が得られる。According to this structure, the required amount of dielectric strength between the main circuit and the control circuit components is the partition wall 5a of the case 5.
Since it is secured by itself, higher packaging density is possible. Further, the heat generated by the energization of the power transistor 2 is transferred to the entire area of the metal insulating substrate 1 through the metal plate 6 without being disturbed by other parts, and the heat is transferred from the metal base 1a. Dissipate heat to an external heat sink. Therefore, even with a small-area metal insulating substrate, it is possible to secure a high heat dissipation property for the power transistor 2 having a large power capacity, and further, to make the entire device smaller. The heat generated by the energization of the control circuit component 3 and the like is extremely small, and even if it is installed on the partition wall 5a of the case 5, there is no problem in practical use. Further, since the control circuit component 3 and the like are arranged on the partition plate 5a so as to be separated from the power transistor 2 and the metal insulating substrate 1, a higher noise immunity to external noise can be obtained as compared with the configuration of FIG.
【００１３】実施例２：図２は先記した実施例１をさら
に発展させて放熱性を高めるようにしたものであり、放
熱用金属板６として金属絶縁基板１の金属箔１ｃの略全
面域を覆うような大面積の金属板が組み込まれ、その全
面が金属絶縁基板の金属箔１ｃと伝熱的に接合されてい
る。かかる構成により、通電に伴うパワートランジスタ
２の発生熱は大面積の放熱用金属板６に拡散して金属絶
縁基板１に伝熱するので、それだけ放熱経路の熱抵抗が
低くより高い放熱性が得られるようになる。Second Embodiment: FIG. 2 is a further development of the first embodiment described above to improve the heat radiation property. As a heat radiation metal plate 6, a substantially entire area of the metal foil 1c of the metal insulating substrate 1 is shown. A large-area metal plate covering the above is incorporated, and the entire surface thereof is thermally conductively joined to the metal foil 1c of the metal insulating substrate. With this configuration, the heat generated by the power transistor 2 due to energization is diffused into the large-area heat-dissipating metal plate 6 and transferred to the metal insulating substrate 1, so that the heat resistance of the heat-dissipating path is low and a higher heat-dissipating property is obtained. Will be available.
【００１４】[0014]
【発明の効果】以上述べたように、本発明による半導体
装置の構成によれば、パワートランジスタモジュールな
どの電力用半導体装置を対象に、高い絶縁耐量，ノイズ
耐量を確保しつつ、高実装密度化とともに金属絶縁基板
の所要面積を縮減して装置全体の小形化を図ることがで
きる。As described above, according to the structure of the semiconductor device of the present invention, it is possible to obtain a high packaging density while ensuring a high dielectric strength and noise resistance for a power semiconductor device such as a power transistor module. At the same time, the required area of the metal insulating substrate can be reduced to reduce the size of the entire device.
【図１】本発明の実施例１に対応する半導体装置の構成
断面図FIG. 1 is a configuration cross-sectional view of a semiconductor device corresponding to a first embodiment of the present invention.
【図２】本発明の実施例２に対応する半導体装置の構成
断面図FIG. 2 is a structural cross-sectional view of a semiconductor device corresponding to a second embodiment of the present invention.
【図３】パワートランジスタモジュールを対象とした従
来における半導体装置の構成断面図FIG. 3 is a sectional view of the configuration of a conventional semiconductor device for a power transistor module.
１ 金属絶縁基板 １ａ 金属ベース １ｂ 絶縁層 １ｃ 金属箔 ２ パワートランジスタ（半導体チップ） ３ 制御回路部品 ４ 外部導出端子 ５ 樹脂ケース ５ａ 中仕切壁 ６ 放熱用金属板 ７ ボンディングワイヤ ８ 配線導体 1 Metal Insulation Substrate 1a Metal Base 1b Insulation Layer 1c Metal Foil 2 Power Transistor (Semiconductor Chip) 3 Control Circuit Parts 4 External Lead Terminal 5 Resin Case 5a Partition Wall 6 Heat Dissipation Metal Plate 7 Bonding Wire 8 Wiring Conductor
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9355−4Ｍ Ｈ０１Ｌ 23/12 Ｆ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 9355-4M H01L 23/12 F
Claims (4)
板にマウントした半導体チップ, 制御回路部品, および
外部導出端子を組み込み、半導体チップと制御回路部
品, 外部導出端子との間をワイヤボンディングして内部
接続した半導体装置において、前記ケース内の中段位置
に半導体チップの実装域を欠如して金属絶縁基板の上面
域を覆う中仕切壁を設け、該中仕切壁の上面側に外部導
出端子,制御回路部品，およびその配線導体を配置した
ことを特徴とする半導体装置。1. A resin case, a metal insulating substrate, a semiconductor chip mounted on the metal insulating substrate, a control circuit component, and an external lead terminal are incorporated, and wire bonding is performed between the semiconductor chip and the control circuit component, the external lead terminal. In the internally connected semiconductor device, a middle partition wall is provided at the middle position in the case to cover the upper surface area of the metal insulating substrate by lacking the mounting area of the semiconductor chip, and the external lead terminal is provided on the upper surface side of the middle partition wall. A semiconductor device in which a control circuit component and its wiring conductor are arranged.
導出端子, 制御回路部品の配線導体をケースの中仕切壁
にインサートして一体成形したことを特徴とする半導体
装置。2. The semiconductor device according to claim 1, wherein an external lead-out terminal and a wiring conductor of a control circuit component are inserted into a partition wall of the case and integrally molded.
絶縁基板の全面域に金属箔を被着させたまま、この上に
放熱用金属板を介して半導体チップをマウントしたこと
を特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein a metal foil is deposited on the entire surface of the metal insulating substrate, and a semiconductor chip is mounted on the metal foil via a heat radiating metal plate. Semiconductor device.
用金属板が金属絶縁基板の金属箔の略全面域を覆って伝
熱的に接合されていることを特徴とする半導体装置。4. The semiconductor device according to claim 3, wherein the heat-dissipating metal plate is heat-conductively bonded to cover substantially the entire area of the metal foil of the metal insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3324874A JP2848068B2 (en) | 1991-12-10 | 1991-12-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3324874A JP2848068B2 (en) | 1991-12-10 | 1991-12-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05304248A true JPH05304248A (en) | 1993-11-16 |
| JP2848068B2 JP2848068B2 (en) | 1999-01-20 |
Family
ID=18170604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3324874A Expired - Fee Related JP2848068B2 (en) | 1991-12-10 | 1991-12-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2848068B2 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5686758A (en) * | 1994-05-31 | 1997-11-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having integral structure of case and external connection terminals |
| JPH1174454A (en) * | 1997-06-23 | 1999-03-16 | Asea Brown Boveri Ag | Power semiconductor module with enclosed submodule |
| US6147869A (en) * | 1997-11-24 | 2000-11-14 | International Rectifier Corp. | Adaptable planar module |
| US6166464A (en) * | 1998-08-24 | 2000-12-26 | International Rectifier Corp. | Power module |
| JP2002203940A (en) * | 2001-01-04 | 2002-07-19 | Mitsubishi Electric Corp | Semiconductor power module |
| US6630727B1 (en) * | 1998-03-03 | 2003-10-07 | Infineon Technologies Ag | Modularly expandable multi-layered semiconductor component |
| JP2006179856A (en) * | 2004-11-25 | 2006-07-06 | Fuji Electric Holdings Co Ltd | Insulating substrate and semiconductor device |
| DE4418426B4 (en) * | 1993-09-08 | 2007-08-02 | Mitsubishi Denki K.K. | Semiconductor power module and method of manufacturing the semiconductor power module |
| JP2007329387A (en) * | 2006-06-09 | 2007-12-20 | Mitsubishi Electric Corp | Semiconductor device |
| WO2013187120A1 (en) | 2012-06-13 | 2013-12-19 | 富士電機株式会社 | Semiconductor device |
| JP2015173299A (en) * | 2015-07-06 | 2015-10-01 | 三菱電機株式会社 | semiconductor module |
| US9443784B2 (en) | 2012-03-09 | 2016-09-13 | Mitsubishi Electric Corporation | Semiconductor module including plate-shaped insulating members having different thickness |
| US9887154B2 (en) | 2014-04-21 | 2018-02-06 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the semiconductor device |
| DE112013007390B4 (en) | 2013-08-29 | 2020-06-25 | Mitsubishi Electric Corporation | Semiconductor module, semiconductor device and vehicle |
| CN116435264A (en) * | 2023-06-12 | 2023-07-14 | 江苏宏微科技股份有限公司 | power semiconductor module |
-
1991
- 1991-12-10 JP JP3324874A patent/JP2848068B2/en not_active Expired - Fee Related
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4418426B4 (en) * | 1993-09-08 | 2007-08-02 | Mitsubishi Denki K.K. | Semiconductor power module and method of manufacturing the semiconductor power module |
| US5686758A (en) * | 1994-05-31 | 1997-11-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having integral structure of case and external connection terminals |
| JPH1174454A (en) * | 1997-06-23 | 1999-03-16 | Asea Brown Boveri Ag | Power semiconductor module with enclosed submodule |
| US6147869A (en) * | 1997-11-24 | 2000-11-14 | International Rectifier Corp. | Adaptable planar module |
| US6630727B1 (en) * | 1998-03-03 | 2003-10-07 | Infineon Technologies Ag | Modularly expandable multi-layered semiconductor component |
| US6166464A (en) * | 1998-08-24 | 2000-12-26 | International Rectifier Corp. | Power module |
| JP2002203940A (en) * | 2001-01-04 | 2002-07-19 | Mitsubishi Electric Corp | Semiconductor power module |
| JP2006179856A (en) * | 2004-11-25 | 2006-07-06 | Fuji Electric Holdings Co Ltd | Insulating substrate and semiconductor device |
| JP2007329387A (en) * | 2006-06-09 | 2007-12-20 | Mitsubishi Electric Corp | Semiconductor device |
| US9443784B2 (en) | 2012-03-09 | 2016-09-13 | Mitsubishi Electric Corporation | Semiconductor module including plate-shaped insulating members having different thickness |
| WO2013187120A1 (en) | 2012-06-13 | 2013-12-19 | 富士電機株式会社 | Semiconductor device |
| JP2013258321A (en) * | 2012-06-13 | 2013-12-26 | Fuji Electric Co Ltd | Semiconductor device |
| US9379096B2 (en) | 2012-06-13 | 2016-06-28 | Fuji Electric Co., Ltd. | Semiconductor device |
| DE112013007390B4 (en) | 2013-08-29 | 2020-06-25 | Mitsubishi Electric Corporation | Semiconductor module, semiconductor device and vehicle |
| US11239123B2 (en) | 2013-08-29 | 2022-02-01 | Mitsubishi Electric Corporation | Semiconductor module, semiconductor device, and vehicle |
| US9887154B2 (en) | 2014-04-21 | 2018-02-06 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the semiconductor device |
| JP2015173299A (en) * | 2015-07-06 | 2015-10-01 | 三菱電機株式会社 | semiconductor module |
| CN116435264A (en) * | 2023-06-12 | 2023-07-14 | 江苏宏微科技股份有限公司 | power semiconductor module |
| CN116435264B (en) * | 2023-06-12 | 2023-10-27 | 江苏宏微科技股份有限公司 | Power semiconductor module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2848068B2 (en) | 1999-01-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6029343A (en) | Insulated surface mount circuit board construction | |
| US5767573A (en) | Semiconductor device | |
| US8890310B2 (en) | Power module package having excellent heat sink emission capability and method for manufacturing the same | |
| US5398160A (en) | Compact power module with a heat spreader | |
| US6166464A (en) | Power module | |
| CN110914975B (en) | power semiconductor module | |
| JPH05304248A (en) | Semiconductor device | |
| JPH05175384A (en) | Power semiconductor device | |
| JPH11191603A (en) | Semiconductor integrated circuit device and method of manufacturing the same | |
| US6483706B2 (en) | Heat dissipation for electronic components | |
| JP4208490B2 (en) | Semiconductor power module and manufacturing method thereof | |
| JPH02201949A (en) | Package of semiconductor device | |
| JP2008187145A (en) | Circuit equipment | |
| JPH11307721A (en) | Power module device and method of manufacturing the same | |
| JPH04137756A (en) | Hybrid integrated circuit | |
| US20060220188A1 (en) | Package structure having mixed circuit and composite substrate | |
| JPH05114776A (en) | Bare chip lsi mounting structure | |
| JP2524482B2 (en) | QFP structure semiconductor device | |
| KR20040075683A (en) | Power semiconductor mudule package and method for fabricating the same | |
| EP0804054A1 (en) | Insulated surface mount circuit board construction | |
| JPH05259373A (en) | Power semiconductor device | |
| JP2612468B2 (en) | Substrate for mounting electronic components | |
| JP3048707B2 (en) | Hybrid integrated circuit | |
| JP2583507B2 (en) | Semiconductor mounting circuit device | |
| JP2771567B2 (en) | Hybrid integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071106 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081106 Year of fee payment: 10 |
|
| LAPS | Cancellation because of no payment of annual fees |