JPH05304518A - Pattern detector - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the size of the unique word detection circuit and to provide expandability so that it can cope with changes in the allowable number of unique word errors. [Configuration] Data input from a data input terminal 31 is serial / parallel converted by a shift register 32. The output bits of the shift register 32 are EX-O in advance.
It is compared with the bits set in R gates 35-38.
The output bits of the EX-OR gates 35 to 38 are parallel / serial converted by the shift register 39, and the counter 42
Is supplied to. The counter 42 having the initial value setting input terminal 42 </ b> A for setting the error tolerance is the shift register 3
It is detected whether or not the error amount of the output bit of 9 is less than or equal to the error allowable amount.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern detecting device for detecting a synchronization word of a radio wave used in, for example, a digital cellular telephone.

[0002]

2. Description of the Related Art There is known a digital cellular telephone which uses a digital signal to make a call. When making a call using a digital cellular telephone, two channels, a communication channel and a control channel, are required.

FIG. 4 shows the configuration of physical slots of the communication channel and the control channel. FIG. 4A shows a physical slot for communication, and a ramp time R for transient response.
(4 bits), start symbol SS (2 bits), preamble RR (6 bits), unique word UW (1
6 bits), data and CRC (error detection code) I (196 bits), and guard bit GB (16 bits), totaling 240 bits.

Further, FIG. 4B shows a control physical slot, which includes a transient response ramp time R (4 bits), a start symbol SS (2 bits), and a control signal CAC (6).
2 bits), unique word UW (32 bits), control signal CAC (124 bits), and guard bit GB
It consists of 240 bits in total (16 bits).

In a digital telephone, the beginning of data can be detected by detecting the unique word UW in the digital signal supplied from the transmitting side at the receiving side.

FIG. 5 shows an example of a block diagram of a detection circuit for detecting the unique word UW. In addition,
In this circuit, it is assumed that there is no error tolerance of the unique word UW, and for the sake of simplicity of explanation, the unique word UW
W has a length of 4 bits. In FIG. 5, the shift register 102 stores serial data in the data input terminal 101.
And the clock pulse is input from the clock input terminal 103. In addition, the shift register 10
An H level voltage is supplied to the terminal 2 from the terminal 104.

In the shift register 102, serial / parallel conversion of input data is performed, and its output signal is E
It is supplied to one input terminal of each of the X-OR gates 105, 106, 107 and 108. The H-level voltage is supplied from the terminal 109 to the other input terminals of the EX-OR gates 105 and 107. In addition, the EX-OR gate 106
And the other input terminals of 108 are grounded. In addition, EX
The signal supplied to the other input terminals of the OR gates 105 to 108 is variable according to the transmitted unique word UW.

EX-OR gates 105, 106 and 107
The output signals of 108 and 108 are supplied to a D flip-flop (hereinafter referred to as DFF) 111 via a NOR gate 110. At the same time, the clock pulse from the clock terminal 103 is supplied to the clock input terminal of the DFF 111 via the inverter 112. Make sure that the DFF111 is not preset or cleared.
H level voltage is supplied to the terminals 113 and 114. The output signal of the DFF111 is the unique word UW.
It is output from the output terminal 115 as a detection signal.

In the above circuit, for example, when 4-bit data (0101) is input from the data input terminal 101, "H" is input to one of the input terminals of the EX-OR gates 105 and 107, and the EX-OR gate is input. 106 and 10
“L” is supplied to each of the eight input terminals. Therefore, the output signals of the EX-OR gates 105 to 108 are all "L", and therefore the output signal of the NOR gate 110 is "H". The output signal of the NOR gate 110 is output from the terminal 115 as a unique word UW detection signal via the DFF 11.

When the unique word UW detection signal is "H", it means that the unique word UW supplied from the transmitting side has been detected by the receiving side, which causes the receiving side to detect the start of data on the transmitting side. It becomes possible to detect parts. Further, for example, when an error occurs in the unique word UW and the unique word UW detection signal becomes “L”, the unique word UW supplied from the transmitting side is accurately received by the receiving side. The receiver will not be able to detect the beginning of the data. Therefore, the receiving side cannot decode the signal supplied from the transmitting side. Further, the transmitting side needs to retransmit the same data.

In order to solve the above problem, there is a detection circuit for the unique word UW in which the error tolerance of the unique word UW is, for example, 1 bit or less. An example of a block diagram of this detection circuit is shown in FIG. It should be noted that the pattern of the unique word UW in this circuit is 4 bits (0101) for simplicity of explanation. In FIG. 6, serial data is input to the shift register 117 from the data input terminal 116, and clock pulses are input from the clock input terminal 118. In addition, the H level voltage is applied to the terminal 139 in the shift register 117.
Supplied from

In the shift register 117, serial / parallel conversion of input data is performed, and its output signal is E
It is supplied to one input terminal of each of the X-OR gates 119, 120, 121 and 122. The H-level voltage is supplied from the terminal 123 to the other input terminals of the EX-OR gates 119 and 121. In addition, the EX-OR gate 120
And the other input terminals of 122 are grounded. In addition, EX
The signals supplied to the other input terminals of the -OR gates 119 to 122 are variable according to the transmitted unique word UW.

EX-OR gates 119, 120, 121
The output signal of each of the NOR gate 122 and the NOR gate 122 is
4 and also the inverters 125, 126, 1
NOR gates 129, 130 through 27 and 128,
It is supplied to the input terminals of 131 and 132. The NOR gate 129 includes EX-OR gates 120, 121 and 1
22 output signals are provided. The output signals of the EX-OR gates 119, 121 and 122 are supplied to the NOR gate 130. The NOR gate 131 has an EX-O
The output signals of R gates 119, 120 and 122 are provided. The NOR gate 132 includes the EX-OR gate 11
The output signals of 9, 120 and 121 are provided.

NOR gates 124, 129, 130, 1
The output signals of 31 and 132 are supplied to the OR gate 133. The output signal of the OR gate 133 is the DFF134.
Is supplied to. Further, the clock pulse of the clock input terminal 118 is input to the clock input terminal of the DFF 134 via the inverter 135. Furthermore, DFF13
D is set so that 4 is not preset or cleared.
The H level voltage is applied to the FF134 by the terminals 136 and 137.
Supplied from The output signal of the DFF 134 is output from the terminal 138 as a unique word UW detection signal.

In the above-mentioned circuit, for example, even though the (0101) unique word UW is transmitted from the transmitting side, a 1-bit error occurs, and the 4-bit serial word (from the data input terminal 116 ( 010
0) is input, the output signal of the EX-OR gate 119 is set to "H", and the EX-OR gates 120 to 1
The output signal of 22 is "L". Therefore, the output signals of the NOR gate 129 are "H", and the output signals of the other NOR gates are all "L". Also, the OR gate 1
The output signal of 33 is "H". As a result, the unique word UW detection signal level is set to "H", and the unique word UW is detected.

When a 2-bit error occurs and (0110) is input from the data input terminal 116, the output signal of the OR gate 133 is set to "L". As a result, the unique word UW detection signal 138 is
It is set to "L", and the unique word UW cannot be detected. As described above, in this circuit, the unique word UW
Even if there is an error of 1 bit or less, the unique word UW can be detected.

In the above circuit, an example in which the unique word length is 4 bits is shown, and five NOR gates are used to judge whether or not the unique word UW having an error tolerance of 1 bit or less can be detected. 124, 129, 130, 13
1 and 132 are required. When the unique word UW (32 bits) of the physical slot of the control channel having an error tolerance of 1 bit or less is applied to the unique word detection circuit as shown in FIG. 6, 33 NOR gates are required. .. From this, for the unique word UW having an n-bit length, when the error tolerance is m (n> m) bits, the required number of NOR gates is ( _n C ₀ +
_n C ₁ + ... _n C _m ). Further, if the unique word UW (32 bits) of the physical slot of the control channel having an error tolerance of 2 bits or less is applied to the unique word detection circuit described above, 529 NOR gates are required.

[0018]

As described above, the number of NOR gates required becomes enormous as the unique word UW length is increased and the error tolerance is increased. .. As a result, the circuit scale of the unique word detection circuit becomes large. Also, the number of NOR gates must be adjusted each time the error tolerance is changed.

Therefore, an object of the present invention is to provide a pattern detecting apparatus which has expandability so as to be able to cope with a case where the allowable number of unique word errors is changed and which is downsized.

[0020]

The present invention is for comparing a first shift register for serial / parallel conversion of an input signal with a preset unique word and an output bit of the first shift register. Of the EX-OR gate, a second shift register for performing parallel / serial conversion on the output bit of the EX-OR gate, and a terminal for setting an error allowable amount for the output bit of the second shift register, 2 is a pattern detection device including a counter for detecting whether or not the error of the output bit of the second shift register is less than or equal to the error allowable amount, and an RS flip-flop for outputting the output bit of the counter.

Further, the present invention is a pattern detecting apparatus characterized in that the error allowable amount of the counter is variable.

Further, the present invention is the pattern detecting apparatus, wherein the counter uses clock pulses of (n + 2) times (where n is a unique word length) times the clock period of the input signal.

[0023]

The one input terminal of the EX-OR gate is set so that the output is "L". The unique word is input from the other input terminal of the EX-OR gate. EX-
The output bit of the OR gate is supplied to the counter via the shift register. In the counter, the error tolerance of the unique word is set. The output bit of the EX-OR gate increments the initial value. When the counter value becomes maximum, the unique word undetectable bit is output from the counter.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit block diagram of a digital cellular telephone to which the present invention is applied. At the time of reception, the radio wave received by the antenna 1 (for example, 800M
A predetermined low frequency component (Hz) is extracted by the bandpass filter 4 via the bandpass filter 2 and the transmission / reception changeover switch 3. The low frequency component is amplified by the low noise amplifier 5 and then supplied to the mixer 6. A local oscillator 7 is connected to the mixer 6. In the mixer 6, the low frequency component is mixed with the local signal of the local oscillator 7, and the output of the mixer 6 is converted into the first intermediate frequency.

The first intermediate frequency is the bandpass filter 8
To eliminate local signal spurs and wide area sideband noise. The output signal of the bandpass filter 8 is supplied to the mixer 9. An oscillator 10 is connected to the mixer 9, and the output signal of the bandpass filter 8 is mixed with the output signal of the oscillator 10. The output signal of the mixer 9 is IF amplifier / RSSI as the second intermediate frequency.
It is amplified by the detection circuit 11.

A signal corresponding to the input data is output from the IF amplifier / RSSI detection circuit 11 and demodulated by the demodulator 12. The demodulator 12 outputs the received data and the recovered clock, and the TDMA channel / dechannel coding circuit 13 outputs TD.
De-channel framing is performed by MA (time division multiplexing). The TDMA channel / dechannel coding circuit 13 detects the unique word UW in the data. The output signal of the TDMA channel / dechannel coding circuit 13 is highly efficiently decoded by the ADPCM codec 14, D / A converted by the PCM codec 15, and then output from the speaker 16.

At the time of transmission, the data input from the microphone 17 is transferred to the A /
It is D-converted and highly efficient coded by the ADPCM codec 14. The output signal of the ADPCM codec 14 is
In the TDMA channel / dechannel coding 13, channel framing is performed by TDMA, and the signal is supplied to the quadrature modulator 22 via the modulator 20. In the quadrature modulator 22, the signal supplied from the modulator 20 is subjected to, for example, π / 4 shift QPSK modulation on the carrier signal supplied from the local synthesizer 21. The output signal of the quadrature modulator 22 is mixed with the signal from the local oscillator 7 in the mixer 23 and converted into a predetermined transmission frequency. The output signal of the mixer 23 is amplified to a frequency that can be transmitted by the power amplifier 25 via the filter 24. The output of the power amplifier 25 is the switch 3
And transmitted from the antenna 1 via the filter 2.

Also, a keypad portion 18A for 10 keys,
A display unit 18B made of, for example, liquid crystal for displaying predetermined information is connected to the CPU 19. CP
U19 is connected to the TDMA channel coding / decoding circuit 13 and the like.

FIG. 2 shows a circuit diagram of an example of the pattern detection circuit according to the present invention provided in the TDMA channel coding / decoding circuit 13, and FIG. 3 shows a clock used in the pattern detection circuit. A timing chart of pulses and the like is shown. In this circuit, the allowable error amount of the unique word UW is set to 1 bit or less and the unique word UW pattern is set to 4 bits (0101). In FIG. 2, serial data (see FIG. 3A) is input to the shift register 32 from the data input terminal 31 and the clock input terminal 33.
Clock pulse (see FIG. 3B) is input. In addition, an H level voltage is applied to the terminal 3 of the shift register 32.
Supplied from No. 4.

In the shift register 32, serial / parallel conversion of input data is performed, and its output signal is EX
It is supplied to one input terminal of the OR gates 35, 36, 37 and 38. The H-level voltage is supplied from the terminal 35A to the other input terminals of the EX-OR gates 35 and 37. Further, the other input terminals of the EX-OR gates 36 and 38 are grounded. In addition, the EX-OR gates 35 to
The signal to the other input terminal of 38 is made variable according to the transmitted unique word UW.

EX-OR gates 35, 36, 37 and 3
8 and the clock pulse from the clock input terminal 40 (see FIG. 3D) and the clock pulse from the clock input terminal 41 (see FIG. 3C) are supplied to the shift register 39. The clock input terminal 41
Outputs a high-speed clock pulse of (n + 2) times (n is a unique word length) times the clock cycle of the serial data. In the shift register 39, parallel / serial conversion of data is performed, and the serial data is supplied to the up counter 42. Further, the high-speed clock pulse from the clock input terminal 41 via the inverter 43 and the clock pulse from the clock input terminal 44 (see FIG. 3E) are supplied to the up counter 42.

In the up counter 42, the initial value (error tolerance of the unique word UW) is set to (1101) by the initial value setting input terminal 42A. In other words, when this initial value is incremented to (1111),
A ripple carry bit is output from the up counter 42. The allowable error amount set in the up counter 42 is variable. It is also possible to use a down counter instead of the up counter.

The output signal of the up counter 42 is supplied to one input terminal of an RS flip-flop (hereinafter referred to as R-SFF) 45. The clock pulse (see FIG. 3F) from the clock input terminal 46 is supplied to the other input terminal of the R-SFF 45. The output signal of the R-SFF 45 is supplied to the DFF 47, and the clock pulse of the clock input terminal 33 is input to the clock input terminal of the DFF 47 via the inverter 48. Furthermore, DF
The H level voltage is supplied to the DFF 47 from the terminals 49 and 50 so that the F 47 is not set to the preset or cleared state. The output signal of the DFF 47 is output from the detection signal output terminal 51 as a unique word UW detection signal (see FIG. 3G).

In the above circuit, for example, when the unique word UW of (0101) is transmitted from the transmitting side,
The output signals of the EX-OR gates 35 to 38 are all set to "L" and supplied to the counter 42 via the shift register 39. This value is counted by the high speed clock pulse from the clock input terminal 41. Therefore, the signal supplied from the counter 42 to the R-SFF 45 is set to "L", and after being latched by the R-SFF 45, the DF
It is supplied to F47. The output signal of the R-SFF 45 is output as a unique word UW detection signal “H” from the DFF 47 at the timing of the clock pulse from the clock input terminal 33 via the inverter 48. Thereby, the unique word UW detection signal can be obtained.

Further, for example, a 1-bit error occurs in the unique word UW from the transmitting side, and the output signal of the EX-OR gate 35 is set to "H". As a result, the initial value of the counter 42 is incremented to (1110). Therefore, from the counter 42 to R
The signal supplied to the -SFF 45 is "L". The output signal of the counter 42 is latched by the R-SFF 45 and then supplied to the DFF 47. The output signal of the R-SFF 45 is supplied to the clock input terminal 33 via the inverter 48.
Is output as a unique word UW detection signal "H" from the DFF 47 at the timing of the clock pulse from. Thereby, the unique word UW detection signal can be obtained.

Further, a 2-bit error occurs from the data input terminal 31, the output signals of the EX-OR gates 37 and 38 are set to "H", and EX-
The output signals of the OR gates 35 and 36 are set to "L".
By the way, the initial value of the counter 42 is set to (1101), and when the second error bit is counted, the value of the up counter 42 is set to (1111).
At this point, the up counter 42 outputs the ripple carry bit at the “H” level, and the R-SFF 45
Is latched by. The output signal "L" of the R-SFF45 is
It is supplied to the DFF 47 and output as the unique word UW detection signal “L” at the timing of the clock pulse passed through the inverter 48. In this case, the unique word UW cannot be detected.

The initial value of the up counter 42 is set to (1
By changing from 101) to (1100), the error tolerance of the unique word UW can be reduced from 1 bit or less to 2 bits or less. In that case, when the third error bit is counted, the initial value is (11
11) and the ripple carry bit is supplied to the R-SFF 45. That is, when the second error bit is counted, the initial value is (1110), and therefore,
The ripple carry bit is not output from the up counter 42.

[0038]

According to the present invention, the unique word UW
Error is counted by the up counter, it is detected whether the count value exceeds the error tolerance set as the initial value, and the initial value of the counter (error tolerance) can be easily changed. It is said that. Therefore, the circuit scale can be reduced as compared with the conventional pattern detection circuit. In addition, wide expandability is possible when the error tolerance is changed. Furthermore, when the error tolerance is increased and the unique word UW length is increased, a particularly great effect can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a digital cellular telephone to which the present invention is applied.

FIG. 2 is a circuit diagram of a pattern detection circuit according to the present invention.

FIG. 3 is a timing chart of data, a clock pulse, and a unique word detection signal used in the pattern detection circuit.

FIG. 4 is a diagram showing a configuration of physical slots of a communication channel and a control channel.

FIG. 5 is a block diagram of a unique word UW detection circuit having no error tolerance.

FIG. 6 is a block diagram of a unique word UW detection circuit having an error allowance of 1 bit or less.

[Description of Reference Signs] 13 TDMA channel / dechannel coding circuit 35, 36, 37, 38 EX-OR gate 39 shift register 42 counter 42A initial value setting input terminal 51 detection signal output terminal

Claims (3)

[Claims] 1. A first means for converting an input signal to serial / parallel, a unique word detecting means for comparing a preset unique word with an output bit of the first means, and the unique word Output bits of word detection means in parallel /
Is there a second means for serial conversion and a terminal for setting an error allowance for the output bit of the second means, and is the error of the output bit of the second means less than or equal to the error allowance? A pattern detection device comprising a detection means for detecting whether or not there is output, and an output means for outputting an output bit of the detection means. 2. The pattern detecting apparatus according to claim 1, wherein the error tolerance of the detecting means is variable. 3. The pattern detecting apparatus according to claim 1, wherein the detecting means uses a clock pulse of (n + 2) times the clock cycle of the input signal (where n is a unique word length) or more.