JPH05307585A - Failure simulator - Google Patents

Abstract

PURPOSE:To perform high-speed fault simulation by making a circuit of a fault simulation algorithm to build it in an object circuit and simulating this object circuit on a logic simulation executing mechanism. CONSTITUTION:An input pattern inserting part 1 inserts an input pattern to a circuit simulation part 3. A fault data inserting part 2 inserts fault data, which a fault data extracting part 6 extracts from a fault list 8, to a circuit simulation part 3. A fault drop part 5 removes fault data, which can be detected, from the fault list 8. For example, the object circuit is converted to a fault simulation circuit to increase the number of gates from 5 to 20. That is, the number of gates is increased four times, but the fault simulation speed is very increased when this logic simulation executing mechanism is used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault simulation system for combinational circuits. When manufacturing a VLSI, it is necessary to generate a test pattern for product defect inspection at the design stage. The fault simulation is performed to check how many faults the test pattern obtained by the test pattern generation can detect.

The fault simulation may also be used as a pre-process for detecting a fault that is easily detected from a random input pattern in test pattern generation.

[0003]

2. Description of the Related Art Conventionally used fault simulation is realized by software of a general-purpose computer. FIG. 13 is a diagram for explaining the failure simulation. The failure simulation is performed on the target circuit 103,
When certain input patterns 100 and 101 are given to 104, it is checked whether the output result 105 of the normal target circuit 104 and the output result 106 of the target circuit 103 in which the failure data 102 are inserted are the same or different. To do.

If output result 105 and output result 106
, And the input pattern 100, 1
It can be said that 01 can detect the failure in the target circuits 103 and 104. However, the output result 105
If the output result 106 is the same, it can be said that the input patterns 100 and 101 cannot detect the failure in the target circuits 103 and 104. This fault needs to be detected by another input pattern.

FIG. 14 shows a block diagram of the failure simulator. The failure simulator 110 receives the circuit data 111 of the target circuit, the input pattern 112, and the failure data 113 from the user. The fault simulator 110 has therein a mechanism for performing a logic simulation of a target circuit, and performs a logic simulation of a normal circuit and a fault circuit.

Further, the fault simulator 110 has a mechanism for checking whether or not a fault has been detected from the result of the logic simulation, and a mechanism for supplying an input to the target circuit. FIG. 15 is a flowchart illustrating a fault simulation algorithm performed by a general fault simulator. In the figure, reference marks S150 to S159 starting with the letter S
Represents a process number, and the process number will be shown in parentheses after the corresponding description.

First, it is checked whether or not there is an input pattern which has not been simulated yet in the input pattern list 114. If not, the process ends there (S150). In the next step, the input pattern is given to the target circuit (S151). Here, the target circuit logic simulation 116 performs a logic simulation of a normal circuit (S152).

Then, the target circuit logic simulation 1
16 performs a logic simulation with no fault inserted. The logical value of the output of the target circuit at this time is stored as the normal circuit output 117.

Next, it is checked whether or not there is a failure that has not been inserted in the failure data list 115. If all the faults have been inserted, the process returns to S150 to insert a new input pattern (S15).
3). In the next step, a fault is inserted in the target circuit (S154). This fault insertion means rewriting the logical value of the signal line of the target circuit from outside the target circuit.

When the fault is inserted, a logic simulation is performed. Here, the event generated in the target circuit due to the insertion of the fault is processed (S155).
The logical value of the output of the target circuit at this time is stored as the fault circuit output 118.

Subsequently, the comparison means 119 is used to compare the logical values of the normal circuit output 117 and the fault circuit output 118 to check whether a fault can be detected (S156). If the comparison results are different, it is possible to detect the fault inserted at that time by the input pattern given to the target circuit at that time.

Faults that can be detected are dropped and removed from the fault data list (S15).
7). A fault that can be detected once does not need to be examined whether it can be detected by another input pattern. Therefore, the failure data that can be detected is deleted from the undetected failure list, which is a table of failure data. What is a failure drop?
The process of deleting the detected failure data from the undetected failure list.

In the step following the failure drop, it is checked whether or not all the failure data given first can be detected. If no failure data remains in the undetected list and all the failures have been detected, the failure simulation ends (S158).

If the fault data still remains, the fault is deleted (S159) and the process returns to S153.
The remaining failure data is simulated. Fault deletion refers to rewriting the logical value of the signal line rewritten by the fault insertion in S154 to the state before the fault insertion. That is, by performing this process, all the logical values in the target circuit return to the same state as in the normal circuit.

[0015]

Since the conventional failure simulator described above is composed of software, its processing requires a huge amount of time. Further, with the recent increase in scale of design circuits, the processing time tends to increase more and more.

By the way, a logic simulator execution mechanism is becoming popular as a CAD tool at present. This is a hardware tool that performs logical simulation, and currently there are dedicated machines and hardware emulators.

The dedicated machine is a machine having an architecture optimized for high-speed execution of logic simulation, and executes operations of logic simulation, which have been realized by software until then, in parallel by hardware. This is a method that achieves high speed.

The hardware emulator is hardware that implements a target circuit in a programmable manner, and implements a logic simulation by constructing a circuit having the same circuit structure as the target circuit on the hardware. These logic simulation execution mechanisms are 1000 times to 1 times as compared with the logic simulation by software.
Boasts an execution speed of, 000,000 times.

Even in the fault simulation, a dedicated machine exists like the logic simulation. But,
In contrast to the logical simulation for checking whether the design circuit operates according to the specifications in hardware development, the failure simulation has a problem that the cost is high because the execution frequency is extremely low and the configuration is complicated.

The present invention is intended to perform a fault simulation using a logic simulation execution mechanism. That is, an object of the present invention is to realize a very high-speed fault simulation by converting the fault simulation algorithm into a circuit, incorporating it into a target circuit, and simulating it on a logic simulation execution mechanism.

[0021]

According to the present invention, the above object is achieved by means as set forth in the claims. That is, the present invention examines whether various input patterns created to detect any fault existing in the fault list can actually detect individual faults, and as a result, A device for performing a fault simulation using the input pattern, which has a logic simulation executing mechanism, and which performs a logic simulation of a normal target circuit and a target circuit in which a fault is inserted, and a circuit simulation unit. It is a failure simulator including an output inspection unit that inspects whether an influence of a failure has occurred on an output.

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, a circuit simulation unit 3 and an output inspection unit 4
Is implemented on the fault simulation circuit, that is, the logic simulation execution mechanism, and the others are processed by the host.

[0023]

In FIG. 1, the input pattern inserting section 1 inserts the input pattern 7 into the circuit simulation section 3. In the fault data insertion unit 2, the fault data extraction 6 is the fault list 8
The failure data extracted from the circuit simulation unit 3
To insert. The failure drop 5 removes failure data that can be detected from the failure list 8.

FIG. 2 is a diagram for explaining the concept of the present invention. The circuit data 10, the input pattern 12, and the failure data 11 are necessary for executing the failure simulation. The host machine 19 converts the data into the data of the circuit that executes the failure simulation on the logic simulation execution mechanism, that is, the failure simulation circuit data 14 by the circuit conversion 13.

The converted circuit data is subjected to a logic simulation 15 on the logic simulation executing mechanism 20.
The logical simulation result 16 is the result of the host machine 1
Send to 9. The host machine 19 analyzes the logic simulation result 16 and obtains the failure simulation result 18 by the data conversion 17.

FIG. 3 shows a conceptual diagram for converting the target circuit into the circuit simulation section of the failure simulation circuit. The circuit simulation unit receives the input pattern and the failure data as its input. The processing performed by the circuit simulation unit is the logic simulation of the target circuit and the insertion and deletion of a fault in the target circuit.

The processing of (1) may be realized by directly implementing the target circuit on the logic simulation executing mechanism.
However, the process of (3) is performed on each gate 33 to 3 of the target circuit.
It is necessary to convert the input and output lines of No. 5 into circuits in which the failure data 30 to 32 can be inserted and deleted. Figure 3
(B) shows the fault data 36 to 38 and the gates 39 to 41 after the circuit conversion.

FIG. 4 shows the gate conversion of the target circuit based on the failure data. The stuck-at fault model is generally used as the fault model used in the fault simulation. The stuck-at fault model is a fault model in which the logical value of the input / output line of the element is fixed to "1" or "0".

As shown in FIG. 4, as failure data for the AND gate 45 of the target circuit, "S.
A. When there is failure data "1", for example, a new input f is added by conversion to obtain the gate circuit 46 that satisfies the truth table shown in FIG.

FIG. 5 shows a configuration example of the output inspection unit. The output inspection unit 50 compares the logical value of the output of the target circuit when the fault is not inserted with the logical value of the output when the fault is inserted in the target circuit, and determines whether the influence of the fault can be detected from the result. Find out.

In FIG. 5, the switching unit 51 determines whether to set the output in the comparison unit 52 or the storage unit 53 according to a select signal from the host. The storage unit 52 stores the logic of the circuit output from the comparison unit 53 only when there is a write signal from the host. The comparison unit 53 compares the logic stored in the storage unit 52 with the logic from the switching unit 51.

The detection unit 54 checks from the comparison result of the comparison unit 53 whether or not any one of the output pins of the target circuit has a failure, and the detection synchronization clock is sent from the host. The result is sent to the host only at the timing.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of processing in the host during operation of the logic simulation execution mechanism is shown in the flow chart of FIG. In FIG. 6, it is first checked whether there is an input pattern, and if there is no input pattern, this is set as the end condition (S6).
0). If there is an input pattern, a normal circuit simulation is performed in the next step (S61), and then a fault circuit simulation is performed (S62).

In the normal circuit simulation, an input pattern is given to the target circuit and a logic simulation of the normal circuit is performed. The details will be described later. On the other hand, in the fault circuit simulation, a fault is given to the normal circuit,
Check if the circuit output has changed. This processing is performed for all the failure data held, and details thereof will be described later.

FIG. 7 shows an example of a normal circuit simulation. In the normal circuit simulation of FIG. 7, first, an input pattern is given (S70), and then simulation is performed by the logic simulation execution mechanism processing (S71). Here, the event generated by the input pattern is evaluated.

Next, the circuit output of the switching unit in the output inspection unit is set to be the storage unit (S72). That is, the output of the target circuit is made to flow to the storage section of the output inspection section. Then, the write signal to the storage section of the output inspection section is set (S73). Here, in order to save the normal circuit output logic, a procedure for storing the output logic that has been sent is performed.

The next step is the logic simulation execution mechanism process, which stores the normal circuit output logic (S7).
4). Then, finally, the write signal given to the storage section of the output inspection section is released (S75).

An example of a fault circuit simulation is shown in FIGS. In the example of the fault circuit simulation of FIG. 8, first, it is checked whether there is a fault that has not been simulated. That is, it is checked whether there is any failure data in the undetected failure list in the given input pattern that has not been subjected to the failure circuit simulation. If not, the fault circuit simulation is ended, and a normal circuit simulation is performed with another input pattern (S80).

Next, failure data is extracted. this is,
From the undetected failure list, failure data that has not been inserted yet is retrieved (S81). Then, the fault insertion is performed. This is to insert the failure data extracted from the undetected list into the circuit simulation unit (S82).

Subsequently, a simulation is performed by the circuit simulation section using the logic simulation execution mechanism. Here, the event that has occurred is evaluated from the inserted failure (S83).

Next, the output inspection unit sets the circuit output of the switching unit to the comparison unit (S84). For example, a select signal is sent to the logic simulation execution mechanism so that the output of the switching unit of the output inspection unit is sent to the comparison unit. In the output inspection unit, for example, the comparison unit compares the stored normal circuit output logic with the circuit output after the fault insertion by using the logic simulation execution mechanism (S85).

Then, a detection synchronization clock is given to the output inspection section (S86). In the output inspection unit, the logic simulation execution mechanism is used, and the detection unit outputs a failure detection signal according to the data from the comparator (S87).
This failure detection signal is sent to the host.

FIG. 9 is a flow chart connecting to FIG. In the first process shown in FIG. 9, it is checked whether a failure has been detected (S90). Then, if a failure is detected based on the failure detection signal sent from the logic simulation execution mechanism, the next failure drop processing is performed (S91). In this failure drop, the detected failure is deleted from the undetected failure list.

Then, it is checked whether or not all the failures have been detected (S92). Check if there are any undetected faults in the undetected fault list, and if all are detected,
If the failure simulation is completed and all are not detected, the process proceeds to the next failure deletion process (S93). Here, in order to return the target circuit to the same state as after the normal circuit failure simulation, the location where the failure is inserted is returned to the state before the insertion.

In the final processing shown in FIG. 9, a simulation is performed by the circuit simulation section (S9).
4). It uses a logic simulation executive to evaluate the events caused by fault elimination.

An example of expanding the target circuit into a failure simulation circuit will be described below. First, an example of the target circuit is shown in FIG. This target circuit has inputs I ₁ , I ₂ , I
₃ , I ₄ , and outputs O ₁ and O _2, and also has five gates 60-64.

It is assumed that the failure data gives "SA failure" to the portion indicated by "X".
“S.A. failure” means that for the location where the failure is inserted,
It is a failure model in which the logic is fixed to "0" or "1".
“S.A.1” is a fault whose logic is fixed at “1”,
On the other hand, “S.A.0” is a fault whose logic is fixed at “0”.

FIG. 11 shows a circuit simulation section of the fault simulation circuit after conversion for the target circuit shown in FIG. In FIG. 11, new gates 75 to 83 for inserting failure data are provided at the locations indicated by “x” in FIG. Note that FIG.
Gates 60-64 of 0 correspond to the gates 70-74 of FIG. 11, respectively.

The faults inserted in the input of the gate 73 and the input of the gate 74 are equivalent faults which can be detected with the same input patterns as the faults inserted in the output of the gate 73 and the output of the gate 74, respectively. Therefore, in this example, the failure data inserted in the input of the gate 73 and the input of the gate 74 are deleted. This processing is performed at the stage of failure data generation.

By the way, "SA.1" is a 2-input OR.
The gate, or "S.A.0", can be replaced by a 2-input AND gate. Therefore, a fault can be inserted by applying a logic "1" to one of the inputs of those gates.

FIG. 12 shows an example in which the output inspection unit is actually converted into a logic circuit. In the case of FIG. 12, the switching unit includes five gates 86 to 90. Further, the storage unit is composed of two registers 91 and 92, the comparison unit is composed of two gates 93 and 94, and the detection unit is composed of two gates 95 and 96.

In FIG. 12, the output inspecting section sends a detection synchronization clock, a write signal, and a select signal from the host.
Also, as the target circuit output from the circuit simulation unit,
Receives O ₁ and O ₂ . The switching unit serves as a selector, and switches the output destination from the select signal. The storage unit is composed of a register, and uses a clock input of the register as a write signal.

In the comparison section, by taking the NAND of the logic of the storage section and the logic of the circuit simulation output,
Check if the two logics match. The detection unit detects the case where even one output logic does not match by taking the logical sum of all the results of the comparison unit. Then, according to the detection synchronization clock from the host, the detection result is sent to the host as a failure detection signal.

[0054]

In the circuit example shown in FIG. 10, the number of gates is changed from 5 gates 60 to 64 to 20 gates 75 to 8 by converting the target circuit into a failure simulation circuit.
It increased to 3,86-96. That is, although it increases four times, the fault simulation according to the present invention is very fast because the present invention uses the logic simulation execution mechanism.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating the concept of the present invention.

FIG. 3 is a diagram illustrating circuit conversion.

FIG. 4 is a diagram illustrating the concept of gate conversion.

FIG. 5 is a diagram illustrating a configuration example of an output inspection unit.

FIG. 6 is a flowchart showing an embodiment of the present invention.

FIG. 7 is a flowchart showing an example of a normal circuit simulation method.

FIG. 8 is a flowchart showing an example of a fault circuit simulation method.

9 is a flow chart connecting to FIG. 8. FIG.

FIG. 10 is a diagram showing an example of a target circuit.

FIG. 11 is a diagram illustrating an example of a circuit simulation unit.

FIG. 12 is a diagram showing a conversion example of an output inspection unit.

FIG. 13 is a diagram illustrating a failure simulation.

FIG. 14 is a diagram showing a configuration of a failure simulator.

FIG. 15 is a flowchart illustrating a failure simulation algorithm.

[Explanation of symbols]

1 Input Pattern Insertion Section 2 Failure Data Insertion Section 3 Circuit Simulation Section 4,50 Output Inspection Section 5 Failure Drop 6 Failure Data Extraction 7, 12, 100, 101, 112 Input Pattern 8 Failure List 10, 111 Circuit Data 11, 30 ~ 32, 36-38, 102, 113 Fault data 13 Circuit conversion 14 Fault simulation circuit data 15 Logic simulation 16 Logic simulation result 17 Data conversion 18 Fault simulation result 19 Host machine 20 Logic simulation execution mechanism 33-35, 39-41, 45 , 46, 60-64, 7
0-83, 86-90, 93-96 gate 51 switching unit 52 storage unit 53 comparing unit 54 detecting unit 91, 92 register 103, 104 target circuit 105, 106 output result 110 fault simulator 114 input pattern list 115 fault data list 116 Target circuit logic simulation 117 Normal circuit output 118 Fault circuit output 119 Comparison means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G06F 15/20 D 7218-5L

Claims (1)

[Claims] 1. A variety of input patterns (7) created to detect an arbitrary fault existing in a fault list (8),
A device for investigating whether or not an individual fault can be actually detected, and performing a fault simulation using the input pattern obtained as a result, which has a logic simulation execution mechanism and is a normal target. A circuit simulation unit (3) that performs a logic simulation of a circuit and a target circuit in which a fault is inserted, and an output inspection unit (4) that inspects the output of the circuit simulation unit for the influence of the fault. Failure simulator characterized by.