JPH05308263A - Digital phase comparator - Google Patents

Abstract

PURPOSE:To provide the digital phase comparator not needing an external clock with small sized circuit configuration by providing a delay circuit comprising twin inverters connected in cascade and a latch circuit latching outputs of the delay circuits to the phase comparator. CONSTITUTION:Twin inverter groups 3-1-3-n each consists of inverters 1,2 delaying and inverting input signals 4-1-4-n-1 sequentially. A reference input signal 4-1 is inverted from an L level to an H level at a time T1. The twin inverter groups 3-1-3-n delay sequentially the reference input signal 4-1 and output delay output signals 4-2-4-n. The delay output signals 4-2-4-n are latched at a rising edge of a comparison input signal 6 by a latch group 7 at a time T2. Then digital phase difference outputs 5-1-5-n corresponding to the phase difference between the reference input signal 4-1 and the comparison input signal 6 are outputted between the times T1 and T2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase comparator, and more particularly to a digital phase comparator which is constructed by using a delay circuit composed of twin inverters and is used for phase comparison of digital signals.

[0002]

2. Description of the Related Art FIG. 3 shows the configuration of an example of a digital phase comparator which is generally used conventionally. Two digital signals from the terminals 55 and 56 for phase comparison,
That is, the reference input signal 110 and the comparison input signal 111 are E
It is input to the XOR gate 10, and the output 112 of the EXOR gate 10 is input to the AND gate 11. Also AND
A predetermined holding signal 114 input from the terminal 57 and the oscillation output of the oscillator 12 are also input to the gate 11.
The logical product 115 corresponding to these three inputs is input to the shift registers 13-1 to 13-n as a clock input.

On the other hand, the shift registers 13-1 to 13-n
A reset signal 113 is input to the shift register 13-1 to 13-n through a terminal 58, and a predetermined power source is connected to the data input side of the shift registers 13-1 to 13-n.

4 (a), (b), (c), (d),
(E), (f) and (g) are operation timing charts related to a main signal in the conventional example. In response to the fall of the reset signal 113 at time T ₁ , the shift registers 13-1 to 13-n are ready for the data shift operation, and the rise of the reference input signal 110 at time T ₂ is compared with that at time T ₃ . In response to the rising of the input signal 111, the output 112 of the EXOR gate 10 has a time T
It is output as an H level signal from ₂ to T ₃ . AN
In the D gate 11, the output 1 of the EXOR gate 10
12, the hold signal 114 and the oscillation output of the oscillator 12 are received, and as shown in FIG. 4 (f), the oscillation output of the oscillator 12 is output as the AND gate output 115 from the time T ₂ to the time T _2.
It is output for ₃ times.

As described above, in response to the falling of the reset signal 113 at the time T _1, in the shift registers 13-1 to 13-n which are in the state where the data shift operation is possible, the AND gate 11 outputs the data. A predetermined shift operation is performed in response to the oscillation output (time T _{2 to} T ₃ ), and the H level output signal 116 is sequentially output via the terminals 59-1 to 59-n. As shown in FIG. 4E, the output signal 116 output via the terminals 59-1 to 59-n in response to the fall of the hold signal 114 at time T ₄ .
By holding the level of, the digital output corresponding to the phase difference of the input signal can be obtained.

[0006]

However, in the above-mentioned conventional digital phase comparator, generally, the number of components required for realizing the circuit is large, which is economically disadvantageous and is a target of phase comparison. There is a drawback in that it is necessary to input a predetermined clock signal in addition to the two digital signals that are input.

Therefore, in view of the above-mentioned drawbacks, a technical problem of the present invention is to provide a digital phase comparator which does not require an external clock and is simplified and has a small circuit configuration.

[0008]

According to the present invention, a delay circuit in which a reference input signal is connected to an input of a twin inverter group in which twin inverters are cascade-connected, and an output of the twin inverter group is generated by a comparison input signal. It is possible to obtain a digital phase comparator which is provided with a latch circuit group for latching each and obtains a digital phase difference output from each of these latch circuit groups.

That is, the digital phase comparator of the present invention is
It is provided with a twin inverter group in which twin inverters for inputting a reference input signal and delaying and outputting are continuously connected, and a latch circuit group for latching an output of the twin inverter group according to a comparison input signal.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a twin inverter group 3-1 to 3-1 composed of inverters 1 and 2 that sequentially delay and output a reference input signal 4-1 is output.
3-n and the output of the twin inverter groups 3-1 to 3-n are latched at the rising edge of the comparison input signal 6 and the output 5-1 to 5-n of the latch circuit group 7 is digital phase difference. It is composed of a circuit to be an output.

2A to 2I are operation timing charts in this embodiment. 2A to 2I, the twin inverter group 3 receives the inversion of the reference input signal 4-1 from the L level to the H level at the time T ₁ .
-1 to 3-n output delayed output signals 4-2 to 4-n which are obtained by sequentially delaying and outputting the reference input signal 4-1. The delayed output signals 4-2 to 4-n are latched by the latch circuit group 7 at time T ₂ , and the phase difference between the reference input signal 4-1 and the comparison input signal 6 is obtained during the time T ₁ to T _2. Corresponding digital values 5-1 to 5-n are output.

The latch circuit group 7 is initialized in response to the rising edge of the reset signal 8 at time T ₃ .

[0014]

As described above, according to the present invention, the delay circuit formed by the twin inverters connected in cascade and the latch circuit for latching the output of each delay circuit are provided, so that an external clock is unnecessary. There is an effect that it is possible to simply provide a digital phase comparator with a small-scale circuit configuration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is an operation timing chart in the embodiment of FIG.

FIG. 3 is a circuit diagram of a conventional digital phase comparator.

FIG. 4 is an operation timing chart in the example of FIG.

[Explanation of symbols]

 1, 2 inverter 3-1 to 3-n twin inverter 110, 4-1 reference input signal 4-2 to 4-n delay output 116, 5-1 to 5-n digital phase difference output 6, 111 comparison input signal 7 Latch circuit group 59-1 to 59-n Output terminal 13-1 to 13-n Shift register 10 EXOR gate 11 AND gate 12 Oscillator 114 Holding signal 8,113 Reset signal

Claims (1)

[Claims] 1. A delay circuit in which a reference input signal is connected to an input of a twin inverter group in which twin inverters in which two inverters are cascaded are connected in series, and an output of the twin inverter group is latched by a comparison input signal. And a latch circuit group for performing digital phase difference output from each of the latch circuit groups.